1 /* 2 * ARM GICv3 support - internal interfaces 3 * 4 * Copyright (c) 2012 Linaro Limited 5 * Copyright (c) 2015 Huawei. 6 * Copyright (c) 2015 Samsung Electronics Co., Ltd. 7 * Written by Peter Maydell 8 * Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation, either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #ifndef QEMU_ARM_GICV3_INTERNAL_H 25 #define QEMU_ARM_GICV3_INTERNAL_H 26 27 #include "hw/registerfields.h" 28 #include "hw/intc/arm_gicv3_common.h" 29 30 /* Distributor registers, as offsets from the distributor base address */ 31 #define GICD_CTLR 0x0000 32 #define GICD_TYPER 0x0004 33 #define GICD_IIDR 0x0008 34 #define GICD_STATUSR 0x0010 35 #define GICD_SETSPI_NSR 0x0040 36 #define GICD_CLRSPI_NSR 0x0048 37 #define GICD_SETSPI_SR 0x0050 38 #define GICD_CLRSPI_SR 0x0058 39 #define GICD_SEIR 0x0068 40 #define GICD_IGROUPR 0x0080 41 #define GICD_ISENABLER 0x0100 42 #define GICD_ICENABLER 0x0180 43 #define GICD_ISPENDR 0x0200 44 #define GICD_ICPENDR 0x0280 45 #define GICD_ISACTIVER 0x0300 46 #define GICD_ICACTIVER 0x0380 47 #define GICD_IPRIORITYR 0x0400 48 #define GICD_ITARGETSR 0x0800 49 #define GICD_ICFGR 0x0C00 50 #define GICD_IGRPMODR 0x0D00 51 #define GICD_NSACR 0x0E00 52 #define GICD_SGIR 0x0F00 53 #define GICD_CPENDSGIR 0x0F10 54 #define GICD_SPENDSGIR 0x0F20 55 #define GICD_IROUTER 0x6000 56 #define GICD_IDREGS 0xFFD0 57 58 /* GICD_CTLR fields */ 59 #define GICD_CTLR_EN_GRP0 (1U << 0) 60 #define GICD_CTLR_EN_GRP1NS (1U << 1) /* GICv3 5.3.20 */ 61 #define GICD_CTLR_EN_GRP1S (1U << 2) 62 #define GICD_CTLR_EN_GRP1_ALL (GICD_CTLR_EN_GRP1NS | GICD_CTLR_EN_GRP1S) 63 /* Bit 4 is ARE if the system doesn't support TrustZone, ARE_S otherwise */ 64 #define GICD_CTLR_ARE (1U << 4) 65 #define GICD_CTLR_ARE_S (1U << 4) 66 #define GICD_CTLR_ARE_NS (1U << 5) 67 #define GICD_CTLR_DS (1U << 6) 68 #define GICD_CTLR_E1NWF (1U << 7) 69 #define GICD_CTLR_RWP (1U << 31) 70 71 /* 16 bits EventId */ 72 #define GICD_TYPER_IDBITS 0xf 73 74 /* 75 * Redistributor frame offsets from RD_base 76 */ 77 #define GICR_SGI_OFFSET 0x10000 78 79 /* 80 * Redistributor registers, offsets from RD_base 81 */ 82 #define GICR_CTLR 0x0000 83 #define GICR_IIDR 0x0004 84 #define GICR_TYPER 0x0008 85 #define GICR_STATUSR 0x0010 86 #define GICR_WAKER 0x0014 87 #define GICR_SETLPIR 0x0040 88 #define GICR_CLRLPIR 0x0048 89 #define GICR_PROPBASER 0x0070 90 #define GICR_PENDBASER 0x0078 91 #define GICR_INVLPIR 0x00A0 92 #define GICR_INVALLR 0x00B0 93 #define GICR_SYNCR 0x00C0 94 #define GICR_IDREGS 0xFFD0 95 96 /* SGI and PPI Redistributor registers, offsets from RD_base */ 97 #define GICR_IGROUPR0 (GICR_SGI_OFFSET + 0x0080) 98 #define GICR_ISENABLER0 (GICR_SGI_OFFSET + 0x0100) 99 #define GICR_ICENABLER0 (GICR_SGI_OFFSET + 0x0180) 100 #define GICR_ISPENDR0 (GICR_SGI_OFFSET + 0x0200) 101 #define GICR_ICPENDR0 (GICR_SGI_OFFSET + 0x0280) 102 #define GICR_ISACTIVER0 (GICR_SGI_OFFSET + 0x0300) 103 #define GICR_ICACTIVER0 (GICR_SGI_OFFSET + 0x0380) 104 #define GICR_IPRIORITYR (GICR_SGI_OFFSET + 0x0400) 105 #define GICR_ICFGR0 (GICR_SGI_OFFSET + 0x0C00) 106 #define GICR_ICFGR1 (GICR_SGI_OFFSET + 0x0C04) 107 #define GICR_IGRPMODR0 (GICR_SGI_OFFSET + 0x0D00) 108 #define GICR_NSACR (GICR_SGI_OFFSET + 0x0E00) 109 110 #define GICR_CTLR_ENABLE_LPIS (1U << 0) 111 #define GICR_CTLR_RWP (1U << 3) 112 #define GICR_CTLR_DPG0 (1U << 24) 113 #define GICR_CTLR_DPG1NS (1U << 25) 114 #define GICR_CTLR_DPG1S (1U << 26) 115 #define GICR_CTLR_UWP (1U << 31) 116 117 #define GICR_TYPER_PLPIS (1U << 0) 118 #define GICR_TYPER_VLPIS (1U << 1) 119 #define GICR_TYPER_DIRECTLPI (1U << 3) 120 #define GICR_TYPER_LAST (1U << 4) 121 #define GICR_TYPER_DPGS (1U << 5) 122 #define GICR_TYPER_PROCNUM (0xFFFFU << 8) 123 #define GICR_TYPER_COMMONLPIAFF (0x3 << 24) 124 #define GICR_TYPER_AFFINITYVALUE (0xFFFFFFFFULL << 32) 125 126 #define GICR_WAKER_ProcessorSleep (1U << 1) 127 #define GICR_WAKER_ChildrenAsleep (1U << 2) 128 129 FIELD(GICR_PROPBASER, IDBITS, 0, 5) 130 FIELD(GICR_PROPBASER, INNERCACHE, 7, 3) 131 FIELD(GICR_PROPBASER, SHAREABILITY, 10, 2) 132 FIELD(GICR_PROPBASER, PHYADDR, 12, 40) 133 FIELD(GICR_PROPBASER, OUTERCACHE, 56, 3) 134 135 FIELD(GICR_PENDBASER, INNERCACHE, 7, 3) 136 FIELD(GICR_PENDBASER, SHAREABILITY, 10, 2) 137 FIELD(GICR_PENDBASER, PHYADDR, 16, 36) 138 FIELD(GICR_PENDBASER, OUTERCACHE, 56, 3) 139 FIELD(GICR_PENDBASER, PTZ, 62, 1) 140 141 #define ICC_CTLR_EL1_CBPR (1U << 0) 142 #define ICC_CTLR_EL1_EOIMODE (1U << 1) 143 #define ICC_CTLR_EL1_PMHE (1U << 6) 144 #define ICC_CTLR_EL1_PRIBITS_SHIFT 8 145 #define ICC_CTLR_EL1_PRIBITS_MASK (7U << ICC_CTLR_EL1_PRIBITS_SHIFT) 146 #define ICC_CTLR_EL1_IDBITS_SHIFT 11 147 #define ICC_CTLR_EL1_SEIS (1U << 14) 148 #define ICC_CTLR_EL1_A3V (1U << 15) 149 150 #define ICC_PMR_PRIORITY_MASK 0xff 151 #define ICC_BPR_BINARYPOINT_MASK 0x07 152 #define ICC_IGRPEN_ENABLE 0x01 153 154 #define ICC_CTLR_EL3_CBPR_EL1S (1U << 0) 155 #define ICC_CTLR_EL3_CBPR_EL1NS (1U << 1) 156 #define ICC_CTLR_EL3_EOIMODE_EL3 (1U << 2) 157 #define ICC_CTLR_EL3_EOIMODE_EL1S (1U << 3) 158 #define ICC_CTLR_EL3_EOIMODE_EL1NS (1U << 4) 159 #define ICC_CTLR_EL3_RM (1U << 5) 160 #define ICC_CTLR_EL3_PMHE (1U << 6) 161 #define ICC_CTLR_EL3_PRIBITS_SHIFT 8 162 #define ICC_CTLR_EL3_IDBITS_SHIFT 11 163 #define ICC_CTLR_EL3_SEIS (1U << 14) 164 #define ICC_CTLR_EL3_A3V (1U << 15) 165 #define ICC_CTLR_EL3_NDS (1U << 17) 166 167 #define ICH_VMCR_EL2_VENG0_SHIFT 0 168 #define ICH_VMCR_EL2_VENG0 (1U << ICH_VMCR_EL2_VENG0_SHIFT) 169 #define ICH_VMCR_EL2_VENG1_SHIFT 1 170 #define ICH_VMCR_EL2_VENG1 (1U << ICH_VMCR_EL2_VENG1_SHIFT) 171 #define ICH_VMCR_EL2_VACKCTL (1U << 2) 172 #define ICH_VMCR_EL2_VFIQEN (1U << 3) 173 #define ICH_VMCR_EL2_VCBPR_SHIFT 4 174 #define ICH_VMCR_EL2_VCBPR (1U << ICH_VMCR_EL2_VCBPR_SHIFT) 175 #define ICH_VMCR_EL2_VEOIM_SHIFT 9 176 #define ICH_VMCR_EL2_VEOIM (1U << ICH_VMCR_EL2_VEOIM_SHIFT) 177 #define ICH_VMCR_EL2_VBPR1_SHIFT 18 178 #define ICH_VMCR_EL2_VBPR1_LENGTH 3 179 #define ICH_VMCR_EL2_VBPR1_MASK (0x7U << ICH_VMCR_EL2_VBPR1_SHIFT) 180 #define ICH_VMCR_EL2_VBPR0_SHIFT 21 181 #define ICH_VMCR_EL2_VBPR0_LENGTH 3 182 #define ICH_VMCR_EL2_VBPR0_MASK (0x7U << ICH_VMCR_EL2_VBPR0_SHIFT) 183 #define ICH_VMCR_EL2_VPMR_SHIFT 24 184 #define ICH_VMCR_EL2_VPMR_LENGTH 8 185 #define ICH_VMCR_EL2_VPMR_MASK (0xffU << ICH_VMCR_EL2_VPMR_SHIFT) 186 187 #define ICH_HCR_EL2_EN (1U << 0) 188 #define ICH_HCR_EL2_UIE (1U << 1) 189 #define ICH_HCR_EL2_LRENPIE (1U << 2) 190 #define ICH_HCR_EL2_NPIE (1U << 3) 191 #define ICH_HCR_EL2_VGRP0EIE (1U << 4) 192 #define ICH_HCR_EL2_VGRP0DIE (1U << 5) 193 #define ICH_HCR_EL2_VGRP1EIE (1U << 6) 194 #define ICH_HCR_EL2_VGRP1DIE (1U << 7) 195 #define ICH_HCR_EL2_TC (1U << 10) 196 #define ICH_HCR_EL2_TALL0 (1U << 11) 197 #define ICH_HCR_EL2_TALL1 (1U << 12) 198 #define ICH_HCR_EL2_TSEI (1U << 13) 199 #define ICH_HCR_EL2_TDIR (1U << 14) 200 #define ICH_HCR_EL2_EOICOUNT_SHIFT 27 201 #define ICH_HCR_EL2_EOICOUNT_LENGTH 5 202 #define ICH_HCR_EL2_EOICOUNT_MASK (0x1fU << ICH_HCR_EL2_EOICOUNT_SHIFT) 203 204 #define ICH_LR_EL2_VINTID_SHIFT 0 205 #define ICH_LR_EL2_VINTID_LENGTH 32 206 #define ICH_LR_EL2_VINTID_MASK (0xffffffffULL << ICH_LR_EL2_VINTID_SHIFT) 207 #define ICH_LR_EL2_PINTID_SHIFT 32 208 #define ICH_LR_EL2_PINTID_LENGTH 10 209 #define ICH_LR_EL2_PINTID_MASK (0x3ffULL << ICH_LR_EL2_PINTID_SHIFT) 210 /* Note that EOI shares with the top bit of the pINTID field */ 211 #define ICH_LR_EL2_EOI (1ULL << 41) 212 #define ICH_LR_EL2_PRIORITY_SHIFT 48 213 #define ICH_LR_EL2_PRIORITY_LENGTH 8 214 #define ICH_LR_EL2_PRIORITY_MASK (0xffULL << ICH_LR_EL2_PRIORITY_SHIFT) 215 #define ICH_LR_EL2_GROUP (1ULL << 60) 216 #define ICH_LR_EL2_HW (1ULL << 61) 217 #define ICH_LR_EL2_STATE_SHIFT 62 218 #define ICH_LR_EL2_STATE_LENGTH 2 219 #define ICH_LR_EL2_STATE_MASK (3ULL << ICH_LR_EL2_STATE_SHIFT) 220 /* values for the state field: */ 221 #define ICH_LR_EL2_STATE_INVALID 0 222 #define ICH_LR_EL2_STATE_PENDING 1 223 #define ICH_LR_EL2_STATE_ACTIVE 2 224 #define ICH_LR_EL2_STATE_ACTIVE_PENDING 3 225 #define ICH_LR_EL2_STATE_PENDING_BIT (1ULL << ICH_LR_EL2_STATE_SHIFT) 226 #define ICH_LR_EL2_STATE_ACTIVE_BIT (2ULL << ICH_LR_EL2_STATE_SHIFT) 227 228 #define ICH_MISR_EL2_EOI (1U << 0) 229 #define ICH_MISR_EL2_U (1U << 1) 230 #define ICH_MISR_EL2_LRENP (1U << 2) 231 #define ICH_MISR_EL2_NP (1U << 3) 232 #define ICH_MISR_EL2_VGRP0E (1U << 4) 233 #define ICH_MISR_EL2_VGRP0D (1U << 5) 234 #define ICH_MISR_EL2_VGRP1E (1U << 6) 235 #define ICH_MISR_EL2_VGRP1D (1U << 7) 236 237 #define ICH_VTR_EL2_LISTREGS_SHIFT 0 238 #define ICH_VTR_EL2_TDS (1U << 19) 239 #define ICH_VTR_EL2_NV4 (1U << 20) 240 #define ICH_VTR_EL2_A3V (1U << 21) 241 #define ICH_VTR_EL2_SEIS (1U << 22) 242 #define ICH_VTR_EL2_IDBITS_SHIFT 23 243 #define ICH_VTR_EL2_PREBITS_SHIFT 26 244 #define ICH_VTR_EL2_PRIBITS_SHIFT 29 245 246 /* ITS Registers */ 247 248 FIELD(GITS_BASER, SIZE, 0, 8) 249 FIELD(GITS_BASER, PAGESIZE, 8, 2) 250 FIELD(GITS_BASER, SHAREABILITY, 10, 2) 251 FIELD(GITS_BASER, PHYADDR, 12, 36) 252 FIELD(GITS_BASER, PHYADDRL_64K, 16, 32) 253 FIELD(GITS_BASER, PHYADDRH_64K, 12, 4) 254 FIELD(GITS_BASER, ENTRYSIZE, 48, 5) 255 FIELD(GITS_BASER, OUTERCACHE, 53, 3) 256 FIELD(GITS_BASER, TYPE, 56, 3) 257 FIELD(GITS_BASER, INNERCACHE, 59, 3) 258 FIELD(GITS_BASER, INDIRECT, 62, 1) 259 FIELD(GITS_BASER, VALID, 63, 1) 260 261 FIELD(GITS_CTLR, QUIESCENT, 31, 1) 262 263 FIELD(GITS_TYPER, PHYSICAL, 0, 1) 264 FIELD(GITS_TYPER, ITT_ENTRY_SIZE, 4, 4) 265 FIELD(GITS_TYPER, IDBITS, 8, 5) 266 FIELD(GITS_TYPER, DEVBITS, 13, 5) 267 FIELD(GITS_TYPER, SEIS, 18, 1) 268 FIELD(GITS_TYPER, PTA, 19, 1) 269 FIELD(GITS_TYPER, CIDBITS, 32, 4) 270 FIELD(GITS_TYPER, CIL, 36, 1) 271 272 #define GITS_BASER_PAGESIZE_4K 0 273 #define GITS_BASER_PAGESIZE_16K 1 274 #define GITS_BASER_PAGESIZE_64K 2 275 276 #define GITS_BASER_TYPE_DEVICE 1ULL 277 #define GITS_BASER_TYPE_COLLECTION 4ULL 278 279 /** 280 * Default features advertised by this version of ITS 281 */ 282 /* Physical LPIs supported */ 283 #define GITS_TYPE_PHYSICAL (1U << 0) 284 285 /* 286 * 12 bytes Interrupt translation Table Entry size 287 * as per Table 5.3 in GICv3 spec 288 * ITE Lower 8 Bytes 289 * Bits: | 49 ... 26 | 25 ... 2 | 1 | 0 | 290 * Values: | 1023 | IntNum | IntType | Valid | 291 * ITE Higher 4 Bytes 292 * Bits: | 31 ... 16 | 15 ...0 | 293 * Values: | vPEID | ICID | 294 */ 295 #define ITS_ITT_ENTRY_SIZE 0xC 296 297 /* 16 bits EventId */ 298 #define ITS_IDBITS GICD_TYPER_IDBITS 299 300 /* 16 bits DeviceId */ 301 #define ITS_DEVBITS 0xF 302 303 /* 16 bits CollectionId */ 304 #define ITS_CIDBITS 0xF 305 306 /* 307 * 8 bytes Device Table Entry size 308 * Valid = 1 bit,ITTAddr = 44 bits,Size = 5 bits 309 */ 310 #define GITS_DTE_SIZE (0x8ULL) 311 312 /* 313 * 8 bytes Collection Table Entry size 314 * Valid = 1 bit,RDBase = 36 bits(considering max RDBASE) 315 */ 316 #define GITS_CTE_SIZE (0x8ULL) 317 318 /* Special interrupt IDs */ 319 #define INTID_SECURE 1020 320 #define INTID_NONSECURE 1021 321 #define INTID_SPURIOUS 1023 322 323 /* Functions internal to the emulated GICv3 */ 324 325 /** 326 * gicv3_redist_update: 327 * @cs: GICv3CPUState for this redistributor 328 * 329 * Recalculate the highest priority pending interrupt after a 330 * change to redistributor state, and inform the CPU accordingly. 331 */ 332 void gicv3_redist_update(GICv3CPUState *cs); 333 334 /** 335 * gicv3_update: 336 * @s: GICv3State 337 * @start: first interrupt whose state changed 338 * @len: length of the range of interrupts whose state changed 339 * 340 * Recalculate the highest priority pending interrupts after a 341 * change to the distributor state affecting @len interrupts 342 * starting at @start, and inform the CPUs accordingly. 343 */ 344 void gicv3_update(GICv3State *s, int start, int len); 345 346 /** 347 * gicv3_full_update_noirqset: 348 * @s: GICv3State 349 * 350 * Recalculate the cached information about highest priority 351 * pending interrupts, but don't inform the CPUs. This should be 352 * called after an incoming migration has loaded new state. 353 */ 354 void gicv3_full_update_noirqset(GICv3State *s); 355 356 /** 357 * gicv3_full_update: 358 * @s: GICv3State 359 * 360 * Recalculate the highest priority pending interrupts after 361 * a change that could affect the status of all interrupts, 362 * and inform the CPUs accordingly. 363 */ 364 void gicv3_full_update(GICv3State *s); 365 MemTxResult gicv3_dist_read(void *opaque, hwaddr offset, uint64_t *data, 366 unsigned size, MemTxAttrs attrs); 367 MemTxResult gicv3_dist_write(void *opaque, hwaddr addr, uint64_t data, 368 unsigned size, MemTxAttrs attrs); 369 MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data, 370 unsigned size, MemTxAttrs attrs); 371 MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data, 372 unsigned size, MemTxAttrs attrs); 373 void gicv3_dist_set_irq(GICv3State *s, int irq, int level); 374 void gicv3_redist_set_irq(GICv3CPUState *cs, int irq, int level); 375 void gicv3_redist_send_sgi(GICv3CPUState *cs, int grp, int irq, bool ns); 376 void gicv3_init_cpuif(GICv3State *s); 377 378 /** 379 * gicv3_cpuif_update: 380 * @cs: GICv3CPUState for the CPU to update 381 * 382 * Recalculate whether to assert the IRQ or FIQ lines after a change 383 * to the current highest priority pending interrupt, the CPU's 384 * current running priority or the CPU's current exception level or 385 * security state. 386 */ 387 void gicv3_cpuif_update(GICv3CPUState *cs); 388 389 static inline uint32_t gicv3_iidr(void) 390 { 391 /* Return the Implementer Identification Register value 392 * for the emulated GICv3, as reported in GICD_IIDR and GICR_IIDR. 393 * 394 * We claim to be an ARM r0p0 with a zero ProductID. 395 * This is the same as an r0p0 GIC-500. 396 */ 397 return 0x43b; 398 } 399 400 static inline uint32_t gicv3_idreg(int regoffset) 401 { 402 /* Return the value of the CoreSight ID register at the specified 403 * offset from the first ID register (as found in the distributor 404 * and redistributor register banks). 405 * These values indicate an ARM implementation of a GICv3. 406 */ 407 static const uint8_t gicd_ids[] = { 408 0x44, 0x00, 0x00, 0x00, 0x92, 0xB4, 0x3B, 0x00, 0x0D, 0xF0, 0x05, 0xB1 409 }; 410 return gicd_ids[regoffset / 4]; 411 } 412 413 /** 414 * gicv3_irq_group: 415 * 416 * Return the group which this interrupt is configured as (GICV3_G0, 417 * GICV3_G1 or GICV3_G1NS). 418 */ 419 static inline int gicv3_irq_group(GICv3State *s, GICv3CPUState *cs, int irq) 420 { 421 bool grpbit, grpmodbit; 422 423 if (irq < GIC_INTERNAL) { 424 grpbit = extract32(cs->gicr_igroupr0, irq, 1); 425 grpmodbit = extract32(cs->gicr_igrpmodr0, irq, 1); 426 } else { 427 grpbit = gicv3_gicd_group_test(s, irq); 428 grpmodbit = gicv3_gicd_grpmod_test(s, irq); 429 } 430 if (grpbit) { 431 return GICV3_G1NS; 432 } 433 if (s->gicd_ctlr & GICD_CTLR_DS) { 434 return GICV3_G0; 435 } 436 return grpmodbit ? GICV3_G1 : GICV3_G0; 437 } 438 439 /** 440 * gicv3_redist_affid: 441 * 442 * Return the 32-bit affinity ID of the CPU connected to this redistributor 443 */ 444 static inline uint32_t gicv3_redist_affid(GICv3CPUState *cs) 445 { 446 return cs->gicr_typer >> 32; 447 } 448 449 /** 450 * gicv3_cache_target_cpustate: 451 * 452 * Update the cached CPU state corresponding to the target for this interrupt 453 * (which is kept in s->gicd_irouter_target[]). 454 */ 455 static inline void gicv3_cache_target_cpustate(GICv3State *s, int irq) 456 { 457 GICv3CPUState *cs = NULL; 458 int i; 459 uint32_t tgtaff = extract64(s->gicd_irouter[irq], 0, 24) | 460 extract64(s->gicd_irouter[irq], 32, 8) << 24; 461 462 for (i = 0; i < s->num_cpu; i++) { 463 if (s->cpu[i].gicr_typer >> 32 == tgtaff) { 464 cs = &s->cpu[i]; 465 break; 466 } 467 } 468 469 s->gicd_irouter_target[irq] = cs; 470 } 471 472 /** 473 * gicv3_cache_all_target_cpustates: 474 * 475 * Populate the entire cache of CPU state pointers for interrupt targets 476 * (eg after inbound migration or CPU reset) 477 */ 478 static inline void gicv3_cache_all_target_cpustates(GICv3State *s) 479 { 480 int irq; 481 482 for (irq = GIC_INTERNAL; irq < GICV3_MAXIRQ; irq++) { 483 gicv3_cache_target_cpustate(s, irq); 484 } 485 } 486 487 void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s); 488 489 #endif /* QEMU_ARM_GICV3_INTERNAL_H */ 490