1 /* 2 * Samsung exynos4210 GIC implementation. Based on hw/arm_gic.c 3 * 4 * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd. 5 * All rights reserved. 6 * 7 * Evgeny Voevodin <e.voevodin@samsung.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 17 * See the GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "hw/sysbus.h" 24 #include "qemu-common.h" 25 #include "hw/irq.h" 26 #include "hw/arm/exynos4210.h" 27 28 enum ExtGicId { 29 EXT_GIC_ID_MDMA_LCD0 = 66, 30 EXT_GIC_ID_PDMA0, 31 EXT_GIC_ID_PDMA1, 32 EXT_GIC_ID_TIMER0, 33 EXT_GIC_ID_TIMER1, 34 EXT_GIC_ID_TIMER2, 35 EXT_GIC_ID_TIMER3, 36 EXT_GIC_ID_TIMER4, 37 EXT_GIC_ID_MCT_L0, 38 EXT_GIC_ID_WDT, 39 EXT_GIC_ID_RTC_ALARM, 40 EXT_GIC_ID_RTC_TIC, 41 EXT_GIC_ID_GPIO_XB, 42 EXT_GIC_ID_GPIO_XA, 43 EXT_GIC_ID_MCT_L1, 44 EXT_GIC_ID_IEM_APC, 45 EXT_GIC_ID_IEM_IEC, 46 EXT_GIC_ID_NFC, 47 EXT_GIC_ID_UART0, 48 EXT_GIC_ID_UART1, 49 EXT_GIC_ID_UART2, 50 EXT_GIC_ID_UART3, 51 EXT_GIC_ID_UART4, 52 EXT_GIC_ID_MCT_G0, 53 EXT_GIC_ID_I2C0, 54 EXT_GIC_ID_I2C1, 55 EXT_GIC_ID_I2C2, 56 EXT_GIC_ID_I2C3, 57 EXT_GIC_ID_I2C4, 58 EXT_GIC_ID_I2C5, 59 EXT_GIC_ID_I2C6, 60 EXT_GIC_ID_I2C7, 61 EXT_GIC_ID_SPI0, 62 EXT_GIC_ID_SPI1, 63 EXT_GIC_ID_SPI2, 64 EXT_GIC_ID_MCT_G1, 65 EXT_GIC_ID_USB_HOST, 66 EXT_GIC_ID_USB_DEVICE, 67 EXT_GIC_ID_MODEMIF, 68 EXT_GIC_ID_HSMMC0, 69 EXT_GIC_ID_HSMMC1, 70 EXT_GIC_ID_HSMMC2, 71 EXT_GIC_ID_HSMMC3, 72 EXT_GIC_ID_SDMMC, 73 EXT_GIC_ID_MIPI_CSI_4LANE, 74 EXT_GIC_ID_MIPI_DSI_4LANE, 75 EXT_GIC_ID_MIPI_CSI_2LANE, 76 EXT_GIC_ID_MIPI_DSI_2LANE, 77 EXT_GIC_ID_ONENAND_AUDI, 78 EXT_GIC_ID_ROTATOR, 79 EXT_GIC_ID_FIMC0, 80 EXT_GIC_ID_FIMC1, 81 EXT_GIC_ID_FIMC2, 82 EXT_GIC_ID_FIMC3, 83 EXT_GIC_ID_JPEG, 84 EXT_GIC_ID_2D, 85 EXT_GIC_ID_PCIe, 86 EXT_GIC_ID_MIXER, 87 EXT_GIC_ID_HDMI, 88 EXT_GIC_ID_HDMI_I2C, 89 EXT_GIC_ID_MFC, 90 EXT_GIC_ID_TVENC, 91 }; 92 93 enum ExtInt { 94 EXT_GIC_ID_EXTINT0 = 48, 95 EXT_GIC_ID_EXTINT1, 96 EXT_GIC_ID_EXTINT2, 97 EXT_GIC_ID_EXTINT3, 98 EXT_GIC_ID_EXTINT4, 99 EXT_GIC_ID_EXTINT5, 100 EXT_GIC_ID_EXTINT6, 101 EXT_GIC_ID_EXTINT7, 102 EXT_GIC_ID_EXTINT8, 103 EXT_GIC_ID_EXTINT9, 104 EXT_GIC_ID_EXTINT10, 105 EXT_GIC_ID_EXTINT11, 106 EXT_GIC_ID_EXTINT12, 107 EXT_GIC_ID_EXTINT13, 108 EXT_GIC_ID_EXTINT14, 109 EXT_GIC_ID_EXTINT15 110 }; 111 112 /* 113 * External GIC sources which are not from External Interrupt Combiner or 114 * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ, 115 * which is INTG16 in Internal Interrupt Combiner. 116 */ 117 118 static uint32_t 119 combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { 120 /* int combiner groups 16-19 */ 121 { }, { }, { }, { }, 122 /* int combiner group 20 */ 123 { 0, EXT_GIC_ID_MDMA_LCD0 }, 124 /* int combiner group 21 */ 125 { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 }, 126 /* int combiner group 22 */ 127 { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2, 128 EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 }, 129 /* int combiner group 23 */ 130 { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC }, 131 /* int combiner group 24 */ 132 { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA }, 133 /* int combiner group 25 */ 134 { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC }, 135 /* int combiner group 26 */ 136 { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3, 137 EXT_GIC_ID_UART4 }, 138 /* int combiner group 27 */ 139 { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3, 140 EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6, 141 EXT_GIC_ID_I2C7 }, 142 /* int combiner group 28 */ 143 { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST}, 144 /* int combiner group 29 */ 145 { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2, 146 EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC }, 147 /* int combiner group 30 */ 148 { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE }, 149 /* int combiner group 31 */ 150 { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE }, 151 /* int combiner group 32 */ 152 { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 }, 153 /* int combiner group 33 */ 154 { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 }, 155 /* int combiner group 34 */ 156 { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC }, 157 /* int combiner group 35 */ 158 { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, 159 /* int combiner group 36 */ 160 { EXT_GIC_ID_MIXER }, 161 /* int combiner group 37 */ 162 { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6, 163 EXT_GIC_ID_EXTINT7 }, 164 /* groups 38-50 */ 165 { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, 166 /* int combiner group 51 */ 167 { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, 168 /* group 52 */ 169 { }, 170 /* int combiner group 53 */ 171 { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, 172 /* groups 54-63 */ 173 { }, { }, { }, { }, { }, { }, { }, { }, { }, { } 174 }; 175 176 #define EXYNOS4210_GIC_NIRQ 160 177 178 #define EXYNOS4210_EXT_GIC_CPU_REGION_SIZE 0x10000 179 #define EXYNOS4210_EXT_GIC_DIST_REGION_SIZE 0x10000 180 181 #define EXYNOS4210_EXT_GIC_PER_CPU_OFFSET 0x8000 182 #define EXYNOS4210_EXT_GIC_CPU_GET_OFFSET(n) \ 183 ((n) * EXYNOS4210_EXT_GIC_PER_CPU_OFFSET) 184 #define EXYNOS4210_EXT_GIC_DIST_GET_OFFSET(n) \ 185 ((n) * EXYNOS4210_EXT_GIC_PER_CPU_OFFSET) 186 187 #define EXYNOS4210_GIC_CPU_REGION_SIZE 0x100 188 #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000 189 190 static void exynos4210_irq_handler(void *opaque, int irq, int level) 191 { 192 Exynos4210Irq *s = (Exynos4210Irq *)opaque; 193 194 /* Bypass */ 195 qemu_set_irq(s->board_irqs[irq], level); 196 } 197 198 /* 199 * Initialize exynos4210 IRQ subsystem stub. 200 */ 201 qemu_irq *exynos4210_init_irq(Exynos4210Irq *s) 202 { 203 return qemu_allocate_irqs(exynos4210_irq_handler, s, 204 EXYNOS4210_MAX_INT_COMBINER_IN_IRQ); 205 } 206 207 /* 208 * Initialize board IRQs. 209 * These IRQs contain splitted Int/External Combiner and External Gic IRQs. 210 */ 211 void exynos4210_init_board_irqs(Exynos4210Irq *s) 212 { 213 uint32_t grp, bit, irq_id, n; 214 215 for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { 216 s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n], 217 s->ext_combiner_irq[n]); 218 219 irq_id = 0; 220 if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) || 221 n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) { 222 /* MCT_G0 is passed to External GIC */ 223 irq_id = EXT_GIC_ID_MCT_G0; 224 } 225 if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) || 226 n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) { 227 /* MCT_G1 is passed to External and GIC */ 228 irq_id = EXT_GIC_ID_MCT_G1; 229 } 230 if (irq_id) { 231 s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n], 232 s->ext_gic_irq[irq_id-32]); 233 } 234 235 } 236 for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { 237 /* these IDs are passed to Internal Combiner and External GIC */ 238 grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n); 239 bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n); 240 irq_id = combiner_grp_to_gic_id[grp - 241 EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; 242 243 if (irq_id) { 244 s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n], 245 s->ext_gic_irq[irq_id-32]); 246 } 247 } 248 } 249 250 /* 251 * Get IRQ number from exynos4210 IRQ subsystem stub. 252 * To identify IRQ source use internal combiner group and bit number 253 * grp - group number 254 * bit - bit number inside group 255 */ 256 uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit) 257 { 258 return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit); 259 } 260 261 /********* GIC part *********/ 262 263 #define TYPE_EXYNOS4210_GIC "exynos4210.gic" 264 #define EXYNOS4210_GIC(obj) \ 265 OBJECT_CHECK(Exynos4210GicState, (obj), TYPE_EXYNOS4210_GIC) 266 267 typedef struct { 268 SysBusDevice parent_obj; 269 270 MemoryRegion cpu_container; 271 MemoryRegion dist_container; 272 MemoryRegion cpu_alias[EXYNOS4210_NCPUS]; 273 MemoryRegion dist_alias[EXYNOS4210_NCPUS]; 274 uint32_t num_cpu; 275 DeviceState *gic; 276 } Exynos4210GicState; 277 278 static void exynos4210_gic_set_irq(void *opaque, int irq, int level) 279 { 280 Exynos4210GicState *s = (Exynos4210GicState *)opaque; 281 qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); 282 } 283 284 static int exynos4210_gic_init(SysBusDevice *sbd) 285 { 286 DeviceState *dev = DEVICE(sbd); 287 Exynos4210GicState *s = EXYNOS4210_GIC(dev); 288 uint32_t i; 289 const char cpu_prefix[] = "exynos4210-gic-alias_cpu"; 290 const char dist_prefix[] = "exynos4210-gic-alias_dist"; 291 char cpu_alias_name[sizeof(cpu_prefix) + 3]; 292 char dist_alias_name[sizeof(cpu_prefix) + 3]; 293 SysBusDevice *busdev; 294 295 s->gic = qdev_create(NULL, "arm_gic"); 296 qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); 297 qdev_prop_set_uint32(s->gic, "num-irq", EXYNOS4210_GIC_NIRQ); 298 qdev_init_nofail(s->gic); 299 busdev = SYS_BUS_DEVICE(s->gic); 300 301 /* Pass through outbound IRQ lines from the GIC */ 302 sysbus_pass_irq(sbd, busdev); 303 304 /* Pass through inbound GPIO lines to the GIC */ 305 qdev_init_gpio_in(dev, exynos4210_gic_set_irq, 306 EXYNOS4210_GIC_NIRQ - 32); 307 308 memory_region_init(&s->cpu_container, OBJECT(s), "exynos4210-cpu-container", 309 EXYNOS4210_EXT_GIC_CPU_REGION_SIZE); 310 memory_region_init(&s->dist_container, OBJECT(s), "exynos4210-dist-container", 311 EXYNOS4210_EXT_GIC_DIST_REGION_SIZE); 312 313 for (i = 0; i < s->num_cpu; i++) { 314 /* Map CPU interface per SMP Core */ 315 sprintf(cpu_alias_name, "%s%x", cpu_prefix, i); 316 memory_region_init_alias(&s->cpu_alias[i], OBJECT(s), 317 cpu_alias_name, 318 sysbus_mmio_get_region(busdev, 1), 319 0, 320 EXYNOS4210_GIC_CPU_REGION_SIZE); 321 memory_region_add_subregion(&s->cpu_container, 322 EXYNOS4210_EXT_GIC_CPU_GET_OFFSET(i), &s->cpu_alias[i]); 323 324 /* Map Distributor per SMP Core */ 325 sprintf(dist_alias_name, "%s%x", dist_prefix, i); 326 memory_region_init_alias(&s->dist_alias[i], OBJECT(s), 327 dist_alias_name, 328 sysbus_mmio_get_region(busdev, 0), 329 0, 330 EXYNOS4210_GIC_DIST_REGION_SIZE); 331 memory_region_add_subregion(&s->dist_container, 332 EXYNOS4210_EXT_GIC_DIST_GET_OFFSET(i), &s->dist_alias[i]); 333 } 334 335 sysbus_init_mmio(sbd, &s->cpu_container); 336 sysbus_init_mmio(sbd, &s->dist_container); 337 338 return 0; 339 } 340 341 static Property exynos4210_gic_properties[] = { 342 DEFINE_PROP_UINT32("num-cpu", Exynos4210GicState, num_cpu, 1), 343 DEFINE_PROP_END_OF_LIST(), 344 }; 345 346 static void exynos4210_gic_class_init(ObjectClass *klass, void *data) 347 { 348 DeviceClass *dc = DEVICE_CLASS(klass); 349 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 350 351 k->init = exynos4210_gic_init; 352 dc->props = exynos4210_gic_properties; 353 } 354 355 static const TypeInfo exynos4210_gic_info = { 356 .name = TYPE_EXYNOS4210_GIC, 357 .parent = TYPE_SYS_BUS_DEVICE, 358 .instance_size = sizeof(Exynos4210GicState), 359 .class_init = exynos4210_gic_class_init, 360 }; 361 362 static void exynos4210_gic_register_types(void) 363 { 364 type_register_static(&exynos4210_gic_info); 365 } 366 367 type_init(exynos4210_gic_register_types) 368 369 /* IRQ OR Gate struct. 370 * 371 * This device models an OR gate. There are n_in input qdev gpio lines and one 372 * output sysbus IRQ line. The output IRQ level is formed as OR between all 373 * gpio inputs. 374 */ 375 376 #define TYPE_EXYNOS4210_IRQ_GATE "exynos4210.irq_gate" 377 #define EXYNOS4210_IRQ_GATE(obj) \ 378 OBJECT_CHECK(Exynos4210IRQGateState, (obj), TYPE_EXYNOS4210_IRQ_GATE) 379 380 typedef struct Exynos4210IRQGateState { 381 SysBusDevice parent_obj; 382 383 uint32_t n_in; /* inputs amount */ 384 uint32_t *level; /* input levels */ 385 qemu_irq out; /* output IRQ */ 386 } Exynos4210IRQGateState; 387 388 static Property exynos4210_irq_gate_properties[] = { 389 DEFINE_PROP_UINT32("n_in", Exynos4210IRQGateState, n_in, 1), 390 DEFINE_PROP_END_OF_LIST(), 391 }; 392 393 static const VMStateDescription vmstate_exynos4210_irq_gate = { 394 .name = "exynos4210.irq_gate", 395 .version_id = 2, 396 .minimum_version_id = 2, 397 .minimum_version_id_old = 2, 398 .fields = (VMStateField[]) { 399 VMSTATE_VBUFFER_UINT32(level, Exynos4210IRQGateState, 1, NULL, 0, n_in), 400 VMSTATE_END_OF_LIST() 401 } 402 }; 403 404 /* Process a change in IRQ input. */ 405 static void exynos4210_irq_gate_handler(void *opaque, int irq, int level) 406 { 407 Exynos4210IRQGateState *s = (Exynos4210IRQGateState *)opaque; 408 uint32_t i; 409 410 assert(irq < s->n_in); 411 412 s->level[irq] = level; 413 414 for (i = 0; i < s->n_in; i++) { 415 if (s->level[i] >= 1) { 416 qemu_irq_raise(s->out); 417 return; 418 } 419 } 420 421 qemu_irq_lower(s->out); 422 } 423 424 static void exynos4210_irq_gate_reset(DeviceState *d) 425 { 426 Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(d); 427 428 memset(s->level, 0, s->n_in * sizeof(*s->level)); 429 } 430 431 /* 432 * IRQ Gate initialization. 433 */ 434 static int exynos4210_irq_gate_init(SysBusDevice *sbd) 435 { 436 DeviceState *dev = DEVICE(sbd); 437 Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(dev); 438 439 /* Allocate general purpose input signals and connect a handler to each of 440 * them */ 441 qdev_init_gpio_in(dev, exynos4210_irq_gate_handler, s->n_in); 442 443 s->level = g_malloc0(s->n_in * sizeof(*s->level)); 444 445 sysbus_init_irq(sbd, &s->out); 446 447 return 0; 448 } 449 450 static void exynos4210_irq_gate_class_init(ObjectClass *klass, void *data) 451 { 452 DeviceClass *dc = DEVICE_CLASS(klass); 453 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 454 455 k->init = exynos4210_irq_gate_init; 456 dc->reset = exynos4210_irq_gate_reset; 457 dc->vmsd = &vmstate_exynos4210_irq_gate; 458 dc->props = exynos4210_irq_gate_properties; 459 } 460 461 static const TypeInfo exynos4210_irq_gate_info = { 462 .name = TYPE_EXYNOS4210_IRQ_GATE, 463 .parent = TYPE_SYS_BUS_DEVICE, 464 .instance_size = sizeof(Exynos4210IRQGateState), 465 .class_init = exynos4210_irq_gate_class_init, 466 }; 467 468 static void exynos4210_irq_gate_register_types(void) 469 { 470 type_register_static(&exynos4210_irq_gate_info); 471 } 472 473 type_init(exynos4210_irq_gate_register_types) 474