1 /* 2 * Samsung exynos4210 GIC implementation. Based on hw/arm_gic.c 3 * 4 * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd. 5 * All rights reserved. 6 * 7 * Evgeny Voevodin <e.voevodin@samsung.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 17 * See the GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "hw/sysbus.h" 25 #include "migration/vmstate.h" 26 #include "qapi/error.h" 27 #include "qemu/module.h" 28 #include "hw/irq.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/arm/exynos4210.h" 31 #include "qom/object.h" 32 33 #define EXYNOS4210_GIC_NIRQ 160 34 35 #define EXYNOS4210_EXT_GIC_CPU_REGION_SIZE 0x10000 36 #define EXYNOS4210_EXT_GIC_DIST_REGION_SIZE 0x10000 37 38 #define EXYNOS4210_EXT_GIC_PER_CPU_OFFSET 0x8000 39 #define EXYNOS4210_EXT_GIC_CPU_GET_OFFSET(n) \ 40 ((n) * EXYNOS4210_EXT_GIC_PER_CPU_OFFSET) 41 #define EXYNOS4210_EXT_GIC_DIST_GET_OFFSET(n) \ 42 ((n) * EXYNOS4210_EXT_GIC_PER_CPU_OFFSET) 43 44 #define EXYNOS4210_GIC_CPU_REGION_SIZE 0x100 45 #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000 46 47 #define TYPE_EXYNOS4210_GIC "exynos4210.gic" 48 OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC) 49 50 struct Exynos4210GicState { 51 SysBusDevice parent_obj; 52 53 MemoryRegion cpu_container; 54 MemoryRegion dist_container; 55 MemoryRegion cpu_alias[EXYNOS4210_NCPUS]; 56 MemoryRegion dist_alias[EXYNOS4210_NCPUS]; 57 uint32_t num_cpu; 58 DeviceState *gic; 59 }; 60 61 static void exynos4210_gic_set_irq(void *opaque, int irq, int level) 62 { 63 Exynos4210GicState *s = (Exynos4210GicState *)opaque; 64 qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); 65 } 66 67 static void exynos4210_gic_realize(DeviceState *dev, Error **errp) 68 { 69 Object *obj = OBJECT(dev); 70 Exynos4210GicState *s = EXYNOS4210_GIC(obj); 71 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 72 const char cpu_prefix[] = "exynos4210-gic-alias_cpu"; 73 const char dist_prefix[] = "exynos4210-gic-alias_dist"; 74 char cpu_alias_name[sizeof(cpu_prefix) + 3]; 75 char dist_alias_name[sizeof(cpu_prefix) + 3]; 76 SysBusDevice *gicbusdev; 77 uint32_t n = s->num_cpu; 78 uint32_t i; 79 80 s->gic = qdev_new("arm_gic"); 81 qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); 82 qdev_prop_set_uint32(s->gic, "num-irq", EXYNOS4210_GIC_NIRQ); 83 gicbusdev = SYS_BUS_DEVICE(s->gic); 84 sysbus_realize_and_unref(gicbusdev, &error_fatal); 85 86 /* Pass through outbound IRQ lines from the GIC */ 87 sysbus_pass_irq(sbd, gicbusdev); 88 89 /* Pass through inbound GPIO lines to the GIC */ 90 qdev_init_gpio_in(dev, exynos4210_gic_set_irq, 91 EXYNOS4210_GIC_NIRQ - 32); 92 93 memory_region_init(&s->cpu_container, obj, "exynos4210-cpu-container", 94 EXYNOS4210_EXT_GIC_CPU_REGION_SIZE); 95 memory_region_init(&s->dist_container, obj, "exynos4210-dist-container", 96 EXYNOS4210_EXT_GIC_DIST_REGION_SIZE); 97 98 /* 99 * This clues in gcc that our on-stack buffers do, in fact have 100 * enough room for the cpu numbers. gcc 9.2.1 on 32-bit x86 101 * doesn't figure this out, otherwise and gives spurious warnings. 102 */ 103 assert(n <= EXYNOS4210_NCPUS); 104 for (i = 0; i < n; i++) { 105 /* Map CPU interface per SMP Core */ 106 sprintf(cpu_alias_name, "%s%x", cpu_prefix, i); 107 memory_region_init_alias(&s->cpu_alias[i], obj, 108 cpu_alias_name, 109 sysbus_mmio_get_region(gicbusdev, 1), 110 0, 111 EXYNOS4210_GIC_CPU_REGION_SIZE); 112 memory_region_add_subregion(&s->cpu_container, 113 EXYNOS4210_EXT_GIC_CPU_GET_OFFSET(i), &s->cpu_alias[i]); 114 115 /* Map Distributor per SMP Core */ 116 sprintf(dist_alias_name, "%s%x", dist_prefix, i); 117 memory_region_init_alias(&s->dist_alias[i], obj, 118 dist_alias_name, 119 sysbus_mmio_get_region(gicbusdev, 0), 120 0, 121 EXYNOS4210_GIC_DIST_REGION_SIZE); 122 memory_region_add_subregion(&s->dist_container, 123 EXYNOS4210_EXT_GIC_DIST_GET_OFFSET(i), &s->dist_alias[i]); 124 } 125 126 sysbus_init_mmio(sbd, &s->cpu_container); 127 sysbus_init_mmio(sbd, &s->dist_container); 128 } 129 130 static Property exynos4210_gic_properties[] = { 131 DEFINE_PROP_UINT32("num-cpu", Exynos4210GicState, num_cpu, 1), 132 DEFINE_PROP_END_OF_LIST(), 133 }; 134 135 static void exynos4210_gic_class_init(ObjectClass *klass, void *data) 136 { 137 DeviceClass *dc = DEVICE_CLASS(klass); 138 139 device_class_set_props(dc, exynos4210_gic_properties); 140 dc->realize = exynos4210_gic_realize; 141 } 142 143 static const TypeInfo exynos4210_gic_info = { 144 .name = TYPE_EXYNOS4210_GIC, 145 .parent = TYPE_SYS_BUS_DEVICE, 146 .instance_size = sizeof(Exynos4210GicState), 147 .class_init = exynos4210_gic_class_init, 148 }; 149 150 static void exynos4210_gic_register_types(void) 151 { 152 type_register_static(&exynos4210_gic_info); 153 } 154 155 type_init(exynos4210_gic_register_types) 156