1 /* 2 * Samsung exynos4210 GIC implementation. Based on hw/arm_gic.c 3 * 4 * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd. 5 * All rights reserved. 6 * 7 * Evgeny Voevodin <e.voevodin@samsung.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 17 * See the GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "hw/sysbus.h" 25 #include "migration/vmstate.h" 26 #include "qapi/error.h" 27 #include "qemu/module.h" 28 #include "hw/irq.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/intc/exynos4210_gic.h" 31 #include "hw/arm/exynos4210.h" 32 #include "qom/object.h" 33 34 #define EXYNOS4210_GIC_NIRQ 160 35 36 #define EXYNOS4210_EXT_GIC_CPU_REGION_SIZE 0x10000 37 #define EXYNOS4210_EXT_GIC_DIST_REGION_SIZE 0x10000 38 39 #define EXYNOS4210_EXT_GIC_PER_CPU_OFFSET 0x8000 40 #define EXYNOS4210_EXT_GIC_CPU_GET_OFFSET(n) \ 41 ((n) * EXYNOS4210_EXT_GIC_PER_CPU_OFFSET) 42 #define EXYNOS4210_EXT_GIC_DIST_GET_OFFSET(n) \ 43 ((n) * EXYNOS4210_EXT_GIC_PER_CPU_OFFSET) 44 45 #define EXYNOS4210_GIC_CPU_REGION_SIZE 0x100 46 #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000 47 48 static void exynos4210_gic_set_irq(void *opaque, int irq, int level) 49 { 50 Exynos4210GicState *s = (Exynos4210GicState *)opaque; 51 qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); 52 } 53 54 static void exynos4210_gic_realize(DeviceState *dev, Error **errp) 55 { 56 Object *obj = OBJECT(dev); 57 Exynos4210GicState *s = EXYNOS4210_GIC(obj); 58 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 59 const char cpu_prefix[] = "exynos4210-gic-alias_cpu"; 60 const char dist_prefix[] = "exynos4210-gic-alias_dist"; 61 char cpu_alias_name[sizeof(cpu_prefix) + 3]; 62 char dist_alias_name[sizeof(cpu_prefix) + 3]; 63 SysBusDevice *gicbusdev; 64 uint32_t n = s->num_cpu; 65 uint32_t i; 66 67 s->gic = qdev_new("arm_gic"); 68 qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); 69 qdev_prop_set_uint32(s->gic, "num-irq", EXYNOS4210_GIC_NIRQ); 70 gicbusdev = SYS_BUS_DEVICE(s->gic); 71 sysbus_realize_and_unref(gicbusdev, &error_fatal); 72 73 /* Pass through outbound IRQ lines from the GIC */ 74 sysbus_pass_irq(sbd, gicbusdev); 75 76 /* Pass through inbound GPIO lines to the GIC */ 77 qdev_init_gpio_in(dev, exynos4210_gic_set_irq, 78 EXYNOS4210_GIC_NIRQ - 32); 79 80 memory_region_init(&s->cpu_container, obj, "exynos4210-cpu-container", 81 EXYNOS4210_EXT_GIC_CPU_REGION_SIZE); 82 memory_region_init(&s->dist_container, obj, "exynos4210-dist-container", 83 EXYNOS4210_EXT_GIC_DIST_REGION_SIZE); 84 85 /* 86 * This clues in gcc that our on-stack buffers do, in fact have 87 * enough room for the cpu numbers. gcc 9.2.1 on 32-bit x86 88 * doesn't figure this out, otherwise and gives spurious warnings. 89 */ 90 assert(n <= EXYNOS4210_GIC_NCPUS); 91 for (i = 0; i < n; i++) { 92 /* Map CPU interface per SMP Core */ 93 sprintf(cpu_alias_name, "%s%x", cpu_prefix, i); 94 memory_region_init_alias(&s->cpu_alias[i], obj, 95 cpu_alias_name, 96 sysbus_mmio_get_region(gicbusdev, 1), 97 0, 98 EXYNOS4210_GIC_CPU_REGION_SIZE); 99 memory_region_add_subregion(&s->cpu_container, 100 EXYNOS4210_EXT_GIC_CPU_GET_OFFSET(i), &s->cpu_alias[i]); 101 102 /* Map Distributor per SMP Core */ 103 sprintf(dist_alias_name, "%s%x", dist_prefix, i); 104 memory_region_init_alias(&s->dist_alias[i], obj, 105 dist_alias_name, 106 sysbus_mmio_get_region(gicbusdev, 0), 107 0, 108 EXYNOS4210_GIC_DIST_REGION_SIZE); 109 memory_region_add_subregion(&s->dist_container, 110 EXYNOS4210_EXT_GIC_DIST_GET_OFFSET(i), &s->dist_alias[i]); 111 } 112 113 sysbus_init_mmio(sbd, &s->cpu_container); 114 sysbus_init_mmio(sbd, &s->dist_container); 115 } 116 117 static Property exynos4210_gic_properties[] = { 118 DEFINE_PROP_UINT32("num-cpu", Exynos4210GicState, num_cpu, 1), 119 DEFINE_PROP_END_OF_LIST(), 120 }; 121 122 static void exynos4210_gic_class_init(ObjectClass *klass, void *data) 123 { 124 DeviceClass *dc = DEVICE_CLASS(klass); 125 126 device_class_set_props(dc, exynos4210_gic_properties); 127 dc->realize = exynos4210_gic_realize; 128 } 129 130 static const TypeInfo exynos4210_gic_info = { 131 .name = TYPE_EXYNOS4210_GIC, 132 .parent = TYPE_SYS_BUS_DEVICE, 133 .instance_size = sizeof(Exynos4210GicState), 134 .class_init = exynos4210_gic_class_init, 135 }; 136 137 static void exynos4210_gic_register_types(void) 138 { 139 type_register_static(&exynos4210_gic_info); 140 } 141 142 type_init(exynos4210_gic_register_types) 143