1 /* 2 * Samsung exynos4210 GIC implementation. Based on hw/arm_gic.c 3 * 4 * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd. 5 * All rights reserved. 6 * 7 * Evgeny Voevodin <e.voevodin@samsung.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 17 * See the GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "hw/sysbus.h" 25 #include "migration/vmstate.h" 26 #include "qapi/error.h" 27 #include "qemu/module.h" 28 #include "hw/irq.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/arm/exynos4210.h" 31 #include "qom/object.h" 32 33 enum ExtGicId { 34 EXT_GIC_ID_MDMA_LCD0 = 66, 35 EXT_GIC_ID_PDMA0, 36 EXT_GIC_ID_PDMA1, 37 EXT_GIC_ID_TIMER0, 38 EXT_GIC_ID_TIMER1, 39 EXT_GIC_ID_TIMER2, 40 EXT_GIC_ID_TIMER3, 41 EXT_GIC_ID_TIMER4, 42 EXT_GIC_ID_MCT_L0, 43 EXT_GIC_ID_WDT, 44 EXT_GIC_ID_RTC_ALARM, 45 EXT_GIC_ID_RTC_TIC, 46 EXT_GIC_ID_GPIO_XB, 47 EXT_GIC_ID_GPIO_XA, 48 EXT_GIC_ID_MCT_L1, 49 EXT_GIC_ID_IEM_APC, 50 EXT_GIC_ID_IEM_IEC, 51 EXT_GIC_ID_NFC, 52 EXT_GIC_ID_UART0, 53 EXT_GIC_ID_UART1, 54 EXT_GIC_ID_UART2, 55 EXT_GIC_ID_UART3, 56 EXT_GIC_ID_UART4, 57 EXT_GIC_ID_MCT_G0, 58 EXT_GIC_ID_I2C0, 59 EXT_GIC_ID_I2C1, 60 EXT_GIC_ID_I2C2, 61 EXT_GIC_ID_I2C3, 62 EXT_GIC_ID_I2C4, 63 EXT_GIC_ID_I2C5, 64 EXT_GIC_ID_I2C6, 65 EXT_GIC_ID_I2C7, 66 EXT_GIC_ID_SPI0, 67 EXT_GIC_ID_SPI1, 68 EXT_GIC_ID_SPI2, 69 EXT_GIC_ID_MCT_G1, 70 EXT_GIC_ID_USB_HOST, 71 EXT_GIC_ID_USB_DEVICE, 72 EXT_GIC_ID_MODEMIF, 73 EXT_GIC_ID_HSMMC0, 74 EXT_GIC_ID_HSMMC1, 75 EXT_GIC_ID_HSMMC2, 76 EXT_GIC_ID_HSMMC3, 77 EXT_GIC_ID_SDMMC, 78 EXT_GIC_ID_MIPI_CSI_4LANE, 79 EXT_GIC_ID_MIPI_DSI_4LANE, 80 EXT_GIC_ID_MIPI_CSI_2LANE, 81 EXT_GIC_ID_MIPI_DSI_2LANE, 82 EXT_GIC_ID_ONENAND_AUDI, 83 EXT_GIC_ID_ROTATOR, 84 EXT_GIC_ID_FIMC0, 85 EXT_GIC_ID_FIMC1, 86 EXT_GIC_ID_FIMC2, 87 EXT_GIC_ID_FIMC3, 88 EXT_GIC_ID_JPEG, 89 EXT_GIC_ID_2D, 90 EXT_GIC_ID_PCIe, 91 EXT_GIC_ID_MIXER, 92 EXT_GIC_ID_HDMI, 93 EXT_GIC_ID_HDMI_I2C, 94 EXT_GIC_ID_MFC, 95 EXT_GIC_ID_TVENC, 96 }; 97 98 enum ExtInt { 99 EXT_GIC_ID_EXTINT0 = 48, 100 EXT_GIC_ID_EXTINT1, 101 EXT_GIC_ID_EXTINT2, 102 EXT_GIC_ID_EXTINT3, 103 EXT_GIC_ID_EXTINT4, 104 EXT_GIC_ID_EXTINT5, 105 EXT_GIC_ID_EXTINT6, 106 EXT_GIC_ID_EXTINT7, 107 EXT_GIC_ID_EXTINT8, 108 EXT_GIC_ID_EXTINT9, 109 EXT_GIC_ID_EXTINT10, 110 EXT_GIC_ID_EXTINT11, 111 EXT_GIC_ID_EXTINT12, 112 EXT_GIC_ID_EXTINT13, 113 EXT_GIC_ID_EXTINT14, 114 EXT_GIC_ID_EXTINT15 115 }; 116 117 /* 118 * External GIC sources which are not from External Interrupt Combiner or 119 * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ, 120 * which is INTG16 in Internal Interrupt Combiner. 121 */ 122 123 static const uint32_t 124 combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { 125 /* int combiner groups 16-19 */ 126 { }, { }, { }, { }, 127 /* int combiner group 20 */ 128 { 0, EXT_GIC_ID_MDMA_LCD0 }, 129 /* int combiner group 21 */ 130 { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 }, 131 /* int combiner group 22 */ 132 { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2, 133 EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 }, 134 /* int combiner group 23 */ 135 { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC }, 136 /* int combiner group 24 */ 137 { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA }, 138 /* int combiner group 25 */ 139 { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC }, 140 /* int combiner group 26 */ 141 { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3, 142 EXT_GIC_ID_UART4 }, 143 /* int combiner group 27 */ 144 { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3, 145 EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6, 146 EXT_GIC_ID_I2C7 }, 147 /* int combiner group 28 */ 148 { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST}, 149 /* int combiner group 29 */ 150 { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2, 151 EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC }, 152 /* int combiner group 30 */ 153 { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE }, 154 /* int combiner group 31 */ 155 { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE }, 156 /* int combiner group 32 */ 157 { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 }, 158 /* int combiner group 33 */ 159 { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 }, 160 /* int combiner group 34 */ 161 { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC }, 162 /* int combiner group 35 */ 163 { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, 164 /* int combiner group 36 */ 165 { EXT_GIC_ID_MIXER }, 166 /* int combiner group 37 */ 167 { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6, 168 EXT_GIC_ID_EXTINT7 }, 169 /* groups 38-50 */ 170 { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, 171 /* int combiner group 51 */ 172 { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, 173 /* group 52 */ 174 { }, 175 /* int combiner group 53 */ 176 { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, 177 /* groups 54-63 */ 178 { }, { }, { }, { }, { }, { }, { }, { }, { }, { } 179 }; 180 181 #define EXYNOS4210_GIC_NIRQ 160 182 183 #define EXYNOS4210_EXT_GIC_CPU_REGION_SIZE 0x10000 184 #define EXYNOS4210_EXT_GIC_DIST_REGION_SIZE 0x10000 185 186 #define EXYNOS4210_EXT_GIC_PER_CPU_OFFSET 0x8000 187 #define EXYNOS4210_EXT_GIC_CPU_GET_OFFSET(n) \ 188 ((n) * EXYNOS4210_EXT_GIC_PER_CPU_OFFSET) 189 #define EXYNOS4210_EXT_GIC_DIST_GET_OFFSET(n) \ 190 ((n) * EXYNOS4210_EXT_GIC_PER_CPU_OFFSET) 191 192 #define EXYNOS4210_GIC_CPU_REGION_SIZE 0x100 193 #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000 194 195 /* 196 * Initialize board IRQs. 197 * These IRQs contain splitted Int/External Combiner and External Gic IRQs. 198 */ 199 void exynos4210_init_board_irqs(Exynos4210State *s) 200 { 201 uint32_t grp, bit, irq_id, n; 202 Exynos4210Irq *is = &s->irqs; 203 204 for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { 205 irq_id = 0; 206 if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) || 207 n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) { 208 /* MCT_G0 is passed to External GIC */ 209 irq_id = EXT_GIC_ID_MCT_G0; 210 } 211 if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) || 212 n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) { 213 /* MCT_G1 is passed to External and GIC */ 214 irq_id = EXT_GIC_ID_MCT_G1; 215 } 216 if (irq_id) { 217 s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], 218 is->ext_gic_irq[irq_id - 32]); 219 } else { 220 s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], 221 is->ext_combiner_irq[n]); 222 } 223 } 224 for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { 225 /* these IDs are passed to Internal Combiner and External GIC */ 226 grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n); 227 bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n); 228 irq_id = combiner_grp_to_gic_id[grp - 229 EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; 230 231 if (irq_id) { 232 s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], 233 is->ext_gic_irq[irq_id - 32]); 234 } 235 } 236 } 237 238 /* 239 * Get IRQ number from exynos4210 IRQ subsystem stub. 240 * To identify IRQ source use internal combiner group and bit number 241 * grp - group number 242 * bit - bit number inside group 243 */ 244 uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit) 245 { 246 return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit); 247 } 248 249 /********* GIC part *********/ 250 251 #define TYPE_EXYNOS4210_GIC "exynos4210.gic" 252 OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC) 253 254 struct Exynos4210GicState { 255 SysBusDevice parent_obj; 256 257 MemoryRegion cpu_container; 258 MemoryRegion dist_container; 259 MemoryRegion cpu_alias[EXYNOS4210_NCPUS]; 260 MemoryRegion dist_alias[EXYNOS4210_NCPUS]; 261 uint32_t num_cpu; 262 DeviceState *gic; 263 }; 264 265 static void exynos4210_gic_set_irq(void *opaque, int irq, int level) 266 { 267 Exynos4210GicState *s = (Exynos4210GicState *)opaque; 268 qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); 269 } 270 271 static void exynos4210_gic_realize(DeviceState *dev, Error **errp) 272 { 273 Object *obj = OBJECT(dev); 274 Exynos4210GicState *s = EXYNOS4210_GIC(obj); 275 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 276 const char cpu_prefix[] = "exynos4210-gic-alias_cpu"; 277 const char dist_prefix[] = "exynos4210-gic-alias_dist"; 278 char cpu_alias_name[sizeof(cpu_prefix) + 3]; 279 char dist_alias_name[sizeof(cpu_prefix) + 3]; 280 SysBusDevice *gicbusdev; 281 uint32_t n = s->num_cpu; 282 uint32_t i; 283 284 s->gic = qdev_new("arm_gic"); 285 qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); 286 qdev_prop_set_uint32(s->gic, "num-irq", EXYNOS4210_GIC_NIRQ); 287 gicbusdev = SYS_BUS_DEVICE(s->gic); 288 sysbus_realize_and_unref(gicbusdev, &error_fatal); 289 290 /* Pass through outbound IRQ lines from the GIC */ 291 sysbus_pass_irq(sbd, gicbusdev); 292 293 /* Pass through inbound GPIO lines to the GIC */ 294 qdev_init_gpio_in(dev, exynos4210_gic_set_irq, 295 EXYNOS4210_GIC_NIRQ - 32); 296 297 memory_region_init(&s->cpu_container, obj, "exynos4210-cpu-container", 298 EXYNOS4210_EXT_GIC_CPU_REGION_SIZE); 299 memory_region_init(&s->dist_container, obj, "exynos4210-dist-container", 300 EXYNOS4210_EXT_GIC_DIST_REGION_SIZE); 301 302 /* 303 * This clues in gcc that our on-stack buffers do, in fact have 304 * enough room for the cpu numbers. gcc 9.2.1 on 32-bit x86 305 * doesn't figure this out, otherwise and gives spurious warnings. 306 */ 307 assert(n <= EXYNOS4210_NCPUS); 308 for (i = 0; i < n; i++) { 309 /* Map CPU interface per SMP Core */ 310 sprintf(cpu_alias_name, "%s%x", cpu_prefix, i); 311 memory_region_init_alias(&s->cpu_alias[i], obj, 312 cpu_alias_name, 313 sysbus_mmio_get_region(gicbusdev, 1), 314 0, 315 EXYNOS4210_GIC_CPU_REGION_SIZE); 316 memory_region_add_subregion(&s->cpu_container, 317 EXYNOS4210_EXT_GIC_CPU_GET_OFFSET(i), &s->cpu_alias[i]); 318 319 /* Map Distributor per SMP Core */ 320 sprintf(dist_alias_name, "%s%x", dist_prefix, i); 321 memory_region_init_alias(&s->dist_alias[i], obj, 322 dist_alias_name, 323 sysbus_mmio_get_region(gicbusdev, 0), 324 0, 325 EXYNOS4210_GIC_DIST_REGION_SIZE); 326 memory_region_add_subregion(&s->dist_container, 327 EXYNOS4210_EXT_GIC_DIST_GET_OFFSET(i), &s->dist_alias[i]); 328 } 329 330 sysbus_init_mmio(sbd, &s->cpu_container); 331 sysbus_init_mmio(sbd, &s->dist_container); 332 } 333 334 static Property exynos4210_gic_properties[] = { 335 DEFINE_PROP_UINT32("num-cpu", Exynos4210GicState, num_cpu, 1), 336 DEFINE_PROP_END_OF_LIST(), 337 }; 338 339 static void exynos4210_gic_class_init(ObjectClass *klass, void *data) 340 { 341 DeviceClass *dc = DEVICE_CLASS(klass); 342 343 device_class_set_props(dc, exynos4210_gic_properties); 344 dc->realize = exynos4210_gic_realize; 345 } 346 347 static const TypeInfo exynos4210_gic_info = { 348 .name = TYPE_EXYNOS4210_GIC, 349 .parent = TYPE_SYS_BUS_DEVICE, 350 .instance_size = sizeof(Exynos4210GicState), 351 .class_init = exynos4210_gic_class_init, 352 }; 353 354 static void exynos4210_gic_register_types(void) 355 { 356 type_register_static(&exynos4210_gic_info); 357 } 358 359 type_init(exynos4210_gic_register_types) 360