1 /* 2 * Samsung exynos4210 GIC implementation. Based on hw/arm_gic.c 3 * 4 * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd. 5 * All rights reserved. 6 * 7 * Evgeny Voevodin <e.voevodin@samsung.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 17 * See the GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "hw/sysbus.h" 25 #include "migration/vmstate.h" 26 #include "qemu/module.h" 27 #include "hw/irq.h" 28 #include "hw/arm/exynos4210.h" 29 30 enum ExtGicId { 31 EXT_GIC_ID_MDMA_LCD0 = 66, 32 EXT_GIC_ID_PDMA0, 33 EXT_GIC_ID_PDMA1, 34 EXT_GIC_ID_TIMER0, 35 EXT_GIC_ID_TIMER1, 36 EXT_GIC_ID_TIMER2, 37 EXT_GIC_ID_TIMER3, 38 EXT_GIC_ID_TIMER4, 39 EXT_GIC_ID_MCT_L0, 40 EXT_GIC_ID_WDT, 41 EXT_GIC_ID_RTC_ALARM, 42 EXT_GIC_ID_RTC_TIC, 43 EXT_GIC_ID_GPIO_XB, 44 EXT_GIC_ID_GPIO_XA, 45 EXT_GIC_ID_MCT_L1, 46 EXT_GIC_ID_IEM_APC, 47 EXT_GIC_ID_IEM_IEC, 48 EXT_GIC_ID_NFC, 49 EXT_GIC_ID_UART0, 50 EXT_GIC_ID_UART1, 51 EXT_GIC_ID_UART2, 52 EXT_GIC_ID_UART3, 53 EXT_GIC_ID_UART4, 54 EXT_GIC_ID_MCT_G0, 55 EXT_GIC_ID_I2C0, 56 EXT_GIC_ID_I2C1, 57 EXT_GIC_ID_I2C2, 58 EXT_GIC_ID_I2C3, 59 EXT_GIC_ID_I2C4, 60 EXT_GIC_ID_I2C5, 61 EXT_GIC_ID_I2C6, 62 EXT_GIC_ID_I2C7, 63 EXT_GIC_ID_SPI0, 64 EXT_GIC_ID_SPI1, 65 EXT_GIC_ID_SPI2, 66 EXT_GIC_ID_MCT_G1, 67 EXT_GIC_ID_USB_HOST, 68 EXT_GIC_ID_USB_DEVICE, 69 EXT_GIC_ID_MODEMIF, 70 EXT_GIC_ID_HSMMC0, 71 EXT_GIC_ID_HSMMC1, 72 EXT_GIC_ID_HSMMC2, 73 EXT_GIC_ID_HSMMC3, 74 EXT_GIC_ID_SDMMC, 75 EXT_GIC_ID_MIPI_CSI_4LANE, 76 EXT_GIC_ID_MIPI_DSI_4LANE, 77 EXT_GIC_ID_MIPI_CSI_2LANE, 78 EXT_GIC_ID_MIPI_DSI_2LANE, 79 EXT_GIC_ID_ONENAND_AUDI, 80 EXT_GIC_ID_ROTATOR, 81 EXT_GIC_ID_FIMC0, 82 EXT_GIC_ID_FIMC1, 83 EXT_GIC_ID_FIMC2, 84 EXT_GIC_ID_FIMC3, 85 EXT_GIC_ID_JPEG, 86 EXT_GIC_ID_2D, 87 EXT_GIC_ID_PCIe, 88 EXT_GIC_ID_MIXER, 89 EXT_GIC_ID_HDMI, 90 EXT_GIC_ID_HDMI_I2C, 91 EXT_GIC_ID_MFC, 92 EXT_GIC_ID_TVENC, 93 }; 94 95 enum ExtInt { 96 EXT_GIC_ID_EXTINT0 = 48, 97 EXT_GIC_ID_EXTINT1, 98 EXT_GIC_ID_EXTINT2, 99 EXT_GIC_ID_EXTINT3, 100 EXT_GIC_ID_EXTINT4, 101 EXT_GIC_ID_EXTINT5, 102 EXT_GIC_ID_EXTINT6, 103 EXT_GIC_ID_EXTINT7, 104 EXT_GIC_ID_EXTINT8, 105 EXT_GIC_ID_EXTINT9, 106 EXT_GIC_ID_EXTINT10, 107 EXT_GIC_ID_EXTINT11, 108 EXT_GIC_ID_EXTINT12, 109 EXT_GIC_ID_EXTINT13, 110 EXT_GIC_ID_EXTINT14, 111 EXT_GIC_ID_EXTINT15 112 }; 113 114 /* 115 * External GIC sources which are not from External Interrupt Combiner or 116 * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ, 117 * which is INTG16 in Internal Interrupt Combiner. 118 */ 119 120 static const uint32_t 121 combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { 122 /* int combiner groups 16-19 */ 123 { }, { }, { }, { }, 124 /* int combiner group 20 */ 125 { 0, EXT_GIC_ID_MDMA_LCD0 }, 126 /* int combiner group 21 */ 127 { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 }, 128 /* int combiner group 22 */ 129 { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2, 130 EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 }, 131 /* int combiner group 23 */ 132 { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC }, 133 /* int combiner group 24 */ 134 { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA }, 135 /* int combiner group 25 */ 136 { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC }, 137 /* int combiner group 26 */ 138 { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3, 139 EXT_GIC_ID_UART4 }, 140 /* int combiner group 27 */ 141 { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3, 142 EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6, 143 EXT_GIC_ID_I2C7 }, 144 /* int combiner group 28 */ 145 { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST}, 146 /* int combiner group 29 */ 147 { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2, 148 EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC }, 149 /* int combiner group 30 */ 150 { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE }, 151 /* int combiner group 31 */ 152 { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE }, 153 /* int combiner group 32 */ 154 { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 }, 155 /* int combiner group 33 */ 156 { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 }, 157 /* int combiner group 34 */ 158 { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC }, 159 /* int combiner group 35 */ 160 { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, 161 /* int combiner group 36 */ 162 { EXT_GIC_ID_MIXER }, 163 /* int combiner group 37 */ 164 { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6, 165 EXT_GIC_ID_EXTINT7 }, 166 /* groups 38-50 */ 167 { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, 168 /* int combiner group 51 */ 169 { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, 170 /* group 52 */ 171 { }, 172 /* int combiner group 53 */ 173 { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, 174 /* groups 54-63 */ 175 { }, { }, { }, { }, { }, { }, { }, { }, { }, { } 176 }; 177 178 #define EXYNOS4210_GIC_NIRQ 160 179 180 #define EXYNOS4210_EXT_GIC_CPU_REGION_SIZE 0x10000 181 #define EXYNOS4210_EXT_GIC_DIST_REGION_SIZE 0x10000 182 183 #define EXYNOS4210_EXT_GIC_PER_CPU_OFFSET 0x8000 184 #define EXYNOS4210_EXT_GIC_CPU_GET_OFFSET(n) \ 185 ((n) * EXYNOS4210_EXT_GIC_PER_CPU_OFFSET) 186 #define EXYNOS4210_EXT_GIC_DIST_GET_OFFSET(n) \ 187 ((n) * EXYNOS4210_EXT_GIC_PER_CPU_OFFSET) 188 189 #define EXYNOS4210_GIC_CPU_REGION_SIZE 0x100 190 #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000 191 192 static void exynos4210_irq_handler(void *opaque, int irq, int level) 193 { 194 Exynos4210Irq *s = (Exynos4210Irq *)opaque; 195 196 /* Bypass */ 197 qemu_set_irq(s->board_irqs[irq], level); 198 } 199 200 /* 201 * Initialize exynos4210 IRQ subsystem stub. 202 */ 203 qemu_irq *exynos4210_init_irq(Exynos4210Irq *s) 204 { 205 return qemu_allocate_irqs(exynos4210_irq_handler, s, 206 EXYNOS4210_MAX_INT_COMBINER_IN_IRQ); 207 } 208 209 /* 210 * Initialize board IRQs. 211 * These IRQs contain splitted Int/External Combiner and External Gic IRQs. 212 */ 213 void exynos4210_init_board_irqs(Exynos4210Irq *s) 214 { 215 uint32_t grp, bit, irq_id, n; 216 217 for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { 218 irq_id = 0; 219 if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) || 220 n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) { 221 /* MCT_G0 is passed to External GIC */ 222 irq_id = EXT_GIC_ID_MCT_G0; 223 } 224 if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) || 225 n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) { 226 /* MCT_G1 is passed to External and GIC */ 227 irq_id = EXT_GIC_ID_MCT_G1; 228 } 229 if (irq_id) { 230 s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n], 231 s->ext_gic_irq[irq_id-32]); 232 } else { 233 s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n], 234 s->ext_combiner_irq[n]); 235 } 236 } 237 for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { 238 /* these IDs are passed to Internal Combiner and External GIC */ 239 grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n); 240 bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n); 241 irq_id = combiner_grp_to_gic_id[grp - 242 EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; 243 244 if (irq_id) { 245 s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n], 246 s->ext_gic_irq[irq_id-32]); 247 } 248 } 249 } 250 251 /* 252 * Get IRQ number from exynos4210 IRQ subsystem stub. 253 * To identify IRQ source use internal combiner group and bit number 254 * grp - group number 255 * bit - bit number inside group 256 */ 257 uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit) 258 { 259 return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit); 260 } 261 262 /********* GIC part *********/ 263 264 #define TYPE_EXYNOS4210_GIC "exynos4210.gic" 265 #define EXYNOS4210_GIC(obj) \ 266 OBJECT_CHECK(Exynos4210GicState, (obj), TYPE_EXYNOS4210_GIC) 267 268 typedef struct { 269 SysBusDevice parent_obj; 270 271 MemoryRegion cpu_container; 272 MemoryRegion dist_container; 273 MemoryRegion cpu_alias[EXYNOS4210_NCPUS]; 274 MemoryRegion dist_alias[EXYNOS4210_NCPUS]; 275 uint32_t num_cpu; 276 DeviceState *gic; 277 } Exynos4210GicState; 278 279 static void exynos4210_gic_set_irq(void *opaque, int irq, int level) 280 { 281 Exynos4210GicState *s = (Exynos4210GicState *)opaque; 282 qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); 283 } 284 285 static void exynos4210_gic_realize(DeviceState *dev, Error **errp) 286 { 287 Object *obj = OBJECT(dev); 288 Exynos4210GicState *s = EXYNOS4210_GIC(obj); 289 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 290 const char cpu_prefix[] = "exynos4210-gic-alias_cpu"; 291 const char dist_prefix[] = "exynos4210-gic-alias_dist"; 292 char cpu_alias_name[sizeof(cpu_prefix) + 3]; 293 char dist_alias_name[sizeof(cpu_prefix) + 3]; 294 SysBusDevice *gicbusdev; 295 uint32_t i; 296 297 s->gic = qdev_create(NULL, "arm_gic"); 298 qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); 299 qdev_prop_set_uint32(s->gic, "num-irq", EXYNOS4210_GIC_NIRQ); 300 qdev_init_nofail(s->gic); 301 gicbusdev = SYS_BUS_DEVICE(s->gic); 302 303 /* Pass through outbound IRQ lines from the GIC */ 304 sysbus_pass_irq(sbd, gicbusdev); 305 306 /* Pass through inbound GPIO lines to the GIC */ 307 qdev_init_gpio_in(dev, exynos4210_gic_set_irq, 308 EXYNOS4210_GIC_NIRQ - 32); 309 310 memory_region_init(&s->cpu_container, obj, "exynos4210-cpu-container", 311 EXYNOS4210_EXT_GIC_CPU_REGION_SIZE); 312 memory_region_init(&s->dist_container, obj, "exynos4210-dist-container", 313 EXYNOS4210_EXT_GIC_DIST_REGION_SIZE); 314 315 for (i = 0; i < s->num_cpu; i++) { 316 /* Map CPU interface per SMP Core */ 317 sprintf(cpu_alias_name, "%s%x", cpu_prefix, i); 318 memory_region_init_alias(&s->cpu_alias[i], obj, 319 cpu_alias_name, 320 sysbus_mmio_get_region(gicbusdev, 1), 321 0, 322 EXYNOS4210_GIC_CPU_REGION_SIZE); 323 memory_region_add_subregion(&s->cpu_container, 324 EXYNOS4210_EXT_GIC_CPU_GET_OFFSET(i), &s->cpu_alias[i]); 325 326 /* Map Distributor per SMP Core */ 327 sprintf(dist_alias_name, "%s%x", dist_prefix, i); 328 memory_region_init_alias(&s->dist_alias[i], obj, 329 dist_alias_name, 330 sysbus_mmio_get_region(gicbusdev, 0), 331 0, 332 EXYNOS4210_GIC_DIST_REGION_SIZE); 333 memory_region_add_subregion(&s->dist_container, 334 EXYNOS4210_EXT_GIC_DIST_GET_OFFSET(i), &s->dist_alias[i]); 335 } 336 337 sysbus_init_mmio(sbd, &s->cpu_container); 338 sysbus_init_mmio(sbd, &s->dist_container); 339 } 340 341 static Property exynos4210_gic_properties[] = { 342 DEFINE_PROP_UINT32("num-cpu", Exynos4210GicState, num_cpu, 1), 343 DEFINE_PROP_END_OF_LIST(), 344 }; 345 346 static void exynos4210_gic_class_init(ObjectClass *klass, void *data) 347 { 348 DeviceClass *dc = DEVICE_CLASS(klass); 349 350 dc->props = exynos4210_gic_properties; 351 dc->realize = exynos4210_gic_realize; 352 } 353 354 static const TypeInfo exynos4210_gic_info = { 355 .name = TYPE_EXYNOS4210_GIC, 356 .parent = TYPE_SYS_BUS_DEVICE, 357 .instance_size = sizeof(Exynos4210GicState), 358 .class_init = exynos4210_gic_class_init, 359 }; 360 361 static void exynos4210_gic_register_types(void) 362 { 363 type_register_static(&exynos4210_gic_info); 364 } 365 366 type_init(exynos4210_gic_register_types) 367 368 /* IRQ OR Gate struct. 369 * 370 * This device models an OR gate. There are n_in input qdev gpio lines and one 371 * output sysbus IRQ line. The output IRQ level is formed as OR between all 372 * gpio inputs. 373 */ 374 375 #define TYPE_EXYNOS4210_IRQ_GATE "exynos4210.irq_gate" 376 #define EXYNOS4210_IRQ_GATE(obj) \ 377 OBJECT_CHECK(Exynos4210IRQGateState, (obj), TYPE_EXYNOS4210_IRQ_GATE) 378 379 typedef struct Exynos4210IRQGateState { 380 SysBusDevice parent_obj; 381 382 uint32_t n_in; /* inputs amount */ 383 uint32_t *level; /* input levels */ 384 qemu_irq out; /* output IRQ */ 385 } Exynos4210IRQGateState; 386 387 static Property exynos4210_irq_gate_properties[] = { 388 DEFINE_PROP_UINT32("n_in", Exynos4210IRQGateState, n_in, 1), 389 DEFINE_PROP_END_OF_LIST(), 390 }; 391 392 static const VMStateDescription vmstate_exynos4210_irq_gate = { 393 .name = "exynos4210.irq_gate", 394 .version_id = 2, 395 .minimum_version_id = 2, 396 .fields = (VMStateField[]) { 397 VMSTATE_VBUFFER_UINT32(level, Exynos4210IRQGateState, 1, NULL, n_in), 398 VMSTATE_END_OF_LIST() 399 } 400 }; 401 402 /* Process a change in IRQ input. */ 403 static void exynos4210_irq_gate_handler(void *opaque, int irq, int level) 404 { 405 Exynos4210IRQGateState *s = (Exynos4210IRQGateState *)opaque; 406 uint32_t i; 407 408 assert(irq < s->n_in); 409 410 s->level[irq] = level; 411 412 for (i = 0; i < s->n_in; i++) { 413 if (s->level[i] >= 1) { 414 qemu_irq_raise(s->out); 415 return; 416 } 417 } 418 419 qemu_irq_lower(s->out); 420 } 421 422 static void exynos4210_irq_gate_reset(DeviceState *d) 423 { 424 Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(d); 425 426 memset(s->level, 0, s->n_in * sizeof(*s->level)); 427 } 428 429 /* 430 * IRQ Gate initialization. 431 */ 432 static void exynos4210_irq_gate_init(Object *obj) 433 { 434 Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(obj); 435 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 436 437 sysbus_init_irq(sbd, &s->out); 438 } 439 440 static void exynos4210_irq_gate_realize(DeviceState *dev, Error **errp) 441 { 442 Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(dev); 443 444 /* Allocate general purpose input signals and connect a handler to each of 445 * them */ 446 qdev_init_gpio_in(dev, exynos4210_irq_gate_handler, s->n_in); 447 448 s->level = g_malloc0(s->n_in * sizeof(*s->level)); 449 } 450 451 static void exynos4210_irq_gate_class_init(ObjectClass *klass, void *data) 452 { 453 DeviceClass *dc = DEVICE_CLASS(klass); 454 455 dc->reset = exynos4210_irq_gate_reset; 456 dc->vmsd = &vmstate_exynos4210_irq_gate; 457 dc->props = exynos4210_irq_gate_properties; 458 dc->realize = exynos4210_irq_gate_realize; 459 } 460 461 static const TypeInfo exynos4210_irq_gate_info = { 462 .name = TYPE_EXYNOS4210_IRQ_GATE, 463 .parent = TYPE_SYS_BUS_DEVICE, 464 .instance_size = sizeof(Exynos4210IRQGateState), 465 .instance_init = exynos4210_irq_gate_init, 466 .class_init = exynos4210_irq_gate_class_init, 467 }; 468 469 static void exynos4210_irq_gate_register_types(void) 470 { 471 type_register_static(&exynos4210_irq_gate_info); 472 } 473 474 type_init(exynos4210_irq_gate_register_types) 475