1 /* 2 * Samsung exynos4210 GIC implementation. Based on hw/arm_gic.c 3 * 4 * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd. 5 * All rights reserved. 6 * 7 * Evgeny Voevodin <e.voevodin@samsung.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 17 * See the GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "hw/sysbus.h" 25 #include "migration/vmstate.h" 26 #include "qapi/error.h" 27 #include "qemu/module.h" 28 #include "hw/irq.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/arm/exynos4210.h" 31 32 enum ExtGicId { 33 EXT_GIC_ID_MDMA_LCD0 = 66, 34 EXT_GIC_ID_PDMA0, 35 EXT_GIC_ID_PDMA1, 36 EXT_GIC_ID_TIMER0, 37 EXT_GIC_ID_TIMER1, 38 EXT_GIC_ID_TIMER2, 39 EXT_GIC_ID_TIMER3, 40 EXT_GIC_ID_TIMER4, 41 EXT_GIC_ID_MCT_L0, 42 EXT_GIC_ID_WDT, 43 EXT_GIC_ID_RTC_ALARM, 44 EXT_GIC_ID_RTC_TIC, 45 EXT_GIC_ID_GPIO_XB, 46 EXT_GIC_ID_GPIO_XA, 47 EXT_GIC_ID_MCT_L1, 48 EXT_GIC_ID_IEM_APC, 49 EXT_GIC_ID_IEM_IEC, 50 EXT_GIC_ID_NFC, 51 EXT_GIC_ID_UART0, 52 EXT_GIC_ID_UART1, 53 EXT_GIC_ID_UART2, 54 EXT_GIC_ID_UART3, 55 EXT_GIC_ID_UART4, 56 EXT_GIC_ID_MCT_G0, 57 EXT_GIC_ID_I2C0, 58 EXT_GIC_ID_I2C1, 59 EXT_GIC_ID_I2C2, 60 EXT_GIC_ID_I2C3, 61 EXT_GIC_ID_I2C4, 62 EXT_GIC_ID_I2C5, 63 EXT_GIC_ID_I2C6, 64 EXT_GIC_ID_I2C7, 65 EXT_GIC_ID_SPI0, 66 EXT_GIC_ID_SPI1, 67 EXT_GIC_ID_SPI2, 68 EXT_GIC_ID_MCT_G1, 69 EXT_GIC_ID_USB_HOST, 70 EXT_GIC_ID_USB_DEVICE, 71 EXT_GIC_ID_MODEMIF, 72 EXT_GIC_ID_HSMMC0, 73 EXT_GIC_ID_HSMMC1, 74 EXT_GIC_ID_HSMMC2, 75 EXT_GIC_ID_HSMMC3, 76 EXT_GIC_ID_SDMMC, 77 EXT_GIC_ID_MIPI_CSI_4LANE, 78 EXT_GIC_ID_MIPI_DSI_4LANE, 79 EXT_GIC_ID_MIPI_CSI_2LANE, 80 EXT_GIC_ID_MIPI_DSI_2LANE, 81 EXT_GIC_ID_ONENAND_AUDI, 82 EXT_GIC_ID_ROTATOR, 83 EXT_GIC_ID_FIMC0, 84 EXT_GIC_ID_FIMC1, 85 EXT_GIC_ID_FIMC2, 86 EXT_GIC_ID_FIMC3, 87 EXT_GIC_ID_JPEG, 88 EXT_GIC_ID_2D, 89 EXT_GIC_ID_PCIe, 90 EXT_GIC_ID_MIXER, 91 EXT_GIC_ID_HDMI, 92 EXT_GIC_ID_HDMI_I2C, 93 EXT_GIC_ID_MFC, 94 EXT_GIC_ID_TVENC, 95 }; 96 97 enum ExtInt { 98 EXT_GIC_ID_EXTINT0 = 48, 99 EXT_GIC_ID_EXTINT1, 100 EXT_GIC_ID_EXTINT2, 101 EXT_GIC_ID_EXTINT3, 102 EXT_GIC_ID_EXTINT4, 103 EXT_GIC_ID_EXTINT5, 104 EXT_GIC_ID_EXTINT6, 105 EXT_GIC_ID_EXTINT7, 106 EXT_GIC_ID_EXTINT8, 107 EXT_GIC_ID_EXTINT9, 108 EXT_GIC_ID_EXTINT10, 109 EXT_GIC_ID_EXTINT11, 110 EXT_GIC_ID_EXTINT12, 111 EXT_GIC_ID_EXTINT13, 112 EXT_GIC_ID_EXTINT14, 113 EXT_GIC_ID_EXTINT15 114 }; 115 116 /* 117 * External GIC sources which are not from External Interrupt Combiner or 118 * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ, 119 * which is INTG16 in Internal Interrupt Combiner. 120 */ 121 122 static const uint32_t 123 combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { 124 /* int combiner groups 16-19 */ 125 { }, { }, { }, { }, 126 /* int combiner group 20 */ 127 { 0, EXT_GIC_ID_MDMA_LCD0 }, 128 /* int combiner group 21 */ 129 { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 }, 130 /* int combiner group 22 */ 131 { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2, 132 EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 }, 133 /* int combiner group 23 */ 134 { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC }, 135 /* int combiner group 24 */ 136 { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA }, 137 /* int combiner group 25 */ 138 { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC }, 139 /* int combiner group 26 */ 140 { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3, 141 EXT_GIC_ID_UART4 }, 142 /* int combiner group 27 */ 143 { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3, 144 EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6, 145 EXT_GIC_ID_I2C7 }, 146 /* int combiner group 28 */ 147 { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST}, 148 /* int combiner group 29 */ 149 { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2, 150 EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC }, 151 /* int combiner group 30 */ 152 { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE }, 153 /* int combiner group 31 */ 154 { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE }, 155 /* int combiner group 32 */ 156 { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 }, 157 /* int combiner group 33 */ 158 { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 }, 159 /* int combiner group 34 */ 160 { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC }, 161 /* int combiner group 35 */ 162 { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, 163 /* int combiner group 36 */ 164 { EXT_GIC_ID_MIXER }, 165 /* int combiner group 37 */ 166 { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6, 167 EXT_GIC_ID_EXTINT7 }, 168 /* groups 38-50 */ 169 { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, 170 /* int combiner group 51 */ 171 { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, 172 /* group 52 */ 173 { }, 174 /* int combiner group 53 */ 175 { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, 176 /* groups 54-63 */ 177 { }, { }, { }, { }, { }, { }, { }, { }, { }, { } 178 }; 179 180 #define EXYNOS4210_GIC_NIRQ 160 181 182 #define EXYNOS4210_EXT_GIC_CPU_REGION_SIZE 0x10000 183 #define EXYNOS4210_EXT_GIC_DIST_REGION_SIZE 0x10000 184 185 #define EXYNOS4210_EXT_GIC_PER_CPU_OFFSET 0x8000 186 #define EXYNOS4210_EXT_GIC_CPU_GET_OFFSET(n) \ 187 ((n) * EXYNOS4210_EXT_GIC_PER_CPU_OFFSET) 188 #define EXYNOS4210_EXT_GIC_DIST_GET_OFFSET(n) \ 189 ((n) * EXYNOS4210_EXT_GIC_PER_CPU_OFFSET) 190 191 #define EXYNOS4210_GIC_CPU_REGION_SIZE 0x100 192 #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000 193 194 static void exynos4210_irq_handler(void *opaque, int irq, int level) 195 { 196 Exynos4210Irq *s = (Exynos4210Irq *)opaque; 197 198 /* Bypass */ 199 qemu_set_irq(s->board_irqs[irq], level); 200 } 201 202 /* 203 * Initialize exynos4210 IRQ subsystem stub. 204 */ 205 qemu_irq *exynos4210_init_irq(Exynos4210Irq *s) 206 { 207 return qemu_allocate_irqs(exynos4210_irq_handler, s, 208 EXYNOS4210_MAX_INT_COMBINER_IN_IRQ); 209 } 210 211 /* 212 * Initialize board IRQs. 213 * These IRQs contain splitted Int/External Combiner and External Gic IRQs. 214 */ 215 void exynos4210_init_board_irqs(Exynos4210Irq *s) 216 { 217 uint32_t grp, bit, irq_id, n; 218 219 for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { 220 irq_id = 0; 221 if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) || 222 n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) { 223 /* MCT_G0 is passed to External GIC */ 224 irq_id = EXT_GIC_ID_MCT_G0; 225 } 226 if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) || 227 n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) { 228 /* MCT_G1 is passed to External and GIC */ 229 irq_id = EXT_GIC_ID_MCT_G1; 230 } 231 if (irq_id) { 232 s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n], 233 s->ext_gic_irq[irq_id-32]); 234 } else { 235 s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n], 236 s->ext_combiner_irq[n]); 237 } 238 } 239 for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { 240 /* these IDs are passed to Internal Combiner and External GIC */ 241 grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n); 242 bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n); 243 irq_id = combiner_grp_to_gic_id[grp - 244 EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; 245 246 if (irq_id) { 247 s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n], 248 s->ext_gic_irq[irq_id-32]); 249 } 250 } 251 } 252 253 /* 254 * Get IRQ number from exynos4210 IRQ subsystem stub. 255 * To identify IRQ source use internal combiner group and bit number 256 * grp - group number 257 * bit - bit number inside group 258 */ 259 uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit) 260 { 261 return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit); 262 } 263 264 /********* GIC part *********/ 265 266 #define TYPE_EXYNOS4210_GIC "exynos4210.gic" 267 #define EXYNOS4210_GIC(obj) \ 268 OBJECT_CHECK(Exynos4210GicState, (obj), TYPE_EXYNOS4210_GIC) 269 270 typedef struct { 271 SysBusDevice parent_obj; 272 273 MemoryRegion cpu_container; 274 MemoryRegion dist_container; 275 MemoryRegion cpu_alias[EXYNOS4210_NCPUS]; 276 MemoryRegion dist_alias[EXYNOS4210_NCPUS]; 277 uint32_t num_cpu; 278 DeviceState *gic; 279 } Exynos4210GicState; 280 281 static void exynos4210_gic_set_irq(void *opaque, int irq, int level) 282 { 283 Exynos4210GicState *s = (Exynos4210GicState *)opaque; 284 qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); 285 } 286 287 static void exynos4210_gic_realize(DeviceState *dev, Error **errp) 288 { 289 Object *obj = OBJECT(dev); 290 Exynos4210GicState *s = EXYNOS4210_GIC(obj); 291 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 292 const char cpu_prefix[] = "exynos4210-gic-alias_cpu"; 293 const char dist_prefix[] = "exynos4210-gic-alias_dist"; 294 char cpu_alias_name[sizeof(cpu_prefix) + 3]; 295 char dist_alias_name[sizeof(cpu_prefix) + 3]; 296 SysBusDevice *gicbusdev; 297 uint32_t n = s->num_cpu; 298 uint32_t i; 299 300 s->gic = qdev_new("arm_gic"); 301 qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); 302 qdev_prop_set_uint32(s->gic, "num-irq", EXYNOS4210_GIC_NIRQ); 303 gicbusdev = SYS_BUS_DEVICE(s->gic); 304 sysbus_realize_and_unref(gicbusdev, &error_fatal); 305 306 /* Pass through outbound IRQ lines from the GIC */ 307 sysbus_pass_irq(sbd, gicbusdev); 308 309 /* Pass through inbound GPIO lines to the GIC */ 310 qdev_init_gpio_in(dev, exynos4210_gic_set_irq, 311 EXYNOS4210_GIC_NIRQ - 32); 312 313 memory_region_init(&s->cpu_container, obj, "exynos4210-cpu-container", 314 EXYNOS4210_EXT_GIC_CPU_REGION_SIZE); 315 memory_region_init(&s->dist_container, obj, "exynos4210-dist-container", 316 EXYNOS4210_EXT_GIC_DIST_REGION_SIZE); 317 318 /* 319 * This clues in gcc that our on-stack buffers do, in fact have 320 * enough room for the cpu numbers. gcc 9.2.1 on 32-bit x86 321 * doesn't figure this out, otherwise and gives spurious warnings. 322 */ 323 assert(n <= EXYNOS4210_NCPUS); 324 for (i = 0; i < n; i++) { 325 /* Map CPU interface per SMP Core */ 326 sprintf(cpu_alias_name, "%s%x", cpu_prefix, i); 327 memory_region_init_alias(&s->cpu_alias[i], obj, 328 cpu_alias_name, 329 sysbus_mmio_get_region(gicbusdev, 1), 330 0, 331 EXYNOS4210_GIC_CPU_REGION_SIZE); 332 memory_region_add_subregion(&s->cpu_container, 333 EXYNOS4210_EXT_GIC_CPU_GET_OFFSET(i), &s->cpu_alias[i]); 334 335 /* Map Distributor per SMP Core */ 336 sprintf(dist_alias_name, "%s%x", dist_prefix, i); 337 memory_region_init_alias(&s->dist_alias[i], obj, 338 dist_alias_name, 339 sysbus_mmio_get_region(gicbusdev, 0), 340 0, 341 EXYNOS4210_GIC_DIST_REGION_SIZE); 342 memory_region_add_subregion(&s->dist_container, 343 EXYNOS4210_EXT_GIC_DIST_GET_OFFSET(i), &s->dist_alias[i]); 344 } 345 346 sysbus_init_mmio(sbd, &s->cpu_container); 347 sysbus_init_mmio(sbd, &s->dist_container); 348 } 349 350 static Property exynos4210_gic_properties[] = { 351 DEFINE_PROP_UINT32("num-cpu", Exynos4210GicState, num_cpu, 1), 352 DEFINE_PROP_END_OF_LIST(), 353 }; 354 355 static void exynos4210_gic_class_init(ObjectClass *klass, void *data) 356 { 357 DeviceClass *dc = DEVICE_CLASS(klass); 358 359 device_class_set_props(dc, exynos4210_gic_properties); 360 dc->realize = exynos4210_gic_realize; 361 } 362 363 static const TypeInfo exynos4210_gic_info = { 364 .name = TYPE_EXYNOS4210_GIC, 365 .parent = TYPE_SYS_BUS_DEVICE, 366 .instance_size = sizeof(Exynos4210GicState), 367 .class_init = exynos4210_gic_class_init, 368 }; 369 370 static void exynos4210_gic_register_types(void) 371 { 372 type_register_static(&exynos4210_gic_info); 373 } 374 375 type_init(exynos4210_gic_register_types) 376 377 /* IRQ OR Gate struct. 378 * 379 * This device models an OR gate. There are n_in input qdev gpio lines and one 380 * output sysbus IRQ line. The output IRQ level is formed as OR between all 381 * gpio inputs. 382 */ 383 384 #define TYPE_EXYNOS4210_IRQ_GATE "exynos4210.irq_gate" 385 #define EXYNOS4210_IRQ_GATE(obj) \ 386 OBJECT_CHECK(Exynos4210IRQGateState, (obj), TYPE_EXYNOS4210_IRQ_GATE) 387 388 typedef struct Exynos4210IRQGateState { 389 SysBusDevice parent_obj; 390 391 uint32_t n_in; /* inputs amount */ 392 uint32_t *level; /* input levels */ 393 qemu_irq out; /* output IRQ */ 394 } Exynos4210IRQGateState; 395 396 static Property exynos4210_irq_gate_properties[] = { 397 DEFINE_PROP_UINT32("n_in", Exynos4210IRQGateState, n_in, 1), 398 DEFINE_PROP_END_OF_LIST(), 399 }; 400 401 static const VMStateDescription vmstate_exynos4210_irq_gate = { 402 .name = "exynos4210.irq_gate", 403 .version_id = 2, 404 .minimum_version_id = 2, 405 .fields = (VMStateField[]) { 406 VMSTATE_VBUFFER_UINT32(level, Exynos4210IRQGateState, 1, NULL, n_in), 407 VMSTATE_END_OF_LIST() 408 } 409 }; 410 411 /* Process a change in IRQ input. */ 412 static void exynos4210_irq_gate_handler(void *opaque, int irq, int level) 413 { 414 Exynos4210IRQGateState *s = (Exynos4210IRQGateState *)opaque; 415 uint32_t i; 416 417 assert(irq < s->n_in); 418 419 s->level[irq] = level; 420 421 for (i = 0; i < s->n_in; i++) { 422 if (s->level[i] >= 1) { 423 qemu_irq_raise(s->out); 424 return; 425 } 426 } 427 428 qemu_irq_lower(s->out); 429 } 430 431 static void exynos4210_irq_gate_reset(DeviceState *d) 432 { 433 Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(d); 434 435 memset(s->level, 0, s->n_in * sizeof(*s->level)); 436 } 437 438 /* 439 * IRQ Gate initialization. 440 */ 441 static void exynos4210_irq_gate_init(Object *obj) 442 { 443 Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(obj); 444 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 445 446 sysbus_init_irq(sbd, &s->out); 447 } 448 449 static void exynos4210_irq_gate_realize(DeviceState *dev, Error **errp) 450 { 451 Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(dev); 452 453 /* Allocate general purpose input signals and connect a handler to each of 454 * them */ 455 qdev_init_gpio_in(dev, exynos4210_irq_gate_handler, s->n_in); 456 457 s->level = g_malloc0(s->n_in * sizeof(*s->level)); 458 } 459 460 static void exynos4210_irq_gate_class_init(ObjectClass *klass, void *data) 461 { 462 DeviceClass *dc = DEVICE_CLASS(klass); 463 464 dc->reset = exynos4210_irq_gate_reset; 465 dc->vmsd = &vmstate_exynos4210_irq_gate; 466 device_class_set_props(dc, exynos4210_irq_gate_properties); 467 dc->realize = exynos4210_irq_gate_realize; 468 } 469 470 static const TypeInfo exynos4210_irq_gate_info = { 471 .name = TYPE_EXYNOS4210_IRQ_GATE, 472 .parent = TYPE_SYS_BUS_DEVICE, 473 .instance_size = sizeof(Exynos4210IRQGateState), 474 .instance_init = exynos4210_irq_gate_init, 475 .class_init = exynos4210_irq_gate_class_init, 476 }; 477 478 static void exynos4210_irq_gate_register_types(void) 479 { 480 type_register_static(&exynos4210_irq_gate_info); 481 } 482 483 type_init(exynos4210_irq_gate_register_types) 484