1 /* 2 * Raspberry Pi emulation (c) 2012 Gregory Estrade 3 * Refactoring for Pi2 Copyright (c) 2015, Microsoft. Written by Andrew Baumann. 4 * This code is licensed under the GNU GPLv2 and later. 5 * Heavily based on pl190.c, copyright terms below: 6 * 7 * Arm PrimeCell PL190 Vector Interrupt Controller 8 * 9 * Copyright (c) 2006 CodeSourcery. 10 * Written by Paul Brook 11 * 12 * This code is licensed under the GPL. 13 */ 14 15 #include "qemu/osdep.h" 16 #include "hw/intc/bcm2835_ic.h" 17 #include "hw/irq.h" 18 #include "qemu/log.h" 19 #include "qemu/module.h" 20 21 #define GPU_IRQS 64 22 #define ARM_IRQS 8 23 24 #define IRQ_PENDING_BASIC 0x00 /* IRQ basic pending */ 25 #define IRQ_PENDING_1 0x04 /* IRQ pending 1 */ 26 #define IRQ_PENDING_2 0x08 /* IRQ pending 2 */ 27 #define FIQ_CONTROL 0x0C /* FIQ register */ 28 #define IRQ_ENABLE_1 0x10 /* Interrupt enable register 1 */ 29 #define IRQ_ENABLE_2 0x14 /* Interrupt enable register 2 */ 30 #define IRQ_ENABLE_BASIC 0x18 /* Base interrupt enable register */ 31 #define IRQ_DISABLE_1 0x1C /* Interrupt disable register 1 */ 32 #define IRQ_DISABLE_2 0x20 /* Interrupt disable register 2 */ 33 #define IRQ_DISABLE_BASIC 0x24 /* Base interrupt disable register */ 34 35 /* Update interrupts. */ 36 static void bcm2835_ic_update(BCM2835ICState *s) 37 { 38 bool set = false; 39 40 if (s->fiq_enable) { 41 if (s->fiq_select >= GPU_IRQS) { 42 /* ARM IRQ */ 43 set = extract32(s->arm_irq_level, s->fiq_select - GPU_IRQS, 1); 44 } else { 45 set = extract64(s->gpu_irq_level, s->fiq_select, 1); 46 } 47 } 48 qemu_set_irq(s->fiq, set); 49 50 set = (s->gpu_irq_level & s->gpu_irq_enable) 51 || (s->arm_irq_level & s->arm_irq_enable); 52 qemu_set_irq(s->irq, set); 53 54 } 55 56 static void bcm2835_ic_set_gpu_irq(void *opaque, int irq, int level) 57 { 58 BCM2835ICState *s = opaque; 59 60 assert(irq >= 0 && irq < 64); 61 s->gpu_irq_level = deposit64(s->gpu_irq_level, irq, 1, level != 0); 62 bcm2835_ic_update(s); 63 } 64 65 static void bcm2835_ic_set_arm_irq(void *opaque, int irq, int level) 66 { 67 BCM2835ICState *s = opaque; 68 69 assert(irq >= 0 && irq < 8); 70 s->arm_irq_level = deposit32(s->arm_irq_level, irq, 1, level != 0); 71 bcm2835_ic_update(s); 72 } 73 74 static const int irq_dups[] = { 7, 9, 10, 18, 19, 53, 54, 55, 56, 57, 62 }; 75 76 static uint64_t bcm2835_ic_read(void *opaque, hwaddr offset, unsigned size) 77 { 78 BCM2835ICState *s = opaque; 79 uint32_t res = 0; 80 uint64_t gpu_pending = s->gpu_irq_level & s->gpu_irq_enable; 81 int i; 82 83 switch (offset) { 84 case IRQ_PENDING_BASIC: 85 /* bits 0-7: ARM irqs */ 86 res = s->arm_irq_level & s->arm_irq_enable; 87 88 /* bits 8 & 9: pending registers 1 & 2 */ 89 res |= (((uint32_t)gpu_pending) != 0) << 8; 90 res |= ((gpu_pending >> 32) != 0) << 9; 91 92 /* bits 10-20: selected GPU IRQs */ 93 for (i = 0; i < ARRAY_SIZE(irq_dups); i++) { 94 res |= extract64(gpu_pending, irq_dups[i], 1) << (i + 10); 95 } 96 break; 97 case IRQ_PENDING_1: 98 res = gpu_pending; 99 break; 100 case IRQ_PENDING_2: 101 res = gpu_pending >> 32; 102 break; 103 case FIQ_CONTROL: 104 res = (s->fiq_enable << 7) | s->fiq_select; 105 break; 106 case IRQ_ENABLE_1: 107 res = s->gpu_irq_enable; 108 break; 109 case IRQ_ENABLE_2: 110 res = s->gpu_irq_enable >> 32; 111 break; 112 case IRQ_ENABLE_BASIC: 113 res = s->arm_irq_enable; 114 break; 115 case IRQ_DISABLE_1: 116 res = ~s->gpu_irq_enable; 117 break; 118 case IRQ_DISABLE_2: 119 res = ~s->gpu_irq_enable >> 32; 120 break; 121 case IRQ_DISABLE_BASIC: 122 res = ~s->arm_irq_enable; 123 break; 124 default: 125 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", 126 __func__, offset); 127 return 0; 128 } 129 130 return res; 131 } 132 133 static void bcm2835_ic_write(void *opaque, hwaddr offset, uint64_t val, 134 unsigned size) 135 { 136 BCM2835ICState *s = opaque; 137 138 switch (offset) { 139 case FIQ_CONTROL: 140 s->fiq_select = extract32(val, 0, 7); 141 s->fiq_enable = extract32(val, 7, 1); 142 break; 143 case IRQ_ENABLE_1: 144 s->gpu_irq_enable |= val; 145 break; 146 case IRQ_ENABLE_2: 147 s->gpu_irq_enable |= val << 32; 148 break; 149 case IRQ_ENABLE_BASIC: 150 s->arm_irq_enable |= val & 0xff; 151 break; 152 case IRQ_DISABLE_1: 153 s->gpu_irq_enable &= ~val; 154 break; 155 case IRQ_DISABLE_2: 156 s->gpu_irq_enable &= ~(val << 32); 157 break; 158 case IRQ_DISABLE_BASIC: 159 s->arm_irq_enable &= ~val & 0xff; 160 break; 161 default: 162 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", 163 __func__, offset); 164 return; 165 } 166 bcm2835_ic_update(s); 167 } 168 169 static const MemoryRegionOps bcm2835_ic_ops = { 170 .read = bcm2835_ic_read, 171 .write = bcm2835_ic_write, 172 .endianness = DEVICE_NATIVE_ENDIAN, 173 .valid.min_access_size = 4, 174 .valid.max_access_size = 4, 175 }; 176 177 static void bcm2835_ic_reset(DeviceState *d) 178 { 179 BCM2835ICState *s = BCM2835_IC(d); 180 181 s->gpu_irq_enable = 0; 182 s->arm_irq_enable = 0; 183 s->fiq_enable = false; 184 s->fiq_select = 0; 185 } 186 187 static void bcm2835_ic_init(Object *obj) 188 { 189 BCM2835ICState *s = BCM2835_IC(obj); 190 191 memory_region_init_io(&s->iomem, obj, &bcm2835_ic_ops, s, TYPE_BCM2835_IC, 192 0x200); 193 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); 194 195 qdev_init_gpio_in_named(DEVICE(s), bcm2835_ic_set_gpu_irq, 196 BCM2835_IC_GPU_IRQ, GPU_IRQS); 197 qdev_init_gpio_in_named(DEVICE(s), bcm2835_ic_set_arm_irq, 198 BCM2835_IC_ARM_IRQ, ARM_IRQS); 199 200 sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq); 201 sysbus_init_irq(SYS_BUS_DEVICE(s), &s->fiq); 202 } 203 204 static const VMStateDescription vmstate_bcm2835_ic = { 205 .name = TYPE_BCM2835_IC, 206 .version_id = 1, 207 .minimum_version_id = 1, 208 .fields = (VMStateField[]) { 209 VMSTATE_UINT64(gpu_irq_level, BCM2835ICState), 210 VMSTATE_UINT64(gpu_irq_enable, BCM2835ICState), 211 VMSTATE_UINT8(arm_irq_level, BCM2835ICState), 212 VMSTATE_UINT8(arm_irq_enable, BCM2835ICState), 213 VMSTATE_BOOL(fiq_enable, BCM2835ICState), 214 VMSTATE_UINT8(fiq_select, BCM2835ICState), 215 VMSTATE_END_OF_LIST() 216 } 217 }; 218 219 static void bcm2835_ic_class_init(ObjectClass *klass, void *data) 220 { 221 DeviceClass *dc = DEVICE_CLASS(klass); 222 223 dc->reset = bcm2835_ic_reset; 224 dc->vmsd = &vmstate_bcm2835_ic; 225 } 226 227 static TypeInfo bcm2835_ic_info = { 228 .name = TYPE_BCM2835_IC, 229 .parent = TYPE_SYS_BUS_DEVICE, 230 .instance_size = sizeof(BCM2835ICState), 231 .class_init = bcm2835_ic_class_init, 232 .instance_init = bcm2835_ic_init, 233 }; 234 235 static void bcm2835_ic_register_types(void) 236 { 237 type_register_static(&bcm2835_ic_info); 238 } 239 240 type_init(bcm2835_ic_register_types) 241