1 /* 2 * ASPEED INTC Controller 3 * 4 * Copyright (C) 2024 ASPEED Technology Inc. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 9 #include "qemu/osdep.h" 10 #include "hw/intc/aspeed_intc.h" 11 #include "hw/irq.h" 12 #include "qemu/log.h" 13 #include "trace.h" 14 #include "hw/registerfields.h" 15 #include "qapi/error.h" 16 17 /* 18 * INTC Registers 19 * 20 * values below are offset by - 0x1000 from datasheet 21 * because its memory region is start at 0x1000 22 * 23 */ 24 REG32(GICINT128_EN, 0x000) 25 REG32(GICINT128_STATUS, 0x004) 26 REG32(GICINT129_EN, 0x100) 27 REG32(GICINT129_STATUS, 0x104) 28 REG32(GICINT130_EN, 0x200) 29 REG32(GICINT130_STATUS, 0x204) 30 REG32(GICINT131_EN, 0x300) 31 REG32(GICINT131_STATUS, 0x304) 32 REG32(GICINT132_EN, 0x400) 33 REG32(GICINT132_STATUS, 0x404) 34 REG32(GICINT133_EN, 0x500) 35 REG32(GICINT133_STATUS, 0x504) 36 REG32(GICINT134_EN, 0x600) 37 REG32(GICINT134_STATUS, 0x604) 38 REG32(GICINT135_EN, 0x700) 39 REG32(GICINT135_STATUS, 0x704) 40 REG32(GICINT136_EN, 0x800) 41 REG32(GICINT136_STATUS, 0x804) 42 43 #define GICINT_STATUS_BASE R_GICINT128_STATUS 44 45 /* 46 * Update the state of an interrupt controller pin by setting 47 * the specified output pin to the given level. 48 * The input pin index should be between 0 and the number of input pins. 49 * The output pin index should be between 0 and the number of output pins. 50 */ 51 static void aspeed_intc_update(AspeedINTCState *s, int inpin_idx, 52 int outpin_idx, int level) 53 { 54 AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s); 55 const char *name = object_get_typename(OBJECT(s)); 56 57 if (inpin_idx >= aic->num_inpins) { 58 qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid input pin index: %d\n", 59 __func__, inpin_idx); 60 return; 61 } 62 63 if (outpin_idx >= aic->num_outpins) { 64 qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid output pin index: %d\n", 65 __func__, outpin_idx); 66 return; 67 } 68 69 trace_aspeed_intc_update_irq(name, inpin_idx, outpin_idx, level); 70 qemu_set_irq(s->output_pins[outpin_idx], level); 71 } 72 73 /* 74 * The address of GICINT128 to GICINT136 are from 0x1000 to 0x1804. 75 * Utilize "address & 0x0f00" to get the irq and irq output pin index 76 * The value of irq should be 0 to num_inpins. 77 * The irq 0 indicates GICINT128, irq 1 indicates GICINT129 and so on. 78 */ 79 static void aspeed_intc_set_irq(void *opaque, int irq, int level) 80 { 81 AspeedINTCState *s = (AspeedINTCState *)opaque; 82 AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s); 83 const char *name = object_get_typename(OBJECT(s)); 84 uint32_t status_reg = GICINT_STATUS_BASE + ((0x100 * irq) >> 2); 85 uint32_t select = 0; 86 uint32_t enable; 87 int outpin_idx; 88 int inpin_idx; 89 int i; 90 91 outpin_idx = irq; 92 inpin_idx = irq; 93 94 if (irq >= aic->num_inpins) { 95 qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid input pin index: %d\n", 96 __func__, irq); 97 return; 98 } 99 100 trace_aspeed_intc_set_irq(name, inpin_idx, level); 101 enable = s->enable[inpin_idx]; 102 103 if (!level) { 104 return; 105 } 106 107 for (i = 0; i < aic->num_lines; i++) { 108 if (s->orgates[inpin_idx].levels[i]) { 109 if (enable & BIT(i)) { 110 select |= BIT(i); 111 } 112 } 113 } 114 115 if (!select) { 116 return; 117 } 118 119 trace_aspeed_intc_select(name, select); 120 121 if (s->mask[inpin_idx] || s->regs[status_reg]) { 122 /* 123 * a. mask is not 0 means in ISR mode 124 * sources interrupt routine are executing. 125 * b. status register value is not 0 means previous 126 * source interrupt does not be executed, yet. 127 * 128 * save source interrupt to pending variable. 129 */ 130 s->pending[inpin_idx] |= select; 131 trace_aspeed_intc_pending_irq(name, inpin_idx, s->pending[inpin_idx]); 132 } else { 133 /* 134 * notify firmware which source interrupt are coming 135 * by setting status register 136 */ 137 s->regs[status_reg] = select; 138 trace_aspeed_intc_trigger_irq(name, inpin_idx, outpin_idx, 139 s->regs[status_reg]); 140 aspeed_intc_update(s, inpin_idx, outpin_idx, 1); 141 } 142 } 143 144 static void aspeed_intc_enable_handler(AspeedINTCState *s, hwaddr offset, 145 uint64_t data) 146 { 147 AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s); 148 const char *name = object_get_typename(OBJECT(s)); 149 uint32_t reg = offset >> 2; 150 uint32_t old_enable; 151 uint32_t change; 152 int inpin_idx; 153 uint32_t irq; 154 155 irq = (offset & 0x0f00) >> 8; 156 inpin_idx = irq; 157 158 if (inpin_idx >= aic->num_inpins) { 159 qemu_log_mask(LOG_GUEST_ERROR, 160 "%s: Invalid input pin index: %d\n", 161 __func__, inpin_idx); 162 return; 163 } 164 165 /* 166 * The enable registers are used to enable source interrupts. 167 * They also handle masking and unmasking of source interrupts 168 * during the execution of the source ISR. 169 */ 170 171 /* disable all source interrupt */ 172 if (!data && !s->enable[inpin_idx]) { 173 s->regs[reg] = data; 174 return; 175 } 176 177 old_enable = s->enable[inpin_idx]; 178 s->enable[inpin_idx] |= data; 179 180 /* enable new source interrupt */ 181 if (old_enable != s->enable[inpin_idx]) { 182 trace_aspeed_intc_enable(name, s->enable[inpin_idx]); 183 s->regs[reg] = data; 184 return; 185 } 186 187 /* mask and unmask source interrupt */ 188 change = s->regs[reg] ^ data; 189 if (change & data) { 190 s->mask[inpin_idx] &= ~change; 191 trace_aspeed_intc_unmask(name, change, s->mask[inpin_idx]); 192 } else { 193 s->mask[inpin_idx] |= change; 194 trace_aspeed_intc_mask(name, change, s->mask[inpin_idx]); 195 } 196 197 s->regs[reg] = data; 198 } 199 200 static void aspeed_intc_status_handler(AspeedINTCState *s, hwaddr offset, 201 uint64_t data) 202 { 203 AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s); 204 const char *name = object_get_typename(OBJECT(s)); 205 uint32_t reg = offset >> 2; 206 int outpin_idx; 207 int inpin_idx; 208 uint32_t irq; 209 210 if (!data) { 211 qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid data 0\n", __func__); 212 return; 213 } 214 215 irq = (offset & 0x0f00) >> 8; 216 outpin_idx = irq; 217 inpin_idx = irq; 218 219 if (inpin_idx >= aic->num_inpins) { 220 qemu_log_mask(LOG_GUEST_ERROR, 221 "%s: Invalid input pin index: %d\n", 222 __func__, inpin_idx); 223 return; 224 } 225 226 /* clear status */ 227 s->regs[reg] &= ~data; 228 229 /* 230 * These status registers are used for notify sources ISR are executed. 231 * If one source ISR is executed, it will clear one bit. 232 * If it clear all bits, it means to initialize this register status 233 * rather than sources ISR are executed. 234 */ 235 if (data == 0xffffffff) { 236 return; 237 } 238 239 /* All source ISR execution are done */ 240 if (!s->regs[reg]) { 241 trace_aspeed_intc_all_isr_done(name, inpin_idx); 242 if (s->pending[inpin_idx]) { 243 /* 244 * handle pending source interrupt 245 * notify firmware which source interrupt are pending 246 * by setting status register 247 */ 248 s->regs[reg] = s->pending[inpin_idx]; 249 s->pending[inpin_idx] = 0; 250 trace_aspeed_intc_trigger_irq(name, inpin_idx, outpin_idx, 251 s->regs[reg]); 252 aspeed_intc_update(s, inpin_idx, outpin_idx, 1); 253 } else { 254 /* clear irq */ 255 trace_aspeed_intc_clear_irq(name, inpin_idx, outpin_idx, 0); 256 aspeed_intc_update(s, inpin_idx, outpin_idx, 0); 257 } 258 } 259 } 260 261 static uint64_t aspeed_intc_read(void *opaque, hwaddr offset, unsigned int size) 262 { 263 AspeedINTCState *s = ASPEED_INTC(opaque); 264 const char *name = object_get_typename(OBJECT(s)); 265 uint32_t reg = offset >> 2; 266 uint32_t value = 0; 267 268 value = s->regs[reg]; 269 trace_aspeed_intc_read(name, offset, size, value); 270 271 return value; 272 } 273 274 static void aspeed_intc_write(void *opaque, hwaddr offset, uint64_t data, 275 unsigned size) 276 { 277 AspeedINTCState *s = ASPEED_INTC(opaque); 278 const char *name = object_get_typename(OBJECT(s)); 279 uint32_t reg = offset >> 2; 280 281 trace_aspeed_intc_write(name, offset, size, data); 282 283 switch (reg) { 284 case R_GICINT128_EN: 285 case R_GICINT129_EN: 286 case R_GICINT130_EN: 287 case R_GICINT131_EN: 288 case R_GICINT132_EN: 289 case R_GICINT133_EN: 290 case R_GICINT134_EN: 291 case R_GICINT135_EN: 292 case R_GICINT136_EN: 293 aspeed_intc_enable_handler(s, offset, data); 294 break; 295 case R_GICINT128_STATUS: 296 case R_GICINT129_STATUS: 297 case R_GICINT130_STATUS: 298 case R_GICINT131_STATUS: 299 case R_GICINT132_STATUS: 300 case R_GICINT133_STATUS: 301 case R_GICINT134_STATUS: 302 case R_GICINT135_STATUS: 303 case R_GICINT136_STATUS: 304 aspeed_intc_status_handler(s, offset, data); 305 break; 306 default: 307 s->regs[reg] = data; 308 break; 309 } 310 311 return; 312 } 313 314 static const MemoryRegionOps aspeed_intc_ops = { 315 .read = aspeed_intc_read, 316 .write = aspeed_intc_write, 317 .endianness = DEVICE_LITTLE_ENDIAN, 318 .valid = { 319 .min_access_size = 4, 320 .max_access_size = 4, 321 } 322 }; 323 324 static void aspeed_intc_instance_init(Object *obj) 325 { 326 AspeedINTCState *s = ASPEED_INTC(obj); 327 AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s); 328 int i; 329 330 assert(aic->num_inpins <= ASPEED_INTC_MAX_INPINS); 331 for (i = 0; i < aic->num_inpins; i++) { 332 object_initialize_child(obj, "intc-orgates[*]", &s->orgates[i], 333 TYPE_OR_IRQ); 334 object_property_set_int(OBJECT(&s->orgates[i]), "num-lines", 335 aic->num_lines, &error_abort); 336 } 337 } 338 339 static void aspeed_intc_reset(DeviceState *dev) 340 { 341 AspeedINTCState *s = ASPEED_INTC(dev); 342 AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s); 343 344 memset(s->regs, 0, aic->nr_regs << 2); 345 memset(s->enable, 0, sizeof(s->enable)); 346 memset(s->mask, 0, sizeof(s->mask)); 347 memset(s->pending, 0, sizeof(s->pending)); 348 } 349 350 static void aspeed_intc_realize(DeviceState *dev, Error **errp) 351 { 352 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 353 AspeedINTCState *s = ASPEED_INTC(dev); 354 AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s); 355 int i; 356 357 memory_region_init(&s->iomem_container, OBJECT(s), 358 TYPE_ASPEED_INTC ".container", aic->mem_size); 359 360 sysbus_init_mmio(sbd, &s->iomem_container); 361 362 s->regs = g_new(uint32_t, aic->nr_regs); 363 memory_region_init_io(&s->iomem, OBJECT(s), aic->reg_ops, s, 364 TYPE_ASPEED_INTC ".regs", aic->nr_regs << 2); 365 366 memory_region_add_subregion(&s->iomem_container, aic->reg_offset, 367 &s->iomem); 368 369 qdev_init_gpio_in(dev, aspeed_intc_set_irq, aic->num_inpins); 370 371 for (i = 0; i < aic->num_inpins; i++) { 372 if (!qdev_realize(DEVICE(&s->orgates[i]), NULL, errp)) { 373 return; 374 } 375 } 376 377 for (i = 0; i < aic->num_outpins; i++) { 378 sysbus_init_irq(sbd, &s->output_pins[i]); 379 } 380 } 381 382 static void aspeed_intc_unrealize(DeviceState *dev) 383 { 384 AspeedINTCState *s = ASPEED_INTC(dev); 385 386 g_free(s->regs); 387 s->regs = NULL; 388 } 389 390 static void aspeed_intc_class_init(ObjectClass *klass, void *data) 391 { 392 DeviceClass *dc = DEVICE_CLASS(klass); 393 AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass); 394 395 dc->desc = "ASPEED INTC Controller"; 396 dc->realize = aspeed_intc_realize; 397 dc->unrealize = aspeed_intc_unrealize; 398 device_class_set_legacy_reset(dc, aspeed_intc_reset); 399 dc->vmsd = NULL; 400 401 aic->reg_ops = &aspeed_intc_ops; 402 } 403 404 static const TypeInfo aspeed_intc_info = { 405 .name = TYPE_ASPEED_INTC, 406 .parent = TYPE_SYS_BUS_DEVICE, 407 .instance_init = aspeed_intc_instance_init, 408 .instance_size = sizeof(AspeedINTCState), 409 .class_init = aspeed_intc_class_init, 410 .class_size = sizeof(AspeedINTCClass), 411 .abstract = true, 412 }; 413 414 static void aspeed_2700_intc_class_init(ObjectClass *klass, void *data) 415 { 416 DeviceClass *dc = DEVICE_CLASS(klass); 417 AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass); 418 419 dc->desc = "ASPEED 2700 INTC Controller"; 420 aic->num_lines = 32; 421 aic->num_inpins = 9; 422 aic->num_outpins = 9; 423 aic->mem_size = 0x4000; 424 aic->nr_regs = 0x808 >> 2; 425 aic->reg_offset = 0x1000; 426 } 427 428 static const TypeInfo aspeed_2700_intc_info = { 429 .name = TYPE_ASPEED_2700_INTC, 430 .parent = TYPE_ASPEED_INTC, 431 .class_init = aspeed_2700_intc_class_init, 432 }; 433 434 static void aspeed_intc_register_types(void) 435 { 436 type_register_static(&aspeed_intc_info); 437 type_register_static(&aspeed_2700_intc_info); 438 } 439 440 type_init(aspeed_intc_register_types); 441