1 /* 2 * ARM Nested Vectored Interrupt Controller 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 * 9 * The ARMv7M System controller is fairly tightly tied in with the 10 * NVIC. Much of that is also implemented here. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "qapi/error.h" 15 #include "hw/sysbus.h" 16 #include "migration/vmstate.h" 17 #include "qemu/timer.h" 18 #include "hw/intc/armv7m_nvic.h" 19 #include "hw/irq.h" 20 #include "hw/qdev-properties.h" 21 #include "sysemu/runstate.h" 22 #include "target/arm/cpu.h" 23 #include "exec/exec-all.h" 24 #include "exec/memop.h" 25 #include "qemu/log.h" 26 #include "qemu/module.h" 27 #include "trace.h" 28 29 /* IRQ number counting: 30 * 31 * the num-irq property counts the number of external IRQ lines 32 * 33 * NVICState::num_irq counts the total number of exceptions 34 * (external IRQs, the 15 internal exceptions including reset, 35 * and one for the unused exception number 0). 36 * 37 * NVIC_MAX_IRQ is the highest permitted number of external IRQ lines. 38 * 39 * NVIC_MAX_VECTORS is the highest permitted number of exceptions. 40 * 41 * Iterating through all exceptions should typically be done with 42 * for (i = 1; i < s->num_irq; i++) to avoid the unused slot 0. 43 * 44 * The external qemu_irq lines are the NVIC's external IRQ lines, 45 * so line 0 is exception 16. 46 * 47 * In the terminology of the architecture manual, "interrupts" are 48 * a subcategory of exception referring to the external interrupts 49 * (which are exception numbers NVIC_FIRST_IRQ and upward). 50 * For historical reasons QEMU tends to use "interrupt" and 51 * "exception" more or less interchangeably. 52 */ 53 #define NVIC_FIRST_IRQ NVIC_INTERNAL_VECTORS 54 #define NVIC_MAX_IRQ (NVIC_MAX_VECTORS - NVIC_FIRST_IRQ) 55 56 /* Effective running priority of the CPU when no exception is active 57 * (higher than the highest possible priority value) 58 */ 59 #define NVIC_NOEXC_PRIO 0x100 60 /* Maximum priority of non-secure exceptions when AIRCR.PRIS is set */ 61 #define NVIC_NS_PRIO_LIMIT 0x80 62 63 static const uint8_t nvic_id[] = { 64 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1 65 }; 66 67 static void signal_sysresetreq(NVICState *s) 68 { 69 if (qemu_irq_is_connected(s->sysresetreq)) { 70 qemu_irq_pulse(s->sysresetreq); 71 } else { 72 /* 73 * Default behaviour if the SoC doesn't need to wire up 74 * SYSRESETREQ (eg to a system reset controller of some kind): 75 * perform a system reset via the usual QEMU API. 76 */ 77 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 78 } 79 } 80 81 static int nvic_pending_prio(NVICState *s) 82 { 83 /* return the group priority of the current pending interrupt, 84 * or NVIC_NOEXC_PRIO if no interrupt is pending 85 */ 86 return s->vectpending_prio; 87 } 88 89 /* Return the value of the ISCR RETTOBASE bit: 90 * 1 if there is exactly one active exception 91 * 0 if there is more than one active exception 92 * UNKNOWN if there are no active exceptions (we choose 1, 93 * which matches the choice Cortex-M3 is documented as making). 94 * 95 * NB: some versions of the documentation talk about this 96 * counting "active exceptions other than the one shown by IPSR"; 97 * this is only different in the obscure corner case where guest 98 * code has manually deactivated an exception and is about 99 * to fail an exception-return integrity check. The definition 100 * above is the one from the v8M ARM ARM and is also in line 101 * with the behaviour documented for the Cortex-M3. 102 */ 103 static bool nvic_rettobase(NVICState *s) 104 { 105 int irq, nhand = 0; 106 bool check_sec = arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY); 107 108 for (irq = ARMV7M_EXCP_RESET; irq < s->num_irq; irq++) { 109 if (s->vectors[irq].active || 110 (check_sec && irq < NVIC_INTERNAL_VECTORS && 111 s->sec_vectors[irq].active)) { 112 nhand++; 113 if (nhand == 2) { 114 return 0; 115 } 116 } 117 } 118 119 return 1; 120 } 121 122 /* Return the value of the ISCR ISRPENDING bit: 123 * 1 if an external interrupt is pending 124 * 0 if no external interrupt is pending 125 */ 126 static bool nvic_isrpending(NVICState *s) 127 { 128 int irq; 129 130 /* 131 * We can shortcut if the highest priority pending interrupt 132 * happens to be external; if not we need to check the whole 133 * vectors[] array. 134 */ 135 if (s->vectpending > NVIC_FIRST_IRQ) { 136 return true; 137 } 138 139 for (irq = NVIC_FIRST_IRQ; irq < s->num_irq; irq++) { 140 if (s->vectors[irq].pending) { 141 return true; 142 } 143 } 144 return false; 145 } 146 147 static bool exc_is_banked(int exc) 148 { 149 /* Return true if this is one of the limited set of exceptions which 150 * are banked (and thus have state in sec_vectors[]) 151 */ 152 return exc == ARMV7M_EXCP_HARD || 153 exc == ARMV7M_EXCP_MEM || 154 exc == ARMV7M_EXCP_USAGE || 155 exc == ARMV7M_EXCP_SVC || 156 exc == ARMV7M_EXCP_PENDSV || 157 exc == ARMV7M_EXCP_SYSTICK; 158 } 159 160 /* Return a mask word which clears the subpriority bits from 161 * a priority value for an M-profile exception, leaving only 162 * the group priority. 163 */ 164 static inline uint32_t nvic_gprio_mask(NVICState *s, bool secure) 165 { 166 return ~0U << (s->prigroup[secure] + 1); 167 } 168 169 static bool exc_targets_secure(NVICState *s, int exc) 170 { 171 /* Return true if this non-banked exception targets Secure state. */ 172 if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) { 173 return false; 174 } 175 176 if (exc >= NVIC_FIRST_IRQ) { 177 return !s->itns[exc]; 178 } 179 180 /* Function shouldn't be called for banked exceptions. */ 181 assert(!exc_is_banked(exc)); 182 183 switch (exc) { 184 case ARMV7M_EXCP_NMI: 185 case ARMV7M_EXCP_BUS: 186 return !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK); 187 case ARMV7M_EXCP_SECURE: 188 return true; 189 case ARMV7M_EXCP_DEBUG: 190 /* TODO: controlled by DEMCR.SDME, which we don't yet implement */ 191 return false; 192 default: 193 /* reset, and reserved (unused) low exception numbers. 194 * We'll get called by code that loops through all the exception 195 * numbers, but it doesn't matter what we return here as these 196 * non-existent exceptions will never be pended or active. 197 */ 198 return true; 199 } 200 } 201 202 static int exc_group_prio(NVICState *s, int rawprio, bool targets_secure) 203 { 204 /* Return the group priority for this exception, given its raw 205 * (group-and-subgroup) priority value and whether it is targeting 206 * secure state or not. 207 */ 208 if (rawprio < 0) { 209 return rawprio; 210 } 211 rawprio &= nvic_gprio_mask(s, targets_secure); 212 /* AIRCR.PRIS causes us to squash all NS priorities into the 213 * lower half of the total range 214 */ 215 if (!targets_secure && 216 (s->cpu->env.v7m.aircr & R_V7M_AIRCR_PRIS_MASK)) { 217 rawprio = (rawprio >> 1) + NVIC_NS_PRIO_LIMIT; 218 } 219 return rawprio; 220 } 221 222 /* Recompute vectpending and exception_prio for a CPU which implements 223 * the Security extension 224 */ 225 static void nvic_recompute_state_secure(NVICState *s) 226 { 227 int i, bank; 228 int pend_prio = NVIC_NOEXC_PRIO; 229 int active_prio = NVIC_NOEXC_PRIO; 230 int pend_irq = 0; 231 bool pending_is_s_banked = false; 232 int pend_subprio = 0; 233 234 /* R_CQRV: precedence is by: 235 * - lowest group priority; if both the same then 236 * - lowest subpriority; if both the same then 237 * - lowest exception number; if both the same (ie banked) then 238 * - secure exception takes precedence 239 * Compare pseudocode RawExecutionPriority. 240 * Annoyingly, now we have two prigroup values (for S and NS) 241 * we can't do the loop comparison on raw priority values. 242 */ 243 for (i = 1; i < s->num_irq; i++) { 244 for (bank = M_REG_S; bank >= M_REG_NS; bank--) { 245 VecInfo *vec; 246 int prio, subprio; 247 bool targets_secure; 248 249 if (bank == M_REG_S) { 250 if (!exc_is_banked(i)) { 251 continue; 252 } 253 vec = &s->sec_vectors[i]; 254 targets_secure = true; 255 } else { 256 vec = &s->vectors[i]; 257 targets_secure = !exc_is_banked(i) && exc_targets_secure(s, i); 258 } 259 260 prio = exc_group_prio(s, vec->prio, targets_secure); 261 subprio = vec->prio & ~nvic_gprio_mask(s, targets_secure); 262 if (vec->enabled && vec->pending && 263 ((prio < pend_prio) || 264 (prio == pend_prio && prio >= 0 && subprio < pend_subprio))) { 265 pend_prio = prio; 266 pend_subprio = subprio; 267 pend_irq = i; 268 pending_is_s_banked = (bank == M_REG_S); 269 } 270 if (vec->active && prio < active_prio) { 271 active_prio = prio; 272 } 273 } 274 } 275 276 s->vectpending_is_s_banked = pending_is_s_banked; 277 s->vectpending = pend_irq; 278 s->vectpending_prio = pend_prio; 279 s->exception_prio = active_prio; 280 281 trace_nvic_recompute_state_secure(s->vectpending, 282 s->vectpending_is_s_banked, 283 s->vectpending_prio, 284 s->exception_prio); 285 } 286 287 /* Recompute vectpending and exception_prio */ 288 static void nvic_recompute_state(NVICState *s) 289 { 290 int i; 291 int pend_prio = NVIC_NOEXC_PRIO; 292 int active_prio = NVIC_NOEXC_PRIO; 293 int pend_irq = 0; 294 295 /* In theory we could write one function that handled both 296 * the "security extension present" and "not present"; however 297 * the security related changes significantly complicate the 298 * recomputation just by themselves and mixing both cases together 299 * would be even worse, so we retain a separate non-secure-only 300 * version for CPUs which don't implement the security extension. 301 */ 302 if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) { 303 nvic_recompute_state_secure(s); 304 return; 305 } 306 307 for (i = 1; i < s->num_irq; i++) { 308 VecInfo *vec = &s->vectors[i]; 309 310 if (vec->enabled && vec->pending && vec->prio < pend_prio) { 311 pend_prio = vec->prio; 312 pend_irq = i; 313 } 314 if (vec->active && vec->prio < active_prio) { 315 active_prio = vec->prio; 316 } 317 } 318 319 if (active_prio > 0) { 320 active_prio &= nvic_gprio_mask(s, false); 321 } 322 323 if (pend_prio > 0) { 324 pend_prio &= nvic_gprio_mask(s, false); 325 } 326 327 s->vectpending = pend_irq; 328 s->vectpending_prio = pend_prio; 329 s->exception_prio = active_prio; 330 331 trace_nvic_recompute_state(s->vectpending, 332 s->vectpending_prio, 333 s->exception_prio); 334 } 335 336 /* Return the current execution priority of the CPU 337 * (equivalent to the pseudocode ExecutionPriority function). 338 * This is a value between -2 (NMI priority) and NVIC_NOEXC_PRIO. 339 */ 340 static inline int nvic_exec_prio(NVICState *s) 341 { 342 CPUARMState *env = &s->cpu->env; 343 int running = NVIC_NOEXC_PRIO; 344 345 if (env->v7m.basepri[M_REG_NS] > 0) { 346 running = exc_group_prio(s, env->v7m.basepri[M_REG_NS], M_REG_NS); 347 } 348 349 if (env->v7m.basepri[M_REG_S] > 0) { 350 int basepri = exc_group_prio(s, env->v7m.basepri[M_REG_S], M_REG_S); 351 if (running > basepri) { 352 running = basepri; 353 } 354 } 355 356 if (env->v7m.primask[M_REG_NS]) { 357 if (env->v7m.aircr & R_V7M_AIRCR_PRIS_MASK) { 358 if (running > NVIC_NS_PRIO_LIMIT) { 359 running = NVIC_NS_PRIO_LIMIT; 360 } 361 } else { 362 running = 0; 363 } 364 } 365 366 if (env->v7m.primask[M_REG_S]) { 367 running = 0; 368 } 369 370 if (env->v7m.faultmask[M_REG_NS]) { 371 if (env->v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) { 372 running = -1; 373 } else { 374 if (env->v7m.aircr & R_V7M_AIRCR_PRIS_MASK) { 375 if (running > NVIC_NS_PRIO_LIMIT) { 376 running = NVIC_NS_PRIO_LIMIT; 377 } 378 } else { 379 running = 0; 380 } 381 } 382 } 383 384 if (env->v7m.faultmask[M_REG_S]) { 385 running = (env->v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) ? -3 : -1; 386 } 387 388 /* consider priority of active handler */ 389 return MIN(running, s->exception_prio); 390 } 391 392 bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) 393 { 394 /* Return true if the requested execution priority is negative 395 * for the specified security state, ie that security state 396 * has an active NMI or HardFault or has set its FAULTMASK. 397 * Note that this is not the same as whether the execution 398 * priority is actually negative (for instance AIRCR.PRIS may 399 * mean we don't allow FAULTMASK_NS to actually make the execution 400 * priority negative). Compare pseudocode IsReqExcPriNeg(). 401 */ 402 if (s->cpu->env.v7m.faultmask[secure]) { 403 return true; 404 } 405 406 if (secure ? s->sec_vectors[ARMV7M_EXCP_HARD].active : 407 s->vectors[ARMV7M_EXCP_HARD].active) { 408 return true; 409 } 410 411 if (s->vectors[ARMV7M_EXCP_NMI].active && 412 exc_targets_secure(s, ARMV7M_EXCP_NMI) == secure) { 413 return true; 414 } 415 416 return false; 417 } 418 419 bool armv7m_nvic_can_take_pending_exception(NVICState *s) 420 { 421 return nvic_exec_prio(s) > nvic_pending_prio(s); 422 } 423 424 int armv7m_nvic_raw_execution_priority(NVICState *s) 425 { 426 return s->exception_prio; 427 } 428 429 /* caller must call nvic_irq_update() after this. 430 * secure indicates the bank to use for banked exceptions (we assert if 431 * we are passed secure=true for a non-banked exception). 432 */ 433 static void set_prio(NVICState *s, unsigned irq, bool secure, uint8_t prio) 434 { 435 assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */ 436 assert(irq < s->num_irq); 437 438 prio &= MAKE_64BIT_MASK(8 - s->num_prio_bits, s->num_prio_bits); 439 440 if (secure) { 441 assert(exc_is_banked(irq)); 442 s->sec_vectors[irq].prio = prio; 443 } else { 444 s->vectors[irq].prio = prio; 445 } 446 447 trace_nvic_set_prio(irq, secure, prio); 448 } 449 450 /* Return the current raw priority register value. 451 * secure indicates the bank to use for banked exceptions (we assert if 452 * we are passed secure=true for a non-banked exception). 453 */ 454 static int get_prio(NVICState *s, unsigned irq, bool secure) 455 { 456 assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */ 457 assert(irq < s->num_irq); 458 459 if (secure) { 460 assert(exc_is_banked(irq)); 461 return s->sec_vectors[irq].prio; 462 } else { 463 return s->vectors[irq].prio; 464 } 465 } 466 467 /* Recompute state and assert irq line accordingly. 468 * Must be called after changes to: 469 * vec->active, vec->enabled, vec->pending or vec->prio for any vector 470 * prigroup 471 */ 472 static void nvic_irq_update(NVICState *s) 473 { 474 int lvl; 475 int pend_prio; 476 477 nvic_recompute_state(s); 478 pend_prio = nvic_pending_prio(s); 479 480 /* Raise NVIC output if this IRQ would be taken, except that we 481 * ignore the effects of the BASEPRI, FAULTMASK and PRIMASK (which 482 * will be checked for in arm_v7m_cpu_exec_interrupt()); changes 483 * to those CPU registers don't cause us to recalculate the NVIC 484 * pending info. 485 */ 486 lvl = (pend_prio < s->exception_prio); 487 trace_nvic_irq_update(s->vectpending, pend_prio, s->exception_prio, lvl); 488 qemu_set_irq(s->excpout, lvl); 489 } 490 491 /** 492 * armv7m_nvic_clear_pending: mark the specified exception as not pending 493 * @opaque: the NVIC 494 * @irq: the exception number to mark as not pending 495 * @secure: false for non-banked exceptions or for the nonsecure 496 * version of a banked exception, true for the secure version of a banked 497 * exception. 498 * 499 * Marks the specified exception as not pending. Note that we will assert() 500 * if @secure is true and @irq does not specify one of the fixed set 501 * of architecturally banked exceptions. 502 */ 503 static void armv7m_nvic_clear_pending(NVICState *s, int irq, bool secure) 504 { 505 VecInfo *vec; 506 507 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); 508 509 if (secure) { 510 assert(exc_is_banked(irq)); 511 vec = &s->sec_vectors[irq]; 512 } else { 513 vec = &s->vectors[irq]; 514 } 515 trace_nvic_clear_pending(irq, secure, vec->enabled, vec->prio); 516 if (vec->pending) { 517 vec->pending = 0; 518 nvic_irq_update(s); 519 } 520 } 521 522 static void do_armv7m_nvic_set_pending(void *opaque, int irq, bool secure, 523 bool derived) 524 { 525 /* Pend an exception, including possibly escalating it to HardFault. 526 * 527 * This function handles both "normal" pending of interrupts and 528 * exceptions, and also derived exceptions (ones which occur as 529 * a result of trying to take some other exception). 530 * 531 * If derived == true, the caller guarantees that we are part way through 532 * trying to take an exception (but have not yet called 533 * armv7m_nvic_acknowledge_irq() to make it active), and so: 534 * - s->vectpending is the "original exception" we were trying to take 535 * - irq is the "derived exception" 536 * - nvic_exec_prio(s) gives the priority before exception entry 537 * Here we handle the prioritization logic which the pseudocode puts 538 * in the DerivedLateArrival() function. 539 */ 540 541 NVICState *s = (NVICState *)opaque; 542 bool banked = exc_is_banked(irq); 543 VecInfo *vec; 544 bool targets_secure; 545 546 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); 547 assert(!secure || banked); 548 549 vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq]; 550 551 targets_secure = banked ? secure : exc_targets_secure(s, irq); 552 553 trace_nvic_set_pending(irq, secure, targets_secure, 554 derived, vec->enabled, vec->prio); 555 556 if (derived) { 557 /* Derived exceptions are always synchronous. */ 558 assert(irq >= ARMV7M_EXCP_HARD && irq < ARMV7M_EXCP_PENDSV); 559 560 if (irq == ARMV7M_EXCP_DEBUG && 561 exc_group_prio(s, vec->prio, secure) >= nvic_exec_prio(s)) { 562 /* DebugMonitorFault, but its priority is lower than the 563 * preempted exception priority: just ignore it. 564 */ 565 return; 566 } 567 568 if (irq == ARMV7M_EXCP_HARD && vec->prio >= s->vectpending_prio) { 569 /* If this is a terminal exception (one which means we cannot 570 * take the original exception, like a failure to read its 571 * vector table entry), then we must take the derived exception. 572 * If the derived exception can't take priority over the 573 * original exception, then we go into Lockup. 574 * 575 * For QEMU, we rely on the fact that a derived exception is 576 * terminal if and only if it's reported to us as HardFault, 577 * which saves having to have an extra argument is_terminal 578 * that we'd only use in one place. 579 */ 580 cpu_abort(&s->cpu->parent_obj, 581 "Lockup: can't take terminal derived exception " 582 "(original exception priority %d)\n", 583 s->vectpending_prio); 584 } 585 /* We now continue with the same code as for a normal pending 586 * exception, which will cause us to pend the derived exception. 587 * We'll then take either the original or the derived exception 588 * based on which is higher priority by the usual mechanism 589 * for selecting the highest priority pending interrupt. 590 */ 591 } 592 593 if (irq >= ARMV7M_EXCP_HARD && irq < ARMV7M_EXCP_PENDSV) { 594 /* If a synchronous exception is pending then it may be 595 * escalated to HardFault if: 596 * * it is equal or lower priority to current execution 597 * * it is disabled 598 * (ie we need to take it immediately but we can't do so). 599 * Asynchronous exceptions (and interrupts) simply remain pending. 600 * 601 * For QEMU, we don't have any imprecise (asynchronous) faults, 602 * so we can assume that PREFETCH_ABORT and DATA_ABORT are always 603 * synchronous. 604 * Debug exceptions are awkward because only Debug exceptions 605 * resulting from the BKPT instruction should be escalated, 606 * but we don't currently implement any Debug exceptions other 607 * than those that result from BKPT, so we treat all debug exceptions 608 * as needing escalation. 609 * 610 * This all means we can identify whether to escalate based only on 611 * the exception number and don't (yet) need the caller to explicitly 612 * tell us whether this exception is synchronous or not. 613 */ 614 int running = nvic_exec_prio(s); 615 bool escalate = false; 616 617 if (exc_group_prio(s, vec->prio, secure) >= running) { 618 trace_nvic_escalate_prio(irq, vec->prio, running); 619 escalate = true; 620 } else if (!vec->enabled) { 621 trace_nvic_escalate_disabled(irq); 622 escalate = true; 623 } 624 625 if (escalate) { 626 627 /* We need to escalate this exception to a synchronous HardFault. 628 * If BFHFNMINS is set then we escalate to the banked HF for 629 * the target security state of the original exception; otherwise 630 * we take a Secure HardFault. 631 */ 632 irq = ARMV7M_EXCP_HARD; 633 if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) && 634 (targets_secure || 635 !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK))) { 636 vec = &s->sec_vectors[irq]; 637 } else { 638 vec = &s->vectors[irq]; 639 } 640 if (running <= vec->prio) { 641 /* We want to escalate to HardFault but we can't take the 642 * synchronous HardFault at this point either. This is a 643 * Lockup condition due to a guest bug. We don't model 644 * Lockup, so report via cpu_abort() instead. 645 */ 646 cpu_abort(&s->cpu->parent_obj, 647 "Lockup: can't escalate %d to HardFault " 648 "(current priority %d)\n", irq, running); 649 } 650 651 /* HF may be banked but there is only one shared HFSR */ 652 s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK; 653 } 654 } 655 656 if (!vec->pending) { 657 vec->pending = 1; 658 nvic_irq_update(s); 659 } 660 } 661 662 void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure) 663 { 664 do_armv7m_nvic_set_pending(s, irq, secure, false); 665 } 666 667 void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure) 668 { 669 do_armv7m_nvic_set_pending(s, irq, secure, true); 670 } 671 672 void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure) 673 { 674 /* 675 * Pend an exception during lazy FP stacking. This differs 676 * from the usual exception pending because the logic for 677 * whether we should escalate depends on the saved context 678 * in the FPCCR register, not on the current state of the CPU/NVIC. 679 */ 680 bool banked = exc_is_banked(irq); 681 VecInfo *vec; 682 bool targets_secure; 683 bool escalate = false; 684 /* 685 * We will only look at bits in fpccr if this is a banked exception 686 * (in which case 'secure' tells us whether it is the S or NS version). 687 * All the bits for the non-banked exceptions are in fpccr_s. 688 */ 689 uint32_t fpccr_s = s->cpu->env.v7m.fpccr[M_REG_S]; 690 uint32_t fpccr = s->cpu->env.v7m.fpccr[secure]; 691 692 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); 693 assert(!secure || banked); 694 695 vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq]; 696 697 targets_secure = banked ? secure : exc_targets_secure(s, irq); 698 699 switch (irq) { 700 case ARMV7M_EXCP_DEBUG: 701 if (!(fpccr_s & R_V7M_FPCCR_MONRDY_MASK)) { 702 /* Ignore DebugMonitor exception */ 703 return; 704 } 705 break; 706 case ARMV7M_EXCP_MEM: 707 escalate = !(fpccr & R_V7M_FPCCR_MMRDY_MASK); 708 break; 709 case ARMV7M_EXCP_USAGE: 710 escalate = !(fpccr & R_V7M_FPCCR_UFRDY_MASK); 711 break; 712 case ARMV7M_EXCP_BUS: 713 escalate = !(fpccr_s & R_V7M_FPCCR_BFRDY_MASK); 714 break; 715 case ARMV7M_EXCP_SECURE: 716 escalate = !(fpccr_s & R_V7M_FPCCR_SFRDY_MASK); 717 break; 718 default: 719 g_assert_not_reached(); 720 } 721 722 if (escalate) { 723 /* 724 * Escalate to HardFault: faults that initially targeted Secure 725 * continue to do so, even if HF normally targets NonSecure. 726 */ 727 irq = ARMV7M_EXCP_HARD; 728 if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) && 729 (targets_secure || 730 !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK))) { 731 vec = &s->sec_vectors[irq]; 732 } else { 733 vec = &s->vectors[irq]; 734 } 735 } 736 737 if (!vec->enabled || 738 nvic_exec_prio(s) <= exc_group_prio(s, vec->prio, secure)) { 739 if (!(fpccr_s & R_V7M_FPCCR_HFRDY_MASK)) { 740 /* 741 * We want to escalate to HardFault but the context the 742 * FP state belongs to prevents the exception pre-empting. 743 */ 744 cpu_abort(&s->cpu->parent_obj, 745 "Lockup: can't escalate to HardFault during " 746 "lazy FP register stacking\n"); 747 } 748 } 749 750 if (escalate) { 751 s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK; 752 } 753 if (!vec->pending) { 754 vec->pending = 1; 755 /* 756 * We do not call nvic_irq_update(), because we know our caller 757 * is going to handle causing us to take the exception by 758 * raising EXCP_LAZYFP, so raising the IRQ line would be 759 * pointless extra work. We just need to recompute the 760 * priorities so that armv7m_nvic_can_take_pending_exception() 761 * returns the right answer. 762 */ 763 nvic_recompute_state(s); 764 } 765 } 766 767 /* Make pending IRQ active. */ 768 void armv7m_nvic_acknowledge_irq(NVICState *s) 769 { 770 CPUARMState *env = &s->cpu->env; 771 const int pending = s->vectpending; 772 const int running = nvic_exec_prio(s); 773 VecInfo *vec; 774 775 assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq); 776 777 if (s->vectpending_is_s_banked) { 778 vec = &s->sec_vectors[pending]; 779 } else { 780 vec = &s->vectors[pending]; 781 } 782 783 assert(vec->enabled); 784 assert(vec->pending); 785 786 assert(s->vectpending_prio < running); 787 788 trace_nvic_acknowledge_irq(pending, s->vectpending_prio); 789 790 vec->active = 1; 791 vec->pending = 0; 792 793 write_v7m_exception(env, s->vectpending); 794 795 nvic_irq_update(s); 796 } 797 798 static bool vectpending_targets_secure(NVICState *s) 799 { 800 /* Return true if s->vectpending targets Secure state */ 801 if (s->vectpending_is_s_banked) { 802 return true; 803 } 804 return !exc_is_banked(s->vectpending) && 805 exc_targets_secure(s, s->vectpending); 806 } 807 808 void armv7m_nvic_get_pending_irq_info(NVICState *s, 809 int *pirq, bool *ptargets_secure) 810 { 811 const int pending = s->vectpending; 812 bool targets_secure; 813 814 assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq); 815 816 targets_secure = vectpending_targets_secure(s); 817 818 trace_nvic_get_pending_irq_info(pending, targets_secure); 819 820 *ptargets_secure = targets_secure; 821 *pirq = pending; 822 } 823 824 int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure) 825 { 826 VecInfo *vec = NULL; 827 int ret = 0; 828 829 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); 830 831 trace_nvic_complete_irq(irq, secure); 832 833 if (secure && exc_is_banked(irq)) { 834 vec = &s->sec_vectors[irq]; 835 } else { 836 vec = &s->vectors[irq]; 837 } 838 839 /* 840 * Identify illegal exception return cases. We can't immediately 841 * return at this point because we still need to deactivate 842 * (either this exception or NMI/HardFault) first. 843 */ 844 if (!exc_is_banked(irq) && exc_targets_secure(s, irq) != secure) { 845 /* 846 * Return from a configurable exception targeting the opposite 847 * security state from the one we're trying to complete it for. 848 * Clear vec because it's not really the VecInfo for this 849 * (irq, secstate) so we mustn't deactivate it. 850 */ 851 ret = -1; 852 vec = NULL; 853 } else if (!vec->active) { 854 /* Return from an inactive interrupt */ 855 ret = -1; 856 } else { 857 /* Legal return, we will return the RETTOBASE bit value to the caller */ 858 ret = nvic_rettobase(s); 859 } 860 861 /* 862 * For negative priorities, v8M will forcibly deactivate the appropriate 863 * NMI or HardFault regardless of what interrupt we're being asked to 864 * deactivate (compare the DeActivate() pseudocode). This is a guard 865 * against software returning from NMI or HardFault with a corrupted 866 * IPSR and leaving the CPU in a negative-priority state. 867 * v7M does not do this, but simply deactivates the requested interrupt. 868 */ 869 if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) { 870 switch (armv7m_nvic_raw_execution_priority(s)) { 871 case -1: 872 if (s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) { 873 vec = &s->vectors[ARMV7M_EXCP_HARD]; 874 } else { 875 vec = &s->sec_vectors[ARMV7M_EXCP_HARD]; 876 } 877 break; 878 case -2: 879 vec = &s->vectors[ARMV7M_EXCP_NMI]; 880 break; 881 case -3: 882 vec = &s->sec_vectors[ARMV7M_EXCP_HARD]; 883 break; 884 default: 885 break; 886 } 887 } 888 889 if (!vec) { 890 return ret; 891 } 892 893 vec->active = 0; 894 if (vec->level) { 895 /* Re-pend the exception if it's still held high; only 896 * happens for extenal IRQs 897 */ 898 assert(irq >= NVIC_FIRST_IRQ); 899 vec->pending = 1; 900 } 901 902 nvic_irq_update(s); 903 904 return ret; 905 } 906 907 bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure) 908 { 909 /* 910 * Return whether an exception is "ready", i.e. it is enabled and is 911 * configured at a priority which would allow it to interrupt the 912 * current execution priority. 913 * 914 * irq and secure have the same semantics as for armv7m_nvic_set_pending(): 915 * for non-banked exceptions secure is always false; for banked exceptions 916 * it indicates which of the exceptions is required. 917 */ 918 bool banked = exc_is_banked(irq); 919 VecInfo *vec; 920 int running = nvic_exec_prio(s); 921 922 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); 923 assert(!secure || banked); 924 925 /* 926 * HardFault is an odd special case: we always check against -1, 927 * even if we're secure and HardFault has priority -3; we never 928 * need to check for enabled state. 929 */ 930 if (irq == ARMV7M_EXCP_HARD) { 931 return running > -1; 932 } 933 934 vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq]; 935 936 return vec->enabled && 937 exc_group_prio(s, vec->prio, secure) < running; 938 } 939 940 /* callback when external interrupt line is changed */ 941 static void set_irq_level(void *opaque, int n, int level) 942 { 943 NVICState *s = opaque; 944 VecInfo *vec; 945 946 n += NVIC_FIRST_IRQ; 947 948 assert(n >= NVIC_FIRST_IRQ && n < s->num_irq); 949 950 trace_nvic_set_irq_level(n, level); 951 952 /* The pending status of an external interrupt is 953 * latched on rising edge and exception handler return. 954 * 955 * Pulsing the IRQ will always run the handler 956 * once, and the handler will re-run until the 957 * level is low when the handler completes. 958 */ 959 vec = &s->vectors[n]; 960 if (level != vec->level) { 961 vec->level = level; 962 if (level) { 963 armv7m_nvic_set_pending(s, n, false); 964 } 965 } 966 } 967 968 /* callback when external NMI line is changed */ 969 static void nvic_nmi_trigger(void *opaque, int n, int level) 970 { 971 NVICState *s = opaque; 972 973 trace_nvic_set_nmi_level(level); 974 975 /* 976 * The architecture doesn't specify whether NMI should share 977 * the normal-interrupt behaviour of being resampled on 978 * exception handler return. We choose not to, so just 979 * set NMI pending here and don't track the current level. 980 */ 981 if (level) { 982 armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false); 983 } 984 } 985 986 static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) 987 { 988 ARMCPU *cpu = s->cpu; 989 uint32_t val; 990 991 switch (offset) { 992 case 4: /* Interrupt Control Type. */ 993 if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) { 994 goto bad_offset; 995 } 996 return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1; 997 case 0xc: /* CPPWR */ 998 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 999 goto bad_offset; 1000 } 1001 /* We make the IMPDEF choice that nothing can ever go into a 1002 * non-retentive power state, which allows us to RAZ/WI this. 1003 */ 1004 return 0; 1005 case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */ 1006 { 1007 int startvec = 8 * (offset - 0x380) + NVIC_FIRST_IRQ; 1008 int i; 1009 1010 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1011 goto bad_offset; 1012 } 1013 if (!attrs.secure) { 1014 return 0; 1015 } 1016 val = 0; 1017 for (i = 0; i < 32 && startvec + i < s->num_irq; i++) { 1018 if (s->itns[startvec + i]) { 1019 val |= (1 << i); 1020 } 1021 } 1022 return val; 1023 } 1024 case 0xcfc: 1025 if (!arm_feature(&cpu->env, ARM_FEATURE_V8_1M)) { 1026 goto bad_offset; 1027 } 1028 return cpu->revidr; 1029 case 0xd00: /* CPUID Base. */ 1030 return cpu->midr; 1031 case 0xd04: /* Interrupt Control State (ICSR) */ 1032 /* VECTACTIVE */ 1033 val = cpu->env.v7m.exception; 1034 /* VECTPENDING */ 1035 if (s->vectpending) { 1036 /* 1037 * From v8.1M VECTPENDING must read as 1 if accessed as 1038 * NonSecure and the highest priority pending and enabled 1039 * exception targets Secure. 1040 */ 1041 int vp = s->vectpending; 1042 if (!attrs.secure && arm_feature(&cpu->env, ARM_FEATURE_V8_1M) && 1043 vectpending_targets_secure(s)) { 1044 vp = 1; 1045 } 1046 val |= (vp & 0x1ff) << 12; 1047 } 1048 /* ISRPENDING - set if any external IRQ is pending */ 1049 if (nvic_isrpending(s)) { 1050 val |= (1 << 22); 1051 } 1052 /* RETTOBASE - set if only one handler is active */ 1053 if (nvic_rettobase(s)) { 1054 val |= (1 << 11); 1055 } 1056 if (attrs.secure) { 1057 /* PENDSTSET */ 1058 if (s->sec_vectors[ARMV7M_EXCP_SYSTICK].pending) { 1059 val |= (1 << 26); 1060 } 1061 /* PENDSVSET */ 1062 if (s->sec_vectors[ARMV7M_EXCP_PENDSV].pending) { 1063 val |= (1 << 28); 1064 } 1065 } else { 1066 /* PENDSTSET */ 1067 if (s->vectors[ARMV7M_EXCP_SYSTICK].pending) { 1068 val |= (1 << 26); 1069 } 1070 /* PENDSVSET */ 1071 if (s->vectors[ARMV7M_EXCP_PENDSV].pending) { 1072 val |= (1 << 28); 1073 } 1074 } 1075 /* NMIPENDSET */ 1076 if ((attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) 1077 && s->vectors[ARMV7M_EXCP_NMI].pending) { 1078 val |= (1 << 31); 1079 } 1080 /* ISRPREEMPT: RES0 when halting debug not implemented */ 1081 /* STTNS: RES0 for the Main Extension */ 1082 return val; 1083 case 0xd08: /* Vector Table Offset. */ 1084 return cpu->env.v7m.vecbase[attrs.secure]; 1085 case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */ 1086 val = 0xfa050000 | (s->prigroup[attrs.secure] << 8); 1087 if (attrs.secure) { 1088 /* s->aircr stores PRIS, BFHFNMINS, SYSRESETREQS */ 1089 val |= cpu->env.v7m.aircr; 1090 } else { 1091 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1092 /* BFHFNMINS is R/O from NS; other bits are RAZ/WI. If 1093 * security isn't supported then BFHFNMINS is RAO (and 1094 * the bit in env.v7m.aircr is always set). 1095 */ 1096 val |= cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK; 1097 } 1098 } 1099 return val; 1100 case 0xd10: /* System Control. */ 1101 if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1102 goto bad_offset; 1103 } 1104 return cpu->env.v7m.scr[attrs.secure]; 1105 case 0xd14: /* Configuration Control. */ 1106 /* 1107 * Non-banked bits: BFHFNMIGN (stored in the NS copy of the register) 1108 * and TRD (stored in the S copy of the register) 1109 */ 1110 val = cpu->env.v7m.ccr[attrs.secure]; 1111 val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK; 1112 /* BFHFNMIGN is RAZ/WI from NS if AIRCR.BFHFNMINS is 0 */ 1113 if (!attrs.secure) { 1114 if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { 1115 val &= ~R_V7M_CCR_BFHFNMIGN_MASK; 1116 } 1117 } 1118 return val; 1119 case 0xd24: /* System Handler Control and State (SHCSR) */ 1120 if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1121 goto bad_offset; 1122 } 1123 val = 0; 1124 if (attrs.secure) { 1125 if (s->sec_vectors[ARMV7M_EXCP_MEM].active) { 1126 val |= (1 << 0); 1127 } 1128 if (s->sec_vectors[ARMV7M_EXCP_HARD].active) { 1129 val |= (1 << 2); 1130 } 1131 if (s->sec_vectors[ARMV7M_EXCP_USAGE].active) { 1132 val |= (1 << 3); 1133 } 1134 if (s->sec_vectors[ARMV7M_EXCP_SVC].active) { 1135 val |= (1 << 7); 1136 } 1137 if (s->sec_vectors[ARMV7M_EXCP_PENDSV].active) { 1138 val |= (1 << 10); 1139 } 1140 if (s->sec_vectors[ARMV7M_EXCP_SYSTICK].active) { 1141 val |= (1 << 11); 1142 } 1143 if (s->sec_vectors[ARMV7M_EXCP_USAGE].pending) { 1144 val |= (1 << 12); 1145 } 1146 if (s->sec_vectors[ARMV7M_EXCP_MEM].pending) { 1147 val |= (1 << 13); 1148 } 1149 if (s->sec_vectors[ARMV7M_EXCP_SVC].pending) { 1150 val |= (1 << 15); 1151 } 1152 if (s->sec_vectors[ARMV7M_EXCP_MEM].enabled) { 1153 val |= (1 << 16); 1154 } 1155 if (s->sec_vectors[ARMV7M_EXCP_USAGE].enabled) { 1156 val |= (1 << 18); 1157 } 1158 if (s->sec_vectors[ARMV7M_EXCP_HARD].pending) { 1159 val |= (1 << 21); 1160 } 1161 /* SecureFault is not banked but is always RAZ/WI to NS */ 1162 if (s->vectors[ARMV7M_EXCP_SECURE].active) { 1163 val |= (1 << 4); 1164 } 1165 if (s->vectors[ARMV7M_EXCP_SECURE].enabled) { 1166 val |= (1 << 19); 1167 } 1168 if (s->vectors[ARMV7M_EXCP_SECURE].pending) { 1169 val |= (1 << 20); 1170 } 1171 } else { 1172 if (s->vectors[ARMV7M_EXCP_MEM].active) { 1173 val |= (1 << 0); 1174 } 1175 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1176 /* HARDFAULTACT, HARDFAULTPENDED not present in v7M */ 1177 if (s->vectors[ARMV7M_EXCP_HARD].active) { 1178 val |= (1 << 2); 1179 } 1180 if (s->vectors[ARMV7M_EXCP_HARD].pending) { 1181 val |= (1 << 21); 1182 } 1183 } 1184 if (s->vectors[ARMV7M_EXCP_USAGE].active) { 1185 val |= (1 << 3); 1186 } 1187 if (s->vectors[ARMV7M_EXCP_SVC].active) { 1188 val |= (1 << 7); 1189 } 1190 if (s->vectors[ARMV7M_EXCP_PENDSV].active) { 1191 val |= (1 << 10); 1192 } 1193 if (s->vectors[ARMV7M_EXCP_SYSTICK].active) { 1194 val |= (1 << 11); 1195 } 1196 if (s->vectors[ARMV7M_EXCP_USAGE].pending) { 1197 val |= (1 << 12); 1198 } 1199 if (s->vectors[ARMV7M_EXCP_MEM].pending) { 1200 val |= (1 << 13); 1201 } 1202 if (s->vectors[ARMV7M_EXCP_SVC].pending) { 1203 val |= (1 << 15); 1204 } 1205 if (s->vectors[ARMV7M_EXCP_MEM].enabled) { 1206 val |= (1 << 16); 1207 } 1208 if (s->vectors[ARMV7M_EXCP_USAGE].enabled) { 1209 val |= (1 << 18); 1210 } 1211 } 1212 if (attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { 1213 if (s->vectors[ARMV7M_EXCP_BUS].active) { 1214 val |= (1 << 1); 1215 } 1216 if (s->vectors[ARMV7M_EXCP_BUS].pending) { 1217 val |= (1 << 14); 1218 } 1219 if (s->vectors[ARMV7M_EXCP_BUS].enabled) { 1220 val |= (1 << 17); 1221 } 1222 if (arm_feature(&cpu->env, ARM_FEATURE_V8) && 1223 s->vectors[ARMV7M_EXCP_NMI].active) { 1224 /* NMIACT is not present in v7M */ 1225 val |= (1 << 5); 1226 } 1227 } 1228 1229 /* TODO: this is RAZ/WI from NS if DEMCR.SDME is set */ 1230 if (s->vectors[ARMV7M_EXCP_DEBUG].active) { 1231 val |= (1 << 8); 1232 } 1233 return val; 1234 case 0xd2c: /* Hard Fault Status. */ 1235 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { 1236 goto bad_offset; 1237 } 1238 return cpu->env.v7m.hfsr; 1239 case 0xd30: /* Debug Fault Status. */ 1240 return cpu->env.v7m.dfsr; 1241 case 0xd34: /* MMFAR MemManage Fault Address */ 1242 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { 1243 goto bad_offset; 1244 } 1245 return cpu->env.v7m.mmfar[attrs.secure]; 1246 case 0xd38: /* Bus Fault Address. */ 1247 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { 1248 goto bad_offset; 1249 } 1250 if (!attrs.secure && 1251 !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { 1252 return 0; 1253 } 1254 return cpu->env.v7m.bfar; 1255 case 0xd3c: /* Aux Fault Status. */ 1256 /* TODO: Implement fault status registers. */ 1257 qemu_log_mask(LOG_UNIMP, 1258 "Aux Fault status registers unimplemented\n"); 1259 return 0; 1260 case 0xd40: /* PFR0. */ 1261 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { 1262 goto bad_offset; 1263 } 1264 return cpu->isar.id_pfr0; 1265 case 0xd44: /* PFR1. */ 1266 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { 1267 goto bad_offset; 1268 } 1269 return cpu->isar.id_pfr1; 1270 case 0xd48: /* DFR0. */ 1271 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { 1272 goto bad_offset; 1273 } 1274 return cpu->isar.id_dfr0; 1275 case 0xd4c: /* AFR0. */ 1276 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { 1277 goto bad_offset; 1278 } 1279 return cpu->id_afr0; 1280 case 0xd50: /* MMFR0. */ 1281 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { 1282 goto bad_offset; 1283 } 1284 return cpu->isar.id_mmfr0; 1285 case 0xd54: /* MMFR1. */ 1286 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { 1287 goto bad_offset; 1288 } 1289 return cpu->isar.id_mmfr1; 1290 case 0xd58: /* MMFR2. */ 1291 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { 1292 goto bad_offset; 1293 } 1294 return cpu->isar.id_mmfr2; 1295 case 0xd5c: /* MMFR3. */ 1296 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { 1297 goto bad_offset; 1298 } 1299 return cpu->isar.id_mmfr3; 1300 case 0xd60: /* ISAR0. */ 1301 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { 1302 goto bad_offset; 1303 } 1304 return cpu->isar.id_isar0; 1305 case 0xd64: /* ISAR1. */ 1306 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { 1307 goto bad_offset; 1308 } 1309 return cpu->isar.id_isar1; 1310 case 0xd68: /* ISAR2. */ 1311 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { 1312 goto bad_offset; 1313 } 1314 return cpu->isar.id_isar2; 1315 case 0xd6c: /* ISAR3. */ 1316 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { 1317 goto bad_offset; 1318 } 1319 return cpu->isar.id_isar3; 1320 case 0xd70: /* ISAR4. */ 1321 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { 1322 goto bad_offset; 1323 } 1324 return cpu->isar.id_isar4; 1325 case 0xd74: /* ISAR5. */ 1326 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { 1327 goto bad_offset; 1328 } 1329 return cpu->isar.id_isar5; 1330 case 0xd78: /* CLIDR */ 1331 return cpu->clidr; 1332 case 0xd7c: /* CTR */ 1333 return cpu->ctr; 1334 case 0xd80: /* CSSIDR */ 1335 { 1336 int idx = cpu->env.v7m.csselr[attrs.secure] & R_V7M_CSSELR_INDEX_MASK; 1337 return cpu->ccsidr[idx]; 1338 } 1339 case 0xd84: /* CSSELR */ 1340 return cpu->env.v7m.csselr[attrs.secure]; 1341 case 0xd88: /* CPACR */ 1342 if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { 1343 return 0; 1344 } 1345 return cpu->env.v7m.cpacr[attrs.secure]; 1346 case 0xd8c: /* NSACR */ 1347 if (!attrs.secure || !cpu_isar_feature(aa32_vfp_simd, cpu)) { 1348 return 0; 1349 } 1350 return cpu->env.v7m.nsacr; 1351 /* TODO: Implement debug registers. */ 1352 case 0xd90: /* MPU_TYPE */ 1353 /* Unified MPU; if the MPU is not present this value is zero */ 1354 return cpu->pmsav7_dregion << 8; 1355 case 0xd94: /* MPU_CTRL */ 1356 return cpu->env.v7m.mpu_ctrl[attrs.secure]; 1357 case 0xd98: /* MPU_RNR */ 1358 return cpu->env.pmsav7.rnr[attrs.secure]; 1359 case 0xd9c: /* MPU_RBAR */ 1360 case 0xda4: /* MPU_RBAR_A1 */ 1361 case 0xdac: /* MPU_RBAR_A2 */ 1362 case 0xdb4: /* MPU_RBAR_A3 */ 1363 { 1364 int region = cpu->env.pmsav7.rnr[attrs.secure]; 1365 1366 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1367 /* PMSAv8M handling of the aliases is different from v7M: 1368 * aliases A1, A2, A3 override the low two bits of the region 1369 * number in MPU_RNR, and there is no 'region' field in the 1370 * RBAR register. 1371 */ 1372 int aliasno = (offset - 0xd9c) / 8; /* 0..3 */ 1373 if (aliasno) { 1374 region = deposit32(region, 0, 2, aliasno); 1375 } 1376 if (region >= cpu->pmsav7_dregion) { 1377 return 0; 1378 } 1379 return cpu->env.pmsav8.rbar[attrs.secure][region]; 1380 } 1381 1382 if (region >= cpu->pmsav7_dregion) { 1383 return 0; 1384 } 1385 return (cpu->env.pmsav7.drbar[region] & ~0x1f) | (region & 0xf); 1386 } 1387 case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */ 1388 case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */ 1389 case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */ 1390 case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */ 1391 { 1392 int region = cpu->env.pmsav7.rnr[attrs.secure]; 1393 1394 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1395 /* PMSAv8M handling of the aliases is different from v7M: 1396 * aliases A1, A2, A3 override the low two bits of the region 1397 * number in MPU_RNR. 1398 */ 1399 int aliasno = (offset - 0xda0) / 8; /* 0..3 */ 1400 if (aliasno) { 1401 region = deposit32(region, 0, 2, aliasno); 1402 } 1403 if (region >= cpu->pmsav7_dregion) { 1404 return 0; 1405 } 1406 return cpu->env.pmsav8.rlar[attrs.secure][region]; 1407 } 1408 1409 if (region >= cpu->pmsav7_dregion) { 1410 return 0; 1411 } 1412 return ((cpu->env.pmsav7.dracr[region] & 0xffff) << 16) | 1413 (cpu->env.pmsav7.drsr[region] & 0xffff); 1414 } 1415 case 0xdc0: /* MPU_MAIR0 */ 1416 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1417 goto bad_offset; 1418 } 1419 return cpu->env.pmsav8.mair0[attrs.secure]; 1420 case 0xdc4: /* MPU_MAIR1 */ 1421 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1422 goto bad_offset; 1423 } 1424 return cpu->env.pmsav8.mair1[attrs.secure]; 1425 case 0xdd0: /* SAU_CTRL */ 1426 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1427 goto bad_offset; 1428 } 1429 if (!attrs.secure) { 1430 return 0; 1431 } 1432 return cpu->env.sau.ctrl; 1433 case 0xdd4: /* SAU_TYPE */ 1434 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1435 goto bad_offset; 1436 } 1437 if (!attrs.secure) { 1438 return 0; 1439 } 1440 return cpu->sau_sregion; 1441 case 0xdd8: /* SAU_RNR */ 1442 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1443 goto bad_offset; 1444 } 1445 if (!attrs.secure) { 1446 return 0; 1447 } 1448 return cpu->env.sau.rnr; 1449 case 0xddc: /* SAU_RBAR */ 1450 { 1451 int region = cpu->env.sau.rnr; 1452 1453 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1454 goto bad_offset; 1455 } 1456 if (!attrs.secure) { 1457 return 0; 1458 } 1459 if (region >= cpu->sau_sregion) { 1460 return 0; 1461 } 1462 return cpu->env.sau.rbar[region]; 1463 } 1464 case 0xde0: /* SAU_RLAR */ 1465 { 1466 int region = cpu->env.sau.rnr; 1467 1468 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1469 goto bad_offset; 1470 } 1471 if (!attrs.secure) { 1472 return 0; 1473 } 1474 if (region >= cpu->sau_sregion) { 1475 return 0; 1476 } 1477 return cpu->env.sau.rlar[region]; 1478 } 1479 case 0xde4: /* SFSR */ 1480 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1481 goto bad_offset; 1482 } 1483 if (!attrs.secure) { 1484 return 0; 1485 } 1486 return cpu->env.v7m.sfsr; 1487 case 0xde8: /* SFAR */ 1488 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1489 goto bad_offset; 1490 } 1491 if (!attrs.secure) { 1492 return 0; 1493 } 1494 return cpu->env.v7m.sfar; 1495 case 0xf04: /* RFSR */ 1496 if (!cpu_isar_feature(aa32_ras, cpu)) { 1497 goto bad_offset; 1498 } 1499 /* We provide minimal-RAS only: RFSR is RAZ/WI */ 1500 return 0; 1501 case 0xf34: /* FPCCR */ 1502 if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { 1503 return 0; 1504 } 1505 if (attrs.secure) { 1506 return cpu->env.v7m.fpccr[M_REG_S]; 1507 } else { 1508 /* 1509 * NS can read LSPEN, CLRONRET and MONRDY. It can read 1510 * BFRDY and HFRDY if AIRCR.BFHFNMINS != 0; 1511 * other non-banked bits RAZ. 1512 * TODO: MONRDY should RAZ/WI if DEMCR.SDME is set. 1513 */ 1514 uint32_t value = cpu->env.v7m.fpccr[M_REG_S]; 1515 uint32_t mask = R_V7M_FPCCR_LSPEN_MASK | 1516 R_V7M_FPCCR_CLRONRET_MASK | 1517 R_V7M_FPCCR_MONRDY_MASK; 1518 1519 if (s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) { 1520 mask |= R_V7M_FPCCR_BFRDY_MASK | R_V7M_FPCCR_HFRDY_MASK; 1521 } 1522 1523 value &= mask; 1524 1525 value |= cpu->env.v7m.fpccr[M_REG_NS]; 1526 return value; 1527 } 1528 case 0xf38: /* FPCAR */ 1529 if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { 1530 return 0; 1531 } 1532 return cpu->env.v7m.fpcar[attrs.secure]; 1533 case 0xf3c: /* FPDSCR */ 1534 if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { 1535 return 0; 1536 } 1537 return cpu->env.v7m.fpdscr[attrs.secure]; 1538 case 0xf40: /* MVFR0 */ 1539 return cpu->isar.mvfr0; 1540 case 0xf44: /* MVFR1 */ 1541 return cpu->isar.mvfr1; 1542 case 0xf48: /* MVFR2 */ 1543 return cpu->isar.mvfr2; 1544 default: 1545 bad_offset: 1546 qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset); 1547 return 0; 1548 } 1549 } 1550 1551 static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, 1552 MemTxAttrs attrs) 1553 { 1554 ARMCPU *cpu = s->cpu; 1555 1556 switch (offset) { 1557 case 0xc: /* CPPWR */ 1558 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1559 goto bad_offset; 1560 } 1561 /* Make the IMPDEF choice to RAZ/WI this. */ 1562 break; 1563 case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */ 1564 { 1565 int startvec = 8 * (offset - 0x380) + NVIC_FIRST_IRQ; 1566 int i; 1567 1568 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1569 goto bad_offset; 1570 } 1571 if (!attrs.secure) { 1572 break; 1573 } 1574 for (i = 0; i < 32 && startvec + i < s->num_irq; i++) { 1575 s->itns[startvec + i] = (value >> i) & 1; 1576 } 1577 nvic_irq_update(s); 1578 break; 1579 } 1580 case 0xd04: /* Interrupt Control State (ICSR) */ 1581 if (attrs.secure || cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) { 1582 if (value & (1 << 31)) { 1583 armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false); 1584 } else if (value & (1 << 30) && 1585 arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1586 /* PENDNMICLR didn't exist in v7M */ 1587 armv7m_nvic_clear_pending(s, ARMV7M_EXCP_NMI, false); 1588 } 1589 } 1590 if (value & (1 << 28)) { 1591 armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure); 1592 } else if (value & (1 << 27)) { 1593 armv7m_nvic_clear_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure); 1594 } 1595 if (value & (1 << 26)) { 1596 armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, attrs.secure); 1597 } else if (value & (1 << 25)) { 1598 armv7m_nvic_clear_pending(s, ARMV7M_EXCP_SYSTICK, attrs.secure); 1599 } 1600 break; 1601 case 0xd08: /* Vector Table Offset. */ 1602 cpu->env.v7m.vecbase[attrs.secure] = value & 0xffffff80; 1603 break; 1604 case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */ 1605 if ((value >> R_V7M_AIRCR_VECTKEY_SHIFT) == 0x05fa) { 1606 if (value & R_V7M_AIRCR_SYSRESETREQ_MASK) { 1607 if (attrs.secure || 1608 !(cpu->env.v7m.aircr & R_V7M_AIRCR_SYSRESETREQS_MASK)) { 1609 signal_sysresetreq(s); 1610 } 1611 } 1612 if (value & R_V7M_AIRCR_VECTCLRACTIVE_MASK) { 1613 qemu_log_mask(LOG_GUEST_ERROR, 1614 "Setting VECTCLRACTIVE when not in DEBUG mode " 1615 "is UNPREDICTABLE\n"); 1616 } 1617 if (value & R_V7M_AIRCR_VECTRESET_MASK) { 1618 /* NB: this bit is RES0 in v8M */ 1619 qemu_log_mask(LOG_GUEST_ERROR, 1620 "Setting VECTRESET when not in DEBUG mode " 1621 "is UNPREDICTABLE\n"); 1622 } 1623 if (arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { 1624 s->prigroup[attrs.secure] = 1625 extract32(value, 1626 R_V7M_AIRCR_PRIGROUP_SHIFT, 1627 R_V7M_AIRCR_PRIGROUP_LENGTH); 1628 } 1629 /* AIRCR.IESB is RAZ/WI because we implement only minimal RAS */ 1630 if (attrs.secure) { 1631 /* These bits are only writable by secure */ 1632 cpu->env.v7m.aircr = value & 1633 (R_V7M_AIRCR_SYSRESETREQS_MASK | 1634 R_V7M_AIRCR_BFHFNMINS_MASK | 1635 R_V7M_AIRCR_PRIS_MASK); 1636 /* BFHFNMINS changes the priority of Secure HardFault, and 1637 * allows a pending Non-secure HardFault to preempt (which 1638 * we implement by marking it enabled). 1639 */ 1640 if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) { 1641 s->sec_vectors[ARMV7M_EXCP_HARD].prio = -3; 1642 s->vectors[ARMV7M_EXCP_HARD].enabled = 1; 1643 } else { 1644 s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1; 1645 s->vectors[ARMV7M_EXCP_HARD].enabled = 0; 1646 } 1647 } 1648 nvic_irq_update(s); 1649 } 1650 break; 1651 case 0xd10: /* System Control. */ 1652 if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1653 goto bad_offset; 1654 } 1655 /* We don't implement deep-sleep so these bits are RAZ/WI. 1656 * The other bits in the register are banked. 1657 * QEMU's implementation ignores SEVONPEND and SLEEPONEXIT, which 1658 * is architecturally permitted. 1659 */ 1660 value &= ~(R_V7M_SCR_SLEEPDEEP_MASK | R_V7M_SCR_SLEEPDEEPS_MASK); 1661 cpu->env.v7m.scr[attrs.secure] = value; 1662 break; 1663 case 0xd14: /* Configuration Control. */ 1664 { 1665 uint32_t mask; 1666 1667 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { 1668 goto bad_offset; 1669 } 1670 1671 /* Enforce RAZ/WI on reserved and must-RAZ/WI bits */ 1672 mask = R_V7M_CCR_STKALIGN_MASK | 1673 R_V7M_CCR_BFHFNMIGN_MASK | 1674 R_V7M_CCR_DIV_0_TRP_MASK | 1675 R_V7M_CCR_UNALIGN_TRP_MASK | 1676 R_V7M_CCR_USERSETMPEND_MASK | 1677 R_V7M_CCR_NONBASETHRDENA_MASK; 1678 if (arm_feature(&cpu->env, ARM_FEATURE_V8_1M) && attrs.secure) { 1679 /* TRD is always RAZ/WI from NS */ 1680 mask |= R_V7M_CCR_TRD_MASK; 1681 } 1682 value &= mask; 1683 1684 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1685 /* v8M makes NONBASETHRDENA and STKALIGN be RES1 */ 1686 value |= R_V7M_CCR_NONBASETHRDENA_MASK 1687 | R_V7M_CCR_STKALIGN_MASK; 1688 } 1689 if (attrs.secure) { 1690 /* the BFHFNMIGN bit is not banked; keep that in the NS copy */ 1691 cpu->env.v7m.ccr[M_REG_NS] = 1692 (cpu->env.v7m.ccr[M_REG_NS] & ~R_V7M_CCR_BFHFNMIGN_MASK) 1693 | (value & R_V7M_CCR_BFHFNMIGN_MASK); 1694 value &= ~R_V7M_CCR_BFHFNMIGN_MASK; 1695 } else { 1696 /* 1697 * BFHFNMIGN is RAZ/WI from NS if AIRCR.BFHFNMINS is 0, so 1698 * preserve the state currently in the NS element of the array 1699 */ 1700 if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { 1701 value &= ~R_V7M_CCR_BFHFNMIGN_MASK; 1702 value |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK; 1703 } 1704 } 1705 1706 cpu->env.v7m.ccr[attrs.secure] = value; 1707 break; 1708 } 1709 case 0xd24: /* System Handler Control and State (SHCSR) */ 1710 if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1711 goto bad_offset; 1712 } 1713 if (attrs.secure) { 1714 s->sec_vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0; 1715 /* Secure HardFault active bit cannot be written */ 1716 s->sec_vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0; 1717 s->sec_vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0; 1718 s->sec_vectors[ARMV7M_EXCP_PENDSV].active = 1719 (value & (1 << 10)) != 0; 1720 s->sec_vectors[ARMV7M_EXCP_SYSTICK].active = 1721 (value & (1 << 11)) != 0; 1722 s->sec_vectors[ARMV7M_EXCP_USAGE].pending = 1723 (value & (1 << 12)) != 0; 1724 s->sec_vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0; 1725 s->sec_vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0; 1726 s->sec_vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0; 1727 s->sec_vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0; 1728 s->sec_vectors[ARMV7M_EXCP_USAGE].enabled = 1729 (value & (1 << 18)) != 0; 1730 s->sec_vectors[ARMV7M_EXCP_HARD].pending = (value & (1 << 21)) != 0; 1731 /* SecureFault not banked, but RAZ/WI to NS */ 1732 s->vectors[ARMV7M_EXCP_SECURE].active = (value & (1 << 4)) != 0; 1733 s->vectors[ARMV7M_EXCP_SECURE].enabled = (value & (1 << 19)) != 0; 1734 s->vectors[ARMV7M_EXCP_SECURE].pending = (value & (1 << 20)) != 0; 1735 } else { 1736 s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0; 1737 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1738 /* HARDFAULTPENDED is not present in v7M */ 1739 s->vectors[ARMV7M_EXCP_HARD].pending = (value & (1 << 21)) != 0; 1740 } 1741 s->vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0; 1742 s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0; 1743 s->vectors[ARMV7M_EXCP_PENDSV].active = (value & (1 << 10)) != 0; 1744 s->vectors[ARMV7M_EXCP_SYSTICK].active = (value & (1 << 11)) != 0; 1745 s->vectors[ARMV7M_EXCP_USAGE].pending = (value & (1 << 12)) != 0; 1746 s->vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0; 1747 s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0; 1748 s->vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0; 1749 s->vectors[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0; 1750 } 1751 if (attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { 1752 s->vectors[ARMV7M_EXCP_BUS].active = (value & (1 << 1)) != 0; 1753 s->vectors[ARMV7M_EXCP_BUS].pending = (value & (1 << 14)) != 0; 1754 s->vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0; 1755 } 1756 /* NMIACT can only be written if the write is of a zero, with 1757 * BFHFNMINS 1, and by the CPU in secure state via the NS alias. 1758 */ 1759 if (!attrs.secure && cpu->env.v7m.secure && 1760 (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) && 1761 (value & (1 << 5)) == 0) { 1762 s->vectors[ARMV7M_EXCP_NMI].active = 0; 1763 } 1764 /* HARDFAULTACT can only be written if the write is of a zero 1765 * to the non-secure HardFault state by the CPU in secure state. 1766 * The only case where we can be targeting the non-secure HF state 1767 * when in secure state is if this is a write via the NS alias 1768 * and BFHFNMINS is 1. 1769 */ 1770 if (!attrs.secure && cpu->env.v7m.secure && 1771 (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) && 1772 (value & (1 << 2)) == 0) { 1773 s->vectors[ARMV7M_EXCP_HARD].active = 0; 1774 } 1775 1776 /* TODO: this is RAZ/WI from NS if DEMCR.SDME is set */ 1777 s->vectors[ARMV7M_EXCP_DEBUG].active = (value & (1 << 8)) != 0; 1778 nvic_irq_update(s); 1779 break; 1780 case 0xd2c: /* Hard Fault Status. */ 1781 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { 1782 goto bad_offset; 1783 } 1784 cpu->env.v7m.hfsr &= ~value; /* W1C */ 1785 break; 1786 case 0xd30: /* Debug Fault Status. */ 1787 cpu->env.v7m.dfsr &= ~value; /* W1C */ 1788 break; 1789 case 0xd34: /* Mem Manage Address. */ 1790 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { 1791 goto bad_offset; 1792 } 1793 cpu->env.v7m.mmfar[attrs.secure] = value; 1794 return; 1795 case 0xd38: /* Bus Fault Address. */ 1796 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { 1797 goto bad_offset; 1798 } 1799 if (!attrs.secure && 1800 !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { 1801 return; 1802 } 1803 cpu->env.v7m.bfar = value; 1804 return; 1805 case 0xd3c: /* Aux Fault Status. */ 1806 qemu_log_mask(LOG_UNIMP, 1807 "NVIC: Aux fault status registers unimplemented\n"); 1808 break; 1809 case 0xd84: /* CSSELR */ 1810 if (!arm_v7m_csselr_razwi(cpu)) { 1811 cpu->env.v7m.csselr[attrs.secure] = value & R_V7M_CSSELR_INDEX_MASK; 1812 } 1813 break; 1814 case 0xd88: /* CPACR */ 1815 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1816 /* We implement only the Floating Point extension's CP10/CP11 */ 1817 cpu->env.v7m.cpacr[attrs.secure] = value & (0xf << 20); 1818 } 1819 break; 1820 case 0xd8c: /* NSACR */ 1821 if (attrs.secure && cpu_isar_feature(aa32_vfp_simd, cpu)) { 1822 /* We implement only the Floating Point extension's CP10/CP11 */ 1823 cpu->env.v7m.nsacr = value & (3 << 10); 1824 } 1825 break; 1826 case 0xd90: /* MPU_TYPE */ 1827 return; /* RO */ 1828 case 0xd94: /* MPU_CTRL */ 1829 if ((value & 1830 (R_V7M_MPU_CTRL_HFNMIENA_MASK | R_V7M_MPU_CTRL_ENABLE_MASK)) 1831 == R_V7M_MPU_CTRL_HFNMIENA_MASK) { 1832 qemu_log_mask(LOG_GUEST_ERROR, "MPU_CTRL: HFNMIENA and !ENABLE is " 1833 "UNPREDICTABLE\n"); 1834 } 1835 cpu->env.v7m.mpu_ctrl[attrs.secure] 1836 = value & (R_V7M_MPU_CTRL_ENABLE_MASK | 1837 R_V7M_MPU_CTRL_HFNMIENA_MASK | 1838 R_V7M_MPU_CTRL_PRIVDEFENA_MASK); 1839 tlb_flush(CPU(cpu)); 1840 break; 1841 case 0xd98: /* MPU_RNR */ 1842 if (value >= cpu->pmsav7_dregion) { 1843 qemu_log_mask(LOG_GUEST_ERROR, "MPU region out of range %" 1844 PRIu32 "/%" PRIu32 "\n", 1845 value, cpu->pmsav7_dregion); 1846 } else { 1847 cpu->env.pmsav7.rnr[attrs.secure] = value; 1848 } 1849 break; 1850 case 0xd9c: /* MPU_RBAR */ 1851 case 0xda4: /* MPU_RBAR_A1 */ 1852 case 0xdac: /* MPU_RBAR_A2 */ 1853 case 0xdb4: /* MPU_RBAR_A3 */ 1854 { 1855 int region; 1856 1857 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1858 /* PMSAv8M handling of the aliases is different from v7M: 1859 * aliases A1, A2, A3 override the low two bits of the region 1860 * number in MPU_RNR, and there is no 'region' field in the 1861 * RBAR register. 1862 */ 1863 int aliasno = (offset - 0xd9c) / 8; /* 0..3 */ 1864 1865 region = cpu->env.pmsav7.rnr[attrs.secure]; 1866 if (aliasno) { 1867 region = deposit32(region, 0, 2, aliasno); 1868 } 1869 if (region >= cpu->pmsav7_dregion) { 1870 return; 1871 } 1872 cpu->env.pmsav8.rbar[attrs.secure][region] = value; 1873 tlb_flush(CPU(cpu)); 1874 return; 1875 } 1876 1877 if (value & (1 << 4)) { 1878 /* VALID bit means use the region number specified in this 1879 * value and also update MPU_RNR.REGION with that value. 1880 */ 1881 region = extract32(value, 0, 4); 1882 if (region >= cpu->pmsav7_dregion) { 1883 qemu_log_mask(LOG_GUEST_ERROR, 1884 "MPU region out of range %u/%" PRIu32 "\n", 1885 region, cpu->pmsav7_dregion); 1886 return; 1887 } 1888 cpu->env.pmsav7.rnr[attrs.secure] = region; 1889 } else { 1890 region = cpu->env.pmsav7.rnr[attrs.secure]; 1891 } 1892 1893 if (region >= cpu->pmsav7_dregion) { 1894 return; 1895 } 1896 1897 cpu->env.pmsav7.drbar[region] = value & ~0x1f; 1898 tlb_flush(CPU(cpu)); 1899 break; 1900 } 1901 case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */ 1902 case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */ 1903 case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */ 1904 case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */ 1905 { 1906 int region = cpu->env.pmsav7.rnr[attrs.secure]; 1907 1908 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1909 /* PMSAv8M handling of the aliases is different from v7M: 1910 * aliases A1, A2, A3 override the low two bits of the region 1911 * number in MPU_RNR. 1912 */ 1913 int aliasno = (offset - 0xd9c) / 8; /* 0..3 */ 1914 1915 region = cpu->env.pmsav7.rnr[attrs.secure]; 1916 if (aliasno) { 1917 region = deposit32(region, 0, 2, aliasno); 1918 } 1919 if (region >= cpu->pmsav7_dregion) { 1920 return; 1921 } 1922 cpu->env.pmsav8.rlar[attrs.secure][region] = value; 1923 tlb_flush(CPU(cpu)); 1924 return; 1925 } 1926 1927 if (region >= cpu->pmsav7_dregion) { 1928 return; 1929 } 1930 1931 cpu->env.pmsav7.drsr[region] = value & 0xff3f; 1932 cpu->env.pmsav7.dracr[region] = (value >> 16) & 0x173f; 1933 tlb_flush(CPU(cpu)); 1934 break; 1935 } 1936 case 0xdc0: /* MPU_MAIR0 */ 1937 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1938 goto bad_offset; 1939 } 1940 if (cpu->pmsav7_dregion) { 1941 /* Register is RES0 if no MPU regions are implemented */ 1942 cpu->env.pmsav8.mair0[attrs.secure] = value; 1943 } 1944 /* We don't need to do anything else because memory attributes 1945 * only affect cacheability, and we don't implement caching. 1946 */ 1947 break; 1948 case 0xdc4: /* MPU_MAIR1 */ 1949 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1950 goto bad_offset; 1951 } 1952 if (cpu->pmsav7_dregion) { 1953 /* Register is RES0 if no MPU regions are implemented */ 1954 cpu->env.pmsav8.mair1[attrs.secure] = value; 1955 } 1956 /* We don't need to do anything else because memory attributes 1957 * only affect cacheability, and we don't implement caching. 1958 */ 1959 break; 1960 case 0xdd0: /* SAU_CTRL */ 1961 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1962 goto bad_offset; 1963 } 1964 if (!attrs.secure) { 1965 return; 1966 } 1967 cpu->env.sau.ctrl = value & 3; 1968 break; 1969 case 0xdd4: /* SAU_TYPE */ 1970 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1971 goto bad_offset; 1972 } 1973 break; 1974 case 0xdd8: /* SAU_RNR */ 1975 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1976 goto bad_offset; 1977 } 1978 if (!attrs.secure) { 1979 return; 1980 } 1981 if (value >= cpu->sau_sregion) { 1982 qemu_log_mask(LOG_GUEST_ERROR, "SAU region out of range %" 1983 PRIu32 "/%" PRIu32 "\n", 1984 value, cpu->sau_sregion); 1985 } else { 1986 cpu->env.sau.rnr = value; 1987 } 1988 break; 1989 case 0xddc: /* SAU_RBAR */ 1990 { 1991 int region = cpu->env.sau.rnr; 1992 1993 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1994 goto bad_offset; 1995 } 1996 if (!attrs.secure) { 1997 return; 1998 } 1999 if (region >= cpu->sau_sregion) { 2000 return; 2001 } 2002 cpu->env.sau.rbar[region] = value & ~0x1f; 2003 tlb_flush(CPU(cpu)); 2004 break; 2005 } 2006 case 0xde0: /* SAU_RLAR */ 2007 { 2008 int region = cpu->env.sau.rnr; 2009 2010 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 2011 goto bad_offset; 2012 } 2013 if (!attrs.secure) { 2014 return; 2015 } 2016 if (region >= cpu->sau_sregion) { 2017 return; 2018 } 2019 cpu->env.sau.rlar[region] = value & ~0x1c; 2020 tlb_flush(CPU(cpu)); 2021 break; 2022 } 2023 case 0xde4: /* SFSR */ 2024 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 2025 goto bad_offset; 2026 } 2027 if (!attrs.secure) { 2028 return; 2029 } 2030 cpu->env.v7m.sfsr &= ~value; /* W1C */ 2031 break; 2032 case 0xde8: /* SFAR */ 2033 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 2034 goto bad_offset; 2035 } 2036 if (!attrs.secure) { 2037 return; 2038 } 2039 cpu->env.v7m.sfsr = value; 2040 break; 2041 case 0xf00: /* Software Triggered Interrupt Register */ 2042 { 2043 int excnum = (value & 0x1ff) + NVIC_FIRST_IRQ; 2044 2045 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { 2046 goto bad_offset; 2047 } 2048 2049 if (excnum < s->num_irq) { 2050 armv7m_nvic_set_pending(s, excnum, false); 2051 } 2052 break; 2053 } 2054 case 0xf04: /* RFSR */ 2055 if (!cpu_isar_feature(aa32_ras, cpu)) { 2056 goto bad_offset; 2057 } 2058 /* We provide minimal-RAS only: RFSR is RAZ/WI */ 2059 break; 2060 case 0xf34: /* FPCCR */ 2061 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 2062 /* Not all bits here are banked. */ 2063 uint32_t fpccr_s; 2064 2065 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 2066 /* Don't allow setting of bits not present in v7M */ 2067 value &= (R_V7M_FPCCR_LSPACT_MASK | 2068 R_V7M_FPCCR_USER_MASK | 2069 R_V7M_FPCCR_THREAD_MASK | 2070 R_V7M_FPCCR_HFRDY_MASK | 2071 R_V7M_FPCCR_MMRDY_MASK | 2072 R_V7M_FPCCR_BFRDY_MASK | 2073 R_V7M_FPCCR_MONRDY_MASK | 2074 R_V7M_FPCCR_LSPEN_MASK | 2075 R_V7M_FPCCR_ASPEN_MASK); 2076 } 2077 value &= ~R_V7M_FPCCR_RES0_MASK; 2078 2079 if (!attrs.secure) { 2080 /* Some non-banked bits are configurably writable by NS */ 2081 fpccr_s = cpu->env.v7m.fpccr[M_REG_S]; 2082 if (!(fpccr_s & R_V7M_FPCCR_LSPENS_MASK)) { 2083 uint32_t lspen = FIELD_EX32(value, V7M_FPCCR, LSPEN); 2084 fpccr_s = FIELD_DP32(fpccr_s, V7M_FPCCR, LSPEN, lspen); 2085 } 2086 if (!(fpccr_s & R_V7M_FPCCR_CLRONRETS_MASK)) { 2087 uint32_t cor = FIELD_EX32(value, V7M_FPCCR, CLRONRET); 2088 fpccr_s = FIELD_DP32(fpccr_s, V7M_FPCCR, CLRONRET, cor); 2089 } 2090 if ((s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { 2091 uint32_t hfrdy = FIELD_EX32(value, V7M_FPCCR, HFRDY); 2092 uint32_t bfrdy = FIELD_EX32(value, V7M_FPCCR, BFRDY); 2093 fpccr_s = FIELD_DP32(fpccr_s, V7M_FPCCR, HFRDY, hfrdy); 2094 fpccr_s = FIELD_DP32(fpccr_s, V7M_FPCCR, BFRDY, bfrdy); 2095 } 2096 /* TODO MONRDY should RAZ/WI if DEMCR.SDME is set */ 2097 { 2098 uint32_t monrdy = FIELD_EX32(value, V7M_FPCCR, MONRDY); 2099 fpccr_s = FIELD_DP32(fpccr_s, V7M_FPCCR, MONRDY, monrdy); 2100 } 2101 2102 /* 2103 * All other non-banked bits are RAZ/WI from NS; write 2104 * just the banked bits to fpccr[M_REG_NS]. 2105 */ 2106 value &= R_V7M_FPCCR_BANKED_MASK; 2107 cpu->env.v7m.fpccr[M_REG_NS] = value; 2108 } else { 2109 fpccr_s = value; 2110 } 2111 cpu->env.v7m.fpccr[M_REG_S] = fpccr_s; 2112 } 2113 break; 2114 case 0xf38: /* FPCAR */ 2115 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 2116 value &= ~7; 2117 cpu->env.v7m.fpcar[attrs.secure] = value; 2118 } 2119 break; 2120 case 0xf3c: /* FPDSCR */ 2121 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 2122 uint32_t mask = FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE_MASK; 2123 if (cpu_isar_feature(any_fp16, cpu)) { 2124 mask |= FPCR_FZ16; 2125 } 2126 value &= mask; 2127 if (cpu_isar_feature(aa32_lob, cpu)) { 2128 value |= 4 << FPCR_LTPSIZE_SHIFT; 2129 } 2130 cpu->env.v7m.fpdscr[attrs.secure] = value; 2131 } 2132 break; 2133 case 0xf50: /* ICIALLU */ 2134 case 0xf58: /* ICIMVAU */ 2135 case 0xf5c: /* DCIMVAC */ 2136 case 0xf60: /* DCISW */ 2137 case 0xf64: /* DCCMVAU */ 2138 case 0xf68: /* DCCMVAC */ 2139 case 0xf6c: /* DCCSW */ 2140 case 0xf70: /* DCCIMVAC */ 2141 case 0xf74: /* DCCISW */ 2142 case 0xf78: /* BPIALL */ 2143 /* Cache and branch predictor maintenance: for QEMU these always NOP */ 2144 break; 2145 default: 2146 bad_offset: 2147 qemu_log_mask(LOG_GUEST_ERROR, 2148 "NVIC: Bad write offset 0x%x\n", offset); 2149 } 2150 } 2151 2152 static bool nvic_user_access_ok(NVICState *s, hwaddr offset, MemTxAttrs attrs) 2153 { 2154 /* Return true if unprivileged access to this register is permitted. */ 2155 switch (offset) { 2156 case 0xf00: /* STIR: accessible only if CCR.USERSETMPEND permits */ 2157 /* For access via STIR_NS it is the NS CCR.USERSETMPEND that 2158 * controls access even though the CPU is in Secure state (I_QDKX). 2159 */ 2160 return s->cpu->env.v7m.ccr[attrs.secure] & R_V7M_CCR_USERSETMPEND_MASK; 2161 default: 2162 /* All other user accesses cause a BusFault unconditionally */ 2163 return false; 2164 } 2165 } 2166 2167 static int shpr_bank(NVICState *s, int exc, MemTxAttrs attrs) 2168 { 2169 /* Behaviour for the SHPR register field for this exception: 2170 * return M_REG_NS to use the nonsecure vector (including for 2171 * non-banked exceptions), M_REG_S for the secure version of 2172 * a banked exception, and -1 if this field should RAZ/WI. 2173 */ 2174 switch (exc) { 2175 case ARMV7M_EXCP_MEM: 2176 case ARMV7M_EXCP_USAGE: 2177 case ARMV7M_EXCP_SVC: 2178 case ARMV7M_EXCP_PENDSV: 2179 case ARMV7M_EXCP_SYSTICK: 2180 /* Banked exceptions */ 2181 return attrs.secure; 2182 case ARMV7M_EXCP_BUS: 2183 /* Not banked, RAZ/WI from nonsecure if BFHFNMINS is zero */ 2184 if (!attrs.secure && 2185 !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { 2186 return -1; 2187 } 2188 return M_REG_NS; 2189 case ARMV7M_EXCP_SECURE: 2190 /* Not banked, RAZ/WI from nonsecure */ 2191 if (!attrs.secure) { 2192 return -1; 2193 } 2194 return M_REG_NS; 2195 case ARMV7M_EXCP_DEBUG: 2196 /* Not banked. TODO should RAZ/WI if DEMCR.SDME is set */ 2197 return M_REG_NS; 2198 case 8 ... 10: 2199 case 13: 2200 /* RES0 */ 2201 return -1; 2202 default: 2203 /* Not reachable due to decode of SHPR register addresses */ 2204 g_assert_not_reached(); 2205 } 2206 } 2207 2208 static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, 2209 uint64_t *data, unsigned size, 2210 MemTxAttrs attrs) 2211 { 2212 NVICState *s = (NVICState *)opaque; 2213 uint32_t offset = addr; 2214 unsigned i, startvec, end; 2215 uint32_t val; 2216 2217 if (attrs.user && !nvic_user_access_ok(s, addr, attrs)) { 2218 /* Generate BusFault for unprivileged accesses */ 2219 return MEMTX_ERROR; 2220 } 2221 2222 switch (offset) { 2223 /* reads of set and clear both return the status */ 2224 case 0x100 ... 0x13f: /* NVIC Set enable */ 2225 offset += 0x80; 2226 /* fall through */ 2227 case 0x180 ... 0x1bf: /* NVIC Clear enable */ 2228 val = 0; 2229 startvec = 8 * (offset - 0x180) + NVIC_FIRST_IRQ; /* vector # */ 2230 2231 for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { 2232 if (s->vectors[startvec + i].enabled && 2233 (attrs.secure || s->itns[startvec + i])) { 2234 val |= (1 << i); 2235 } 2236 } 2237 break; 2238 case 0x200 ... 0x23f: /* NVIC Set pend */ 2239 offset += 0x80; 2240 /* fall through */ 2241 case 0x280 ... 0x2bf: /* NVIC Clear pend */ 2242 val = 0; 2243 startvec = 8 * (offset - 0x280) + NVIC_FIRST_IRQ; /* vector # */ 2244 for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { 2245 if (s->vectors[startvec + i].pending && 2246 (attrs.secure || s->itns[startvec + i])) { 2247 val |= (1 << i); 2248 } 2249 } 2250 break; 2251 case 0x300 ... 0x33f: /* NVIC Active */ 2252 val = 0; 2253 2254 if (!arm_feature(&s->cpu->env, ARM_FEATURE_V7)) { 2255 break; 2256 } 2257 2258 startvec = 8 * (offset - 0x300) + NVIC_FIRST_IRQ; /* vector # */ 2259 2260 for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { 2261 if (s->vectors[startvec + i].active && 2262 (attrs.secure || s->itns[startvec + i])) { 2263 val |= (1 << i); 2264 } 2265 } 2266 break; 2267 case 0x400 ... 0x5ef: /* NVIC Priority */ 2268 val = 0; 2269 startvec = offset - 0x400 + NVIC_FIRST_IRQ; /* vector # */ 2270 2271 for (i = 0; i < size && startvec + i < s->num_irq; i++) { 2272 if (attrs.secure || s->itns[startvec + i]) { 2273 val |= s->vectors[startvec + i].prio << (8 * i); 2274 } 2275 } 2276 break; 2277 case 0xd18 ... 0xd1b: /* System Handler Priority (SHPR1) */ 2278 if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) { 2279 val = 0; 2280 break; 2281 } 2282 /* fall through */ 2283 case 0xd1c ... 0xd23: /* System Handler Priority (SHPR2, SHPR3) */ 2284 val = 0; 2285 for (i = 0; i < size; i++) { 2286 unsigned hdlidx = (offset - 0xd14) + i; 2287 int sbank = shpr_bank(s, hdlidx, attrs); 2288 2289 if (sbank < 0) { 2290 continue; 2291 } 2292 val = deposit32(val, i * 8, 8, get_prio(s, hdlidx, sbank)); 2293 } 2294 break; 2295 case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */ 2296 if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) { 2297 val = 0; 2298 break; 2299 }; 2300 /* 2301 * The BFSR bits [15:8] are shared between security states 2302 * and we store them in the NS copy. They are RAZ/WI for 2303 * NS code if AIRCR.BFHFNMINS is 0. 2304 */ 2305 val = s->cpu->env.v7m.cfsr[attrs.secure]; 2306 if (!attrs.secure && 2307 !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { 2308 val &= ~R_V7M_CFSR_BFSR_MASK; 2309 } else { 2310 val |= s->cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK; 2311 } 2312 val = extract32(val, (offset - 0xd28) * 8, size * 8); 2313 break; 2314 case 0xfe0 ... 0xfff: /* ID. */ 2315 if (offset & 3) { 2316 val = 0; 2317 } else { 2318 val = nvic_id[(offset - 0xfe0) >> 2]; 2319 } 2320 break; 2321 default: 2322 if (size == 4) { 2323 val = nvic_readl(s, offset, attrs); 2324 } else { 2325 qemu_log_mask(LOG_GUEST_ERROR, 2326 "NVIC: Bad read of size %d at offset 0x%x\n", 2327 size, offset); 2328 val = 0; 2329 } 2330 } 2331 2332 trace_nvic_sysreg_read(addr, val, size); 2333 *data = val; 2334 return MEMTX_OK; 2335 } 2336 2337 static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, 2338 uint64_t value, unsigned size, 2339 MemTxAttrs attrs) 2340 { 2341 NVICState *s = (NVICState *)opaque; 2342 uint32_t offset = addr; 2343 unsigned i, startvec, end; 2344 unsigned setval = 0; 2345 2346 trace_nvic_sysreg_write(addr, value, size); 2347 2348 if (attrs.user && !nvic_user_access_ok(s, addr, attrs)) { 2349 /* Generate BusFault for unprivileged accesses */ 2350 return MEMTX_ERROR; 2351 } 2352 2353 switch (offset) { 2354 case 0x100 ... 0x13f: /* NVIC Set enable */ 2355 offset += 0x80; 2356 setval = 1; 2357 /* fall through */ 2358 case 0x180 ... 0x1bf: /* NVIC Clear enable */ 2359 startvec = 8 * (offset - 0x180) + NVIC_FIRST_IRQ; 2360 2361 for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { 2362 if (value & (1 << i) && 2363 (attrs.secure || s->itns[startvec + i])) { 2364 s->vectors[startvec + i].enabled = setval; 2365 } 2366 } 2367 nvic_irq_update(s); 2368 goto exit_ok; 2369 case 0x200 ... 0x23f: /* NVIC Set pend */ 2370 /* the special logic in armv7m_nvic_set_pending() 2371 * is not needed since IRQs are never escalated 2372 */ 2373 offset += 0x80; 2374 setval = 1; 2375 /* fall through */ 2376 case 0x280 ... 0x2bf: /* NVIC Clear pend */ 2377 startvec = 8 * (offset - 0x280) + NVIC_FIRST_IRQ; /* vector # */ 2378 2379 for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { 2380 /* 2381 * Note that if the input line is still held high and the interrupt 2382 * is not active then rule R_CVJS requires that the Pending state 2383 * remains set; in that case we mustn't let it be cleared. 2384 */ 2385 if (value & (1 << i) && 2386 (attrs.secure || s->itns[startvec + i]) && 2387 !(setval == 0 && s->vectors[startvec + i].level && 2388 !s->vectors[startvec + i].active)) { 2389 s->vectors[startvec + i].pending = setval; 2390 } 2391 } 2392 nvic_irq_update(s); 2393 goto exit_ok; 2394 case 0x300 ... 0x33f: /* NVIC Active */ 2395 goto exit_ok; /* R/O */ 2396 case 0x400 ... 0x5ef: /* NVIC Priority */ 2397 startvec = (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */ 2398 2399 for (i = 0; i < size && startvec + i < s->num_irq; i++) { 2400 if (attrs.secure || s->itns[startvec + i]) { 2401 set_prio(s, startvec + i, false, (value >> (i * 8)) & 0xff); 2402 } 2403 } 2404 nvic_irq_update(s); 2405 goto exit_ok; 2406 case 0xd18 ... 0xd1b: /* System Handler Priority (SHPR1) */ 2407 if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) { 2408 goto exit_ok; 2409 } 2410 /* fall through */ 2411 case 0xd1c ... 0xd23: /* System Handler Priority (SHPR2, SHPR3) */ 2412 for (i = 0; i < size; i++) { 2413 unsigned hdlidx = (offset - 0xd14) + i; 2414 int newprio = extract32(value, i * 8, 8); 2415 int sbank = shpr_bank(s, hdlidx, attrs); 2416 2417 if (sbank < 0) { 2418 continue; 2419 } 2420 set_prio(s, hdlidx, sbank, newprio); 2421 } 2422 nvic_irq_update(s); 2423 goto exit_ok; 2424 case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */ 2425 if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) { 2426 goto exit_ok; 2427 } 2428 /* All bits are W1C, so construct 32 bit value with 0s in 2429 * the parts not written by the access size 2430 */ 2431 value <<= ((offset - 0xd28) * 8); 2432 2433 if (!attrs.secure && 2434 !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { 2435 /* BFSR bits are RAZ/WI for NS if BFHFNMINS is set */ 2436 value &= ~R_V7M_CFSR_BFSR_MASK; 2437 } 2438 2439 s->cpu->env.v7m.cfsr[attrs.secure] &= ~value; 2440 if (attrs.secure) { 2441 /* The BFSR bits [15:8] are shared between security states 2442 * and we store them in the NS copy. 2443 */ 2444 s->cpu->env.v7m.cfsr[M_REG_NS] &= ~(value & R_V7M_CFSR_BFSR_MASK); 2445 } 2446 goto exit_ok; 2447 } 2448 if (size == 4) { 2449 nvic_writel(s, offset, value, attrs); 2450 goto exit_ok; 2451 } 2452 qemu_log_mask(LOG_GUEST_ERROR, 2453 "NVIC: Bad write of size %d at offset 0x%x\n", size, offset); 2454 /* This is UNPREDICTABLE; treat as RAZ/WI */ 2455 2456 exit_ok: 2457 /* Ensure any changes made are reflected in the cached hflags. */ 2458 arm_rebuild_hflags(&s->cpu->env); 2459 return MEMTX_OK; 2460 } 2461 2462 static const MemoryRegionOps nvic_sysreg_ops = { 2463 .read_with_attrs = nvic_sysreg_read, 2464 .write_with_attrs = nvic_sysreg_write, 2465 .endianness = DEVICE_NATIVE_ENDIAN, 2466 }; 2467 2468 static int nvic_post_load(void *opaque, int version_id) 2469 { 2470 NVICState *s = opaque; 2471 unsigned i; 2472 int resetprio; 2473 2474 /* Check for out of range priority settings */ 2475 resetprio = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? -4 : -3; 2476 2477 if (s->vectors[ARMV7M_EXCP_RESET].prio != resetprio || 2478 s->vectors[ARMV7M_EXCP_NMI].prio != -2 || 2479 s->vectors[ARMV7M_EXCP_HARD].prio != -1) { 2480 return 1; 2481 } 2482 for (i = ARMV7M_EXCP_MEM; i < s->num_irq; i++) { 2483 if (s->vectors[i].prio & ~0xff) { 2484 return 1; 2485 } 2486 } 2487 2488 nvic_recompute_state(s); 2489 2490 return 0; 2491 } 2492 2493 static const VMStateDescription vmstate_VecInfo = { 2494 .name = "armv7m_nvic_info", 2495 .version_id = 1, 2496 .minimum_version_id = 1, 2497 .fields = (VMStateField[]) { 2498 VMSTATE_INT16(prio, VecInfo), 2499 VMSTATE_UINT8(enabled, VecInfo), 2500 VMSTATE_UINT8(pending, VecInfo), 2501 VMSTATE_UINT8(active, VecInfo), 2502 VMSTATE_UINT8(level, VecInfo), 2503 VMSTATE_END_OF_LIST() 2504 } 2505 }; 2506 2507 static bool nvic_security_needed(void *opaque) 2508 { 2509 NVICState *s = opaque; 2510 2511 return arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY); 2512 } 2513 2514 static int nvic_security_post_load(void *opaque, int version_id) 2515 { 2516 NVICState *s = opaque; 2517 int i; 2518 2519 /* Check for out of range priority settings */ 2520 if (s->sec_vectors[ARMV7M_EXCP_HARD].prio != -1 2521 && s->sec_vectors[ARMV7M_EXCP_HARD].prio != -3) { 2522 /* We can't cross-check against AIRCR.BFHFNMINS as we don't know 2523 * if the CPU state has been migrated yet; a mismatch won't 2524 * cause the emulation to blow up, though. 2525 */ 2526 return 1; 2527 } 2528 for (i = ARMV7M_EXCP_MEM; i < ARRAY_SIZE(s->sec_vectors); i++) { 2529 if (s->sec_vectors[i].prio & ~0xff) { 2530 return 1; 2531 } 2532 } 2533 return 0; 2534 } 2535 2536 static const VMStateDescription vmstate_nvic_security = { 2537 .name = "armv7m_nvic/m-security", 2538 .version_id = 1, 2539 .minimum_version_id = 1, 2540 .needed = nvic_security_needed, 2541 .post_load = &nvic_security_post_load, 2542 .fields = (VMStateField[]) { 2543 VMSTATE_STRUCT_ARRAY(sec_vectors, NVICState, NVIC_INTERNAL_VECTORS, 1, 2544 vmstate_VecInfo, VecInfo), 2545 VMSTATE_UINT32(prigroup[M_REG_S], NVICState), 2546 VMSTATE_BOOL_ARRAY(itns, NVICState, NVIC_MAX_VECTORS), 2547 VMSTATE_END_OF_LIST() 2548 } 2549 }; 2550 2551 static const VMStateDescription vmstate_nvic = { 2552 .name = "armv7m_nvic", 2553 .version_id = 4, 2554 .minimum_version_id = 4, 2555 .post_load = &nvic_post_load, 2556 .fields = (VMStateField[]) { 2557 VMSTATE_STRUCT_ARRAY(vectors, NVICState, NVIC_MAX_VECTORS, 1, 2558 vmstate_VecInfo, VecInfo), 2559 VMSTATE_UINT32(prigroup[M_REG_NS], NVICState), 2560 VMSTATE_END_OF_LIST() 2561 }, 2562 .subsections = (const VMStateDescription*[]) { 2563 &vmstate_nvic_security, 2564 NULL 2565 } 2566 }; 2567 2568 static Property props_nvic[] = { 2569 /* Number of external IRQ lines (so excluding the 16 internal exceptions) */ 2570 DEFINE_PROP_UINT32("num-irq", NVICState, num_irq, 64), 2571 DEFINE_PROP_END_OF_LIST() 2572 }; 2573 2574 static void armv7m_nvic_reset(DeviceState *dev) 2575 { 2576 int resetprio; 2577 NVICState *s = NVIC(dev); 2578 2579 memset(s->vectors, 0, sizeof(s->vectors)); 2580 memset(s->sec_vectors, 0, sizeof(s->sec_vectors)); 2581 s->prigroup[M_REG_NS] = 0; 2582 s->prigroup[M_REG_S] = 0; 2583 2584 s->vectors[ARMV7M_EXCP_NMI].enabled = 1; 2585 /* MEM, BUS, and USAGE are enabled through 2586 * the System Handler Control register 2587 */ 2588 s->vectors[ARMV7M_EXCP_SVC].enabled = 1; 2589 s->vectors[ARMV7M_EXCP_PENDSV].enabled = 1; 2590 s->vectors[ARMV7M_EXCP_SYSTICK].enabled = 1; 2591 2592 /* DebugMonitor is enabled via DEMCR.MON_EN */ 2593 s->vectors[ARMV7M_EXCP_DEBUG].enabled = 0; 2594 2595 resetprio = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? -4 : -3; 2596 s->vectors[ARMV7M_EXCP_RESET].prio = resetprio; 2597 s->vectors[ARMV7M_EXCP_NMI].prio = -2; 2598 s->vectors[ARMV7M_EXCP_HARD].prio = -1; 2599 2600 if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) { 2601 s->sec_vectors[ARMV7M_EXCP_HARD].enabled = 1; 2602 s->sec_vectors[ARMV7M_EXCP_SVC].enabled = 1; 2603 s->sec_vectors[ARMV7M_EXCP_PENDSV].enabled = 1; 2604 s->sec_vectors[ARMV7M_EXCP_SYSTICK].enabled = 1; 2605 2606 /* AIRCR.BFHFNMINS resets to 0 so Secure HF is priority -1 (R_CMTC) */ 2607 s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1; 2608 /* If AIRCR.BFHFNMINS is 0 then NS HF is (effectively) disabled */ 2609 s->vectors[ARMV7M_EXCP_HARD].enabled = 0; 2610 } else { 2611 s->vectors[ARMV7M_EXCP_HARD].enabled = 1; 2612 } 2613 2614 /* Strictly speaking the reset handler should be enabled. 2615 * However, we don't simulate soft resets through the NVIC, 2616 * and the reset vector should never be pended. 2617 * So we leave it disabled to catch logic errors. 2618 */ 2619 2620 s->exception_prio = NVIC_NOEXC_PRIO; 2621 s->vectpending = 0; 2622 s->vectpending_is_s_banked = false; 2623 s->vectpending_prio = NVIC_NOEXC_PRIO; 2624 2625 if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) { 2626 memset(s->itns, 0, sizeof(s->itns)); 2627 } else { 2628 /* This state is constant and not guest accessible in a non-security 2629 * NVIC; we set the bits to true to avoid having to do a feature 2630 * bit check in the NVIC enable/pend/etc register accessors. 2631 */ 2632 int i; 2633 2634 for (i = NVIC_FIRST_IRQ; i < ARRAY_SIZE(s->itns); i++) { 2635 s->itns[i] = true; 2636 } 2637 } 2638 2639 /* 2640 * We updated state that affects the CPU's MMUidx and thus its hflags; 2641 * and we can't guarantee that we run before the CPU reset function. 2642 */ 2643 arm_rebuild_hflags(&s->cpu->env); 2644 } 2645 2646 static void nvic_systick_trigger(void *opaque, int n, int level) 2647 { 2648 NVICState *s = opaque; 2649 2650 if (level) { 2651 /* SysTick just asked us to pend its exception. 2652 * (This is different from an external interrupt line's 2653 * behaviour.) 2654 * n == 0 : NonSecure systick 2655 * n == 1 : Secure systick 2656 */ 2657 armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, n); 2658 } 2659 } 2660 2661 static void armv7m_nvic_realize(DeviceState *dev, Error **errp) 2662 { 2663 NVICState *s = NVIC(dev); 2664 2665 /* The armv7m container object will have set our CPU pointer */ 2666 if (!s->cpu || !arm_feature(&s->cpu->env, ARM_FEATURE_M)) { 2667 error_setg(errp, "The NVIC can only be used with a Cortex-M CPU"); 2668 return; 2669 } 2670 2671 if (s->num_irq > NVIC_MAX_IRQ) { 2672 error_setg(errp, "num-irq %d exceeds NVIC maximum", s->num_irq); 2673 return; 2674 } 2675 2676 qdev_init_gpio_in(dev, set_irq_level, s->num_irq); 2677 2678 /* include space for internal exception vectors */ 2679 s->num_irq += NVIC_FIRST_IRQ; 2680 2681 s->num_prio_bits = arm_feature(&s->cpu->env, ARM_FEATURE_V7) ? 8 : 2; 2682 2683 /* 2684 * This device provides a single memory region which covers the 2685 * sysreg/NVIC registers from 0xE000E000 .. 0xE000EFFF, with the 2686 * exception of the systick timer registers 0xE000E010 .. 0xE000E0FF. 2687 */ 2688 memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s, 2689 "nvic_sysregs", 0x1000); 2690 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sysregmem); 2691 } 2692 2693 static void armv7m_nvic_instance_init(Object *obj) 2694 { 2695 DeviceState *dev = DEVICE(obj); 2696 NVICState *nvic = NVIC(obj); 2697 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 2698 2699 sysbus_init_irq(sbd, &nvic->excpout); 2700 qdev_init_gpio_out_named(dev, &nvic->sysresetreq, "SYSRESETREQ", 1); 2701 qdev_init_gpio_in_named(dev, nvic_systick_trigger, "systick-trigger", 2702 M_REG_NUM_BANKS); 2703 qdev_init_gpio_in_named(dev, nvic_nmi_trigger, "NMI", 1); 2704 } 2705 2706 static void armv7m_nvic_class_init(ObjectClass *klass, void *data) 2707 { 2708 DeviceClass *dc = DEVICE_CLASS(klass); 2709 2710 dc->vmsd = &vmstate_nvic; 2711 device_class_set_props(dc, props_nvic); 2712 dc->reset = armv7m_nvic_reset; 2713 dc->realize = armv7m_nvic_realize; 2714 } 2715 2716 static const TypeInfo armv7m_nvic_info = { 2717 .name = TYPE_NVIC, 2718 .parent = TYPE_SYS_BUS_DEVICE, 2719 .instance_init = armv7m_nvic_instance_init, 2720 .instance_size = sizeof(NVICState), 2721 .class_init = armv7m_nvic_class_init, 2722 .class_size = sizeof(SysBusDeviceClass), 2723 }; 2724 2725 static void armv7m_nvic_register_types(void) 2726 { 2727 type_register_static(&armv7m_nvic_info); 2728 } 2729 2730 type_init(armv7m_nvic_register_types) 2731