1 /* 2 * ARM Nested Vectored Interrupt Controller 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 * 9 * The ARMv7M System controller is fairly tightly tied in with the 10 * NVIC. Much of that is also implemented here. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "qapi/error.h" 15 #include "qemu-common.h" 16 #include "cpu.h" 17 #include "hw/sysbus.h" 18 #include "qemu/timer.h" 19 #include "hw/arm/arm.h" 20 #include "hw/intc/armv7m_nvic.h" 21 #include "target/arm/cpu.h" 22 #include "exec/exec-all.h" 23 #include "qemu/log.h" 24 #include "trace.h" 25 26 /* IRQ number counting: 27 * 28 * the num-irq property counts the number of external IRQ lines 29 * 30 * NVICState::num_irq counts the total number of exceptions 31 * (external IRQs, the 15 internal exceptions including reset, 32 * and one for the unused exception number 0). 33 * 34 * NVIC_MAX_IRQ is the highest permitted number of external IRQ lines. 35 * 36 * NVIC_MAX_VECTORS is the highest permitted number of exceptions. 37 * 38 * Iterating through all exceptions should typically be done with 39 * for (i = 1; i < s->num_irq; i++) to avoid the unused slot 0. 40 * 41 * The external qemu_irq lines are the NVIC's external IRQ lines, 42 * so line 0 is exception 16. 43 * 44 * In the terminology of the architecture manual, "interrupts" are 45 * a subcategory of exception referring to the external interrupts 46 * (which are exception numbers NVIC_FIRST_IRQ and upward). 47 * For historical reasons QEMU tends to use "interrupt" and 48 * "exception" more or less interchangeably. 49 */ 50 #define NVIC_FIRST_IRQ NVIC_INTERNAL_VECTORS 51 #define NVIC_MAX_IRQ (NVIC_MAX_VECTORS - NVIC_FIRST_IRQ) 52 53 /* Effective running priority of the CPU when no exception is active 54 * (higher than the highest possible priority value) 55 */ 56 #define NVIC_NOEXC_PRIO 0x100 57 /* Maximum priority of non-secure exceptions when AIRCR.PRIS is set */ 58 #define NVIC_NS_PRIO_LIMIT 0x80 59 60 static const uint8_t nvic_id[] = { 61 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1 62 }; 63 64 static int nvic_pending_prio(NVICState *s) 65 { 66 /* return the group priority of the current pending interrupt, 67 * or NVIC_NOEXC_PRIO if no interrupt is pending 68 */ 69 return s->vectpending_prio; 70 } 71 72 /* Return the value of the ISCR RETTOBASE bit: 73 * 1 if there is exactly one active exception 74 * 0 if there is more than one active exception 75 * UNKNOWN if there are no active exceptions (we choose 1, 76 * which matches the choice Cortex-M3 is documented as making). 77 * 78 * NB: some versions of the documentation talk about this 79 * counting "active exceptions other than the one shown by IPSR"; 80 * this is only different in the obscure corner case where guest 81 * code has manually deactivated an exception and is about 82 * to fail an exception-return integrity check. The definition 83 * above is the one from the v8M ARM ARM and is also in line 84 * with the behaviour documented for the Cortex-M3. 85 */ 86 static bool nvic_rettobase(NVICState *s) 87 { 88 int irq, nhand = 0; 89 bool check_sec = arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY); 90 91 for (irq = ARMV7M_EXCP_RESET; irq < s->num_irq; irq++) { 92 if (s->vectors[irq].active || 93 (check_sec && irq < NVIC_INTERNAL_VECTORS && 94 s->sec_vectors[irq].active)) { 95 nhand++; 96 if (nhand == 2) { 97 return 0; 98 } 99 } 100 } 101 102 return 1; 103 } 104 105 /* Return the value of the ISCR ISRPENDING bit: 106 * 1 if an external interrupt is pending 107 * 0 if no external interrupt is pending 108 */ 109 static bool nvic_isrpending(NVICState *s) 110 { 111 int irq; 112 113 /* We can shortcut if the highest priority pending interrupt 114 * happens to be external or if there is nothing pending. 115 */ 116 if (s->vectpending > NVIC_FIRST_IRQ) { 117 return true; 118 } 119 if (s->vectpending == 0) { 120 return false; 121 } 122 123 for (irq = NVIC_FIRST_IRQ; irq < s->num_irq; irq++) { 124 if (s->vectors[irq].pending) { 125 return true; 126 } 127 } 128 return false; 129 } 130 131 static bool exc_is_banked(int exc) 132 { 133 /* Return true if this is one of the limited set of exceptions which 134 * are banked (and thus have state in sec_vectors[]) 135 */ 136 return exc == ARMV7M_EXCP_HARD || 137 exc == ARMV7M_EXCP_MEM || 138 exc == ARMV7M_EXCP_USAGE || 139 exc == ARMV7M_EXCP_SVC || 140 exc == ARMV7M_EXCP_PENDSV || 141 exc == ARMV7M_EXCP_SYSTICK; 142 } 143 144 /* Return a mask word which clears the subpriority bits from 145 * a priority value for an M-profile exception, leaving only 146 * the group priority. 147 */ 148 static inline uint32_t nvic_gprio_mask(NVICState *s, bool secure) 149 { 150 return ~0U << (s->prigroup[secure] + 1); 151 } 152 153 static bool exc_targets_secure(NVICState *s, int exc) 154 { 155 /* Return true if this non-banked exception targets Secure state. */ 156 if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) { 157 return false; 158 } 159 160 if (exc >= NVIC_FIRST_IRQ) { 161 return !s->itns[exc]; 162 } 163 164 /* Function shouldn't be called for banked exceptions. */ 165 assert(!exc_is_banked(exc)); 166 167 switch (exc) { 168 case ARMV7M_EXCP_NMI: 169 case ARMV7M_EXCP_BUS: 170 return !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK); 171 case ARMV7M_EXCP_SECURE: 172 return true; 173 case ARMV7M_EXCP_DEBUG: 174 /* TODO: controlled by DEMCR.SDME, which we don't yet implement */ 175 return false; 176 default: 177 /* reset, and reserved (unused) low exception numbers. 178 * We'll get called by code that loops through all the exception 179 * numbers, but it doesn't matter what we return here as these 180 * non-existent exceptions will never be pended or active. 181 */ 182 return true; 183 } 184 } 185 186 static int exc_group_prio(NVICState *s, int rawprio, bool targets_secure) 187 { 188 /* Return the group priority for this exception, given its raw 189 * (group-and-subgroup) priority value and whether it is targeting 190 * secure state or not. 191 */ 192 if (rawprio < 0) { 193 return rawprio; 194 } 195 rawprio &= nvic_gprio_mask(s, targets_secure); 196 /* AIRCR.PRIS causes us to squash all NS priorities into the 197 * lower half of the total range 198 */ 199 if (!targets_secure && 200 (s->cpu->env.v7m.aircr & R_V7M_AIRCR_PRIS_MASK)) { 201 rawprio = (rawprio >> 1) + NVIC_NS_PRIO_LIMIT; 202 } 203 return rawprio; 204 } 205 206 /* Recompute vectpending and exception_prio for a CPU which implements 207 * the Security extension 208 */ 209 static void nvic_recompute_state_secure(NVICState *s) 210 { 211 int i, bank; 212 int pend_prio = NVIC_NOEXC_PRIO; 213 int active_prio = NVIC_NOEXC_PRIO; 214 int pend_irq = 0; 215 bool pending_is_s_banked = false; 216 217 /* R_CQRV: precedence is by: 218 * - lowest group priority; if both the same then 219 * - lowest subpriority; if both the same then 220 * - lowest exception number; if both the same (ie banked) then 221 * - secure exception takes precedence 222 * Compare pseudocode RawExecutionPriority. 223 * Annoyingly, now we have two prigroup values (for S and NS) 224 * we can't do the loop comparison on raw priority values. 225 */ 226 for (i = 1; i < s->num_irq; i++) { 227 for (bank = M_REG_S; bank >= M_REG_NS; bank--) { 228 VecInfo *vec; 229 int prio; 230 bool targets_secure; 231 232 if (bank == M_REG_S) { 233 if (!exc_is_banked(i)) { 234 continue; 235 } 236 vec = &s->sec_vectors[i]; 237 targets_secure = true; 238 } else { 239 vec = &s->vectors[i]; 240 targets_secure = !exc_is_banked(i) && exc_targets_secure(s, i); 241 } 242 243 prio = exc_group_prio(s, vec->prio, targets_secure); 244 if (vec->enabled && vec->pending && prio < pend_prio) { 245 pend_prio = prio; 246 pend_irq = i; 247 pending_is_s_banked = (bank == M_REG_S); 248 } 249 if (vec->active && prio < active_prio) { 250 active_prio = prio; 251 } 252 } 253 } 254 255 s->vectpending_is_s_banked = pending_is_s_banked; 256 s->vectpending = pend_irq; 257 s->vectpending_prio = pend_prio; 258 s->exception_prio = active_prio; 259 260 trace_nvic_recompute_state_secure(s->vectpending, 261 s->vectpending_is_s_banked, 262 s->vectpending_prio, 263 s->exception_prio); 264 } 265 266 /* Recompute vectpending and exception_prio */ 267 static void nvic_recompute_state(NVICState *s) 268 { 269 int i; 270 int pend_prio = NVIC_NOEXC_PRIO; 271 int active_prio = NVIC_NOEXC_PRIO; 272 int pend_irq = 0; 273 274 /* In theory we could write one function that handled both 275 * the "security extension present" and "not present"; however 276 * the security related changes significantly complicate the 277 * recomputation just by themselves and mixing both cases together 278 * would be even worse, so we retain a separate non-secure-only 279 * version for CPUs which don't implement the security extension. 280 */ 281 if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) { 282 nvic_recompute_state_secure(s); 283 return; 284 } 285 286 for (i = 1; i < s->num_irq; i++) { 287 VecInfo *vec = &s->vectors[i]; 288 289 if (vec->enabled && vec->pending && vec->prio < pend_prio) { 290 pend_prio = vec->prio; 291 pend_irq = i; 292 } 293 if (vec->active && vec->prio < active_prio) { 294 active_prio = vec->prio; 295 } 296 } 297 298 if (active_prio > 0) { 299 active_prio &= nvic_gprio_mask(s, false); 300 } 301 302 if (pend_prio > 0) { 303 pend_prio &= nvic_gprio_mask(s, false); 304 } 305 306 s->vectpending = pend_irq; 307 s->vectpending_prio = pend_prio; 308 s->exception_prio = active_prio; 309 310 trace_nvic_recompute_state(s->vectpending, 311 s->vectpending_prio, 312 s->exception_prio); 313 } 314 315 /* Return the current execution priority of the CPU 316 * (equivalent to the pseudocode ExecutionPriority function). 317 * This is a value between -2 (NMI priority) and NVIC_NOEXC_PRIO. 318 */ 319 static inline int nvic_exec_prio(NVICState *s) 320 { 321 CPUARMState *env = &s->cpu->env; 322 int running; 323 324 if (env->v7m.faultmask[env->v7m.secure]) { 325 running = -1; 326 } else if (env->v7m.primask[env->v7m.secure]) { 327 running = 0; 328 } else if (env->v7m.basepri[env->v7m.secure] > 0) { 329 running = env->v7m.basepri[env->v7m.secure] & 330 nvic_gprio_mask(s, env->v7m.secure); 331 } else { 332 running = NVIC_NOEXC_PRIO; /* lower than any possible priority */ 333 } 334 /* consider priority of active handler */ 335 return MIN(running, s->exception_prio); 336 } 337 338 bool armv7m_nvic_can_take_pending_exception(void *opaque) 339 { 340 NVICState *s = opaque; 341 342 return nvic_exec_prio(s) > nvic_pending_prio(s); 343 } 344 345 int armv7m_nvic_raw_execution_priority(void *opaque) 346 { 347 NVICState *s = opaque; 348 349 return s->exception_prio; 350 } 351 352 /* caller must call nvic_irq_update() after this. 353 * secure indicates the bank to use for banked exceptions (we assert if 354 * we are passed secure=true for a non-banked exception). 355 */ 356 static void set_prio(NVICState *s, unsigned irq, bool secure, uint8_t prio) 357 { 358 assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */ 359 assert(irq < s->num_irq); 360 361 if (secure) { 362 assert(exc_is_banked(irq)); 363 s->sec_vectors[irq].prio = prio; 364 } else { 365 s->vectors[irq].prio = prio; 366 } 367 368 trace_nvic_set_prio(irq, secure, prio); 369 } 370 371 /* Return the current raw priority register value. 372 * secure indicates the bank to use for banked exceptions (we assert if 373 * we are passed secure=true for a non-banked exception). 374 */ 375 static int get_prio(NVICState *s, unsigned irq, bool secure) 376 { 377 assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */ 378 assert(irq < s->num_irq); 379 380 if (secure) { 381 assert(exc_is_banked(irq)); 382 return s->sec_vectors[irq].prio; 383 } else { 384 return s->vectors[irq].prio; 385 } 386 } 387 388 /* Recompute state and assert irq line accordingly. 389 * Must be called after changes to: 390 * vec->active, vec->enabled, vec->pending or vec->prio for any vector 391 * prigroup 392 */ 393 static void nvic_irq_update(NVICState *s) 394 { 395 int lvl; 396 int pend_prio; 397 398 nvic_recompute_state(s); 399 pend_prio = nvic_pending_prio(s); 400 401 /* Raise NVIC output if this IRQ would be taken, except that we 402 * ignore the effects of the BASEPRI, FAULTMASK and PRIMASK (which 403 * will be checked for in arm_v7m_cpu_exec_interrupt()); changes 404 * to those CPU registers don't cause us to recalculate the NVIC 405 * pending info. 406 */ 407 lvl = (pend_prio < s->exception_prio); 408 trace_nvic_irq_update(s->vectpending, pend_prio, s->exception_prio, lvl); 409 qemu_set_irq(s->excpout, lvl); 410 } 411 412 /** 413 * armv7m_nvic_clear_pending: mark the specified exception as not pending 414 * @opaque: the NVIC 415 * @irq: the exception number to mark as not pending 416 * @secure: false for non-banked exceptions or for the nonsecure 417 * version of a banked exception, true for the secure version of a banked 418 * exception. 419 * 420 * Marks the specified exception as not pending. Note that we will assert() 421 * if @secure is true and @irq does not specify one of the fixed set 422 * of architecturally banked exceptions. 423 */ 424 static void armv7m_nvic_clear_pending(void *opaque, int irq, bool secure) 425 { 426 NVICState *s = (NVICState *)opaque; 427 VecInfo *vec; 428 429 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); 430 431 if (secure) { 432 assert(exc_is_banked(irq)); 433 vec = &s->sec_vectors[irq]; 434 } else { 435 vec = &s->vectors[irq]; 436 } 437 trace_nvic_clear_pending(irq, secure, vec->enabled, vec->prio); 438 if (vec->pending) { 439 vec->pending = 0; 440 nvic_irq_update(s); 441 } 442 } 443 444 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure) 445 { 446 NVICState *s = (NVICState *)opaque; 447 bool banked = exc_is_banked(irq); 448 VecInfo *vec; 449 450 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); 451 assert(!secure || banked); 452 453 vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq]; 454 455 trace_nvic_set_pending(irq, secure, vec->enabled, vec->prio); 456 457 if (irq >= ARMV7M_EXCP_HARD && irq < ARMV7M_EXCP_PENDSV) { 458 /* If a synchronous exception is pending then it may be 459 * escalated to HardFault if: 460 * * it is equal or lower priority to current execution 461 * * it is disabled 462 * (ie we need to take it immediately but we can't do so). 463 * Asynchronous exceptions (and interrupts) simply remain pending. 464 * 465 * For QEMU, we don't have any imprecise (asynchronous) faults, 466 * so we can assume that PREFETCH_ABORT and DATA_ABORT are always 467 * synchronous. 468 * Debug exceptions are awkward because only Debug exceptions 469 * resulting from the BKPT instruction should be escalated, 470 * but we don't currently implement any Debug exceptions other 471 * than those that result from BKPT, so we treat all debug exceptions 472 * as needing escalation. 473 * 474 * This all means we can identify whether to escalate based only on 475 * the exception number and don't (yet) need the caller to explicitly 476 * tell us whether this exception is synchronous or not. 477 */ 478 int running = nvic_exec_prio(s); 479 bool escalate = false; 480 481 if (exc_group_prio(s, vec->prio, secure) >= running) { 482 trace_nvic_escalate_prio(irq, vec->prio, running); 483 escalate = true; 484 } else if (!vec->enabled) { 485 trace_nvic_escalate_disabled(irq); 486 escalate = true; 487 } 488 489 if (escalate) { 490 491 /* We need to escalate this exception to a synchronous HardFault. 492 * If BFHFNMINS is set then we escalate to the banked HF for 493 * the target security state of the original exception; otherwise 494 * we take a Secure HardFault. 495 */ 496 irq = ARMV7M_EXCP_HARD; 497 if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) && 498 (secure || 499 !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK))) { 500 vec = &s->sec_vectors[irq]; 501 } else { 502 vec = &s->vectors[irq]; 503 } 504 if (running <= vec->prio) { 505 /* We want to escalate to HardFault but we can't take the 506 * synchronous HardFault at this point either. This is a 507 * Lockup condition due to a guest bug. We don't model 508 * Lockup, so report via cpu_abort() instead. 509 */ 510 cpu_abort(&s->cpu->parent_obj, 511 "Lockup: can't escalate %d to HardFault " 512 "(current priority %d)\n", irq, running); 513 } 514 515 /* HF may be banked but there is only one shared HFSR */ 516 s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK; 517 } 518 } 519 520 if (!vec->pending) { 521 vec->pending = 1; 522 nvic_irq_update(s); 523 } 524 } 525 526 /* Make pending IRQ active. */ 527 void armv7m_nvic_acknowledge_irq(void *opaque) 528 { 529 NVICState *s = (NVICState *)opaque; 530 CPUARMState *env = &s->cpu->env; 531 const int pending = s->vectpending; 532 const int running = nvic_exec_prio(s); 533 VecInfo *vec; 534 535 assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq); 536 537 vec = &s->vectors[pending]; 538 539 assert(vec->enabled); 540 assert(vec->pending); 541 542 assert(s->vectpending_prio < running); 543 544 trace_nvic_acknowledge_irq(pending, s->vectpending_prio); 545 546 vec->active = 1; 547 vec->pending = 0; 548 549 env->v7m.exception = s->vectpending; 550 551 nvic_irq_update(s); 552 } 553 554 int armv7m_nvic_complete_irq(void *opaque, int irq) 555 { 556 NVICState *s = (NVICState *)opaque; 557 VecInfo *vec; 558 int ret; 559 560 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); 561 562 vec = &s->vectors[irq]; 563 564 trace_nvic_complete_irq(irq); 565 566 if (!vec->active) { 567 /* Tell the caller this was an illegal exception return */ 568 return -1; 569 } 570 571 ret = nvic_rettobase(s); 572 573 vec->active = 0; 574 if (vec->level) { 575 /* Re-pend the exception if it's still held high; only 576 * happens for extenal IRQs 577 */ 578 assert(irq >= NVIC_FIRST_IRQ); 579 vec->pending = 1; 580 } 581 582 nvic_irq_update(s); 583 584 return ret; 585 } 586 587 /* callback when external interrupt line is changed */ 588 static void set_irq_level(void *opaque, int n, int level) 589 { 590 NVICState *s = opaque; 591 VecInfo *vec; 592 593 n += NVIC_FIRST_IRQ; 594 595 assert(n >= NVIC_FIRST_IRQ && n < s->num_irq); 596 597 trace_nvic_set_irq_level(n, level); 598 599 /* The pending status of an external interrupt is 600 * latched on rising edge and exception handler return. 601 * 602 * Pulsing the IRQ will always run the handler 603 * once, and the handler will re-run until the 604 * level is low when the handler completes. 605 */ 606 vec = &s->vectors[n]; 607 if (level != vec->level) { 608 vec->level = level; 609 if (level) { 610 armv7m_nvic_set_pending(s, n, false); 611 } 612 } 613 } 614 615 static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) 616 { 617 ARMCPU *cpu = s->cpu; 618 uint32_t val; 619 620 switch (offset) { 621 case 4: /* Interrupt Control Type. */ 622 return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1; 623 case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */ 624 { 625 int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ; 626 int i; 627 628 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 629 goto bad_offset; 630 } 631 if (!attrs.secure) { 632 return 0; 633 } 634 val = 0; 635 for (i = 0; i < 32 && startvec + i < s->num_irq; i++) { 636 if (s->itns[startvec + i]) { 637 val |= (1 << i); 638 } 639 } 640 return val; 641 } 642 case 0xd00: /* CPUID Base. */ 643 return cpu->midr; 644 case 0xd04: /* Interrupt Control State. */ 645 /* VECTACTIVE */ 646 val = cpu->env.v7m.exception; 647 /* VECTPENDING */ 648 val |= (s->vectpending & 0xff) << 12; 649 /* ISRPENDING - set if any external IRQ is pending */ 650 if (nvic_isrpending(s)) { 651 val |= (1 << 22); 652 } 653 /* RETTOBASE - set if only one handler is active */ 654 if (nvic_rettobase(s)) { 655 val |= (1 << 11); 656 } 657 /* PENDSTSET */ 658 if (s->vectors[ARMV7M_EXCP_SYSTICK].pending) { 659 val |= (1 << 26); 660 } 661 /* PENDSVSET */ 662 if (s->vectors[ARMV7M_EXCP_PENDSV].pending) { 663 val |= (1 << 28); 664 } 665 /* NMIPENDSET */ 666 if (s->vectors[ARMV7M_EXCP_NMI].pending) { 667 val |= (1 << 31); 668 } 669 /* ISRPREEMPT not implemented */ 670 return val; 671 case 0xd08: /* Vector Table Offset. */ 672 return cpu->env.v7m.vecbase[attrs.secure]; 673 case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */ 674 val = 0xfa050000 | (s->prigroup[attrs.secure] << 8); 675 if (attrs.secure) { 676 /* s->aircr stores PRIS, BFHFNMINS, SYSRESETREQS */ 677 val |= cpu->env.v7m.aircr; 678 } else { 679 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 680 /* BFHFNMINS is R/O from NS; other bits are RAZ/WI. If 681 * security isn't supported then BFHFNMINS is RAO (and 682 * the bit in env.v7m.aircr is always set). 683 */ 684 val |= cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK; 685 } 686 } 687 return val; 688 case 0xd10: /* System Control. */ 689 /* TODO: Implement SLEEPONEXIT. */ 690 return 0; 691 case 0xd14: /* Configuration Control. */ 692 /* The BFHFNMIGN bit is the only non-banked bit; we 693 * keep it in the non-secure copy of the register. 694 */ 695 val = cpu->env.v7m.ccr[attrs.secure]; 696 val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK; 697 return val; 698 case 0xd24: /* System Handler Status. */ 699 val = 0; 700 if (s->vectors[ARMV7M_EXCP_MEM].active) { 701 val |= (1 << 0); 702 } 703 if (s->vectors[ARMV7M_EXCP_BUS].active) { 704 val |= (1 << 1); 705 } 706 if (s->vectors[ARMV7M_EXCP_USAGE].active) { 707 val |= (1 << 3); 708 } 709 if (s->vectors[ARMV7M_EXCP_SVC].active) { 710 val |= (1 << 7); 711 } 712 if (s->vectors[ARMV7M_EXCP_DEBUG].active) { 713 val |= (1 << 8); 714 } 715 if (s->vectors[ARMV7M_EXCP_PENDSV].active) { 716 val |= (1 << 10); 717 } 718 if (s->vectors[ARMV7M_EXCP_SYSTICK].active) { 719 val |= (1 << 11); 720 } 721 if (s->vectors[ARMV7M_EXCP_USAGE].pending) { 722 val |= (1 << 12); 723 } 724 if (s->vectors[ARMV7M_EXCP_MEM].pending) { 725 val |= (1 << 13); 726 } 727 if (s->vectors[ARMV7M_EXCP_BUS].pending) { 728 val |= (1 << 14); 729 } 730 if (s->vectors[ARMV7M_EXCP_SVC].pending) { 731 val |= (1 << 15); 732 } 733 if (s->vectors[ARMV7M_EXCP_MEM].enabled) { 734 val |= (1 << 16); 735 } 736 if (s->vectors[ARMV7M_EXCP_BUS].enabled) { 737 val |= (1 << 17); 738 } 739 if (s->vectors[ARMV7M_EXCP_USAGE].enabled) { 740 val |= (1 << 18); 741 } 742 return val; 743 case 0xd28: /* Configurable Fault Status. */ 744 /* The BFSR bits [15:8] are shared between security states 745 * and we store them in the NS copy 746 */ 747 val = cpu->env.v7m.cfsr[attrs.secure]; 748 val |= cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK; 749 return val; 750 case 0xd2c: /* Hard Fault Status. */ 751 return cpu->env.v7m.hfsr; 752 case 0xd30: /* Debug Fault Status. */ 753 return cpu->env.v7m.dfsr; 754 case 0xd34: /* MMFAR MemManage Fault Address */ 755 return cpu->env.v7m.mmfar[attrs.secure]; 756 case 0xd38: /* Bus Fault Address. */ 757 return cpu->env.v7m.bfar; 758 case 0xd3c: /* Aux Fault Status. */ 759 /* TODO: Implement fault status registers. */ 760 qemu_log_mask(LOG_UNIMP, 761 "Aux Fault status registers unimplemented\n"); 762 return 0; 763 case 0xd40: /* PFR0. */ 764 return 0x00000030; 765 case 0xd44: /* PRF1. */ 766 return 0x00000200; 767 case 0xd48: /* DFR0. */ 768 return 0x00100000; 769 case 0xd4c: /* AFR0. */ 770 return 0x00000000; 771 case 0xd50: /* MMFR0. */ 772 return 0x00000030; 773 case 0xd54: /* MMFR1. */ 774 return 0x00000000; 775 case 0xd58: /* MMFR2. */ 776 return 0x00000000; 777 case 0xd5c: /* MMFR3. */ 778 return 0x00000000; 779 case 0xd60: /* ISAR0. */ 780 return 0x01141110; 781 case 0xd64: /* ISAR1. */ 782 return 0x02111000; 783 case 0xd68: /* ISAR2. */ 784 return 0x21112231; 785 case 0xd6c: /* ISAR3. */ 786 return 0x01111110; 787 case 0xd70: /* ISAR4. */ 788 return 0x01310102; 789 /* TODO: Implement debug registers. */ 790 case 0xd90: /* MPU_TYPE */ 791 /* Unified MPU; if the MPU is not present this value is zero */ 792 return cpu->pmsav7_dregion << 8; 793 break; 794 case 0xd94: /* MPU_CTRL */ 795 return cpu->env.v7m.mpu_ctrl[attrs.secure]; 796 case 0xd98: /* MPU_RNR */ 797 return cpu->env.pmsav7.rnr[attrs.secure]; 798 case 0xd9c: /* MPU_RBAR */ 799 case 0xda4: /* MPU_RBAR_A1 */ 800 case 0xdac: /* MPU_RBAR_A2 */ 801 case 0xdb4: /* MPU_RBAR_A3 */ 802 { 803 int region = cpu->env.pmsav7.rnr[attrs.secure]; 804 805 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 806 /* PMSAv8M handling of the aliases is different from v7M: 807 * aliases A1, A2, A3 override the low two bits of the region 808 * number in MPU_RNR, and there is no 'region' field in the 809 * RBAR register. 810 */ 811 int aliasno = (offset - 0xd9c) / 8; /* 0..3 */ 812 if (aliasno) { 813 region = deposit32(region, 0, 2, aliasno); 814 } 815 if (region >= cpu->pmsav7_dregion) { 816 return 0; 817 } 818 return cpu->env.pmsav8.rbar[attrs.secure][region]; 819 } 820 821 if (region >= cpu->pmsav7_dregion) { 822 return 0; 823 } 824 return (cpu->env.pmsav7.drbar[region] & 0x1f) | (region & 0xf); 825 } 826 case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */ 827 case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */ 828 case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */ 829 case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */ 830 { 831 int region = cpu->env.pmsav7.rnr[attrs.secure]; 832 833 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 834 /* PMSAv8M handling of the aliases is different from v7M: 835 * aliases A1, A2, A3 override the low two bits of the region 836 * number in MPU_RNR. 837 */ 838 int aliasno = (offset - 0xda0) / 8; /* 0..3 */ 839 if (aliasno) { 840 region = deposit32(region, 0, 2, aliasno); 841 } 842 if (region >= cpu->pmsav7_dregion) { 843 return 0; 844 } 845 return cpu->env.pmsav8.rlar[attrs.secure][region]; 846 } 847 848 if (region >= cpu->pmsav7_dregion) { 849 return 0; 850 } 851 return ((cpu->env.pmsav7.dracr[region] & 0xffff) << 16) | 852 (cpu->env.pmsav7.drsr[region] & 0xffff); 853 } 854 case 0xdc0: /* MPU_MAIR0 */ 855 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 856 goto bad_offset; 857 } 858 return cpu->env.pmsav8.mair0[attrs.secure]; 859 case 0xdc4: /* MPU_MAIR1 */ 860 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 861 goto bad_offset; 862 } 863 return cpu->env.pmsav8.mair1[attrs.secure]; 864 default: 865 bad_offset: 866 qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset); 867 return 0; 868 } 869 } 870 871 static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, 872 MemTxAttrs attrs) 873 { 874 ARMCPU *cpu = s->cpu; 875 876 switch (offset) { 877 case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */ 878 { 879 int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ; 880 int i; 881 882 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 883 goto bad_offset; 884 } 885 if (!attrs.secure) { 886 break; 887 } 888 for (i = 0; i < 32 && startvec + i < s->num_irq; i++) { 889 s->itns[startvec + i] = (value >> i) & 1; 890 } 891 nvic_irq_update(s); 892 break; 893 } 894 case 0xd04: /* Interrupt Control State. */ 895 if (value & (1 << 31)) { 896 armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false); 897 } 898 if (value & (1 << 28)) { 899 armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure); 900 } else if (value & (1 << 27)) { 901 armv7m_nvic_clear_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure); 902 } 903 if (value & (1 << 26)) { 904 armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, attrs.secure); 905 } else if (value & (1 << 25)) { 906 armv7m_nvic_clear_pending(s, ARMV7M_EXCP_SYSTICK, attrs.secure); 907 } 908 break; 909 case 0xd08: /* Vector Table Offset. */ 910 cpu->env.v7m.vecbase[attrs.secure] = value & 0xffffff80; 911 break; 912 case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */ 913 if ((value >> R_V7M_AIRCR_VECTKEY_SHIFT) == 0x05fa) { 914 if (value & R_V7M_AIRCR_SYSRESETREQ_MASK) { 915 if (attrs.secure || 916 !(cpu->env.v7m.aircr & R_V7M_AIRCR_SYSRESETREQS_MASK)) { 917 qemu_irq_pulse(s->sysresetreq); 918 } 919 } 920 if (value & R_V7M_AIRCR_VECTCLRACTIVE_MASK) { 921 qemu_log_mask(LOG_GUEST_ERROR, 922 "Setting VECTCLRACTIVE when not in DEBUG mode " 923 "is UNPREDICTABLE\n"); 924 } 925 if (value & R_V7M_AIRCR_VECTRESET_MASK) { 926 /* NB: this bit is RES0 in v8M */ 927 qemu_log_mask(LOG_GUEST_ERROR, 928 "Setting VECTRESET when not in DEBUG mode " 929 "is UNPREDICTABLE\n"); 930 } 931 s->prigroup[attrs.secure] = extract32(value, 932 R_V7M_AIRCR_PRIGROUP_SHIFT, 933 R_V7M_AIRCR_PRIGROUP_LENGTH); 934 if (attrs.secure) { 935 /* These bits are only writable by secure */ 936 cpu->env.v7m.aircr = value & 937 (R_V7M_AIRCR_SYSRESETREQS_MASK | 938 R_V7M_AIRCR_BFHFNMINS_MASK | 939 R_V7M_AIRCR_PRIS_MASK); 940 } 941 nvic_irq_update(s); 942 } 943 break; 944 case 0xd10: /* System Control. */ 945 /* TODO: Implement control registers. */ 946 qemu_log_mask(LOG_UNIMP, "NVIC: SCR unimplemented\n"); 947 break; 948 case 0xd14: /* Configuration Control. */ 949 /* Enforce RAZ/WI on reserved and must-RAZ/WI bits */ 950 value &= (R_V7M_CCR_STKALIGN_MASK | 951 R_V7M_CCR_BFHFNMIGN_MASK | 952 R_V7M_CCR_DIV_0_TRP_MASK | 953 R_V7M_CCR_UNALIGN_TRP_MASK | 954 R_V7M_CCR_USERSETMPEND_MASK | 955 R_V7M_CCR_NONBASETHRDENA_MASK); 956 957 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 958 /* v8M makes NONBASETHRDENA and STKALIGN be RES1 */ 959 value |= R_V7M_CCR_NONBASETHRDENA_MASK 960 | R_V7M_CCR_STKALIGN_MASK; 961 } 962 if (attrs.secure) { 963 /* the BFHFNMIGN bit is not banked; keep that in the NS copy */ 964 cpu->env.v7m.ccr[M_REG_NS] = 965 (cpu->env.v7m.ccr[M_REG_NS] & ~R_V7M_CCR_BFHFNMIGN_MASK) 966 | (value & R_V7M_CCR_BFHFNMIGN_MASK); 967 value &= ~R_V7M_CCR_BFHFNMIGN_MASK; 968 } 969 970 cpu->env.v7m.ccr[attrs.secure] = value; 971 break; 972 case 0xd24: /* System Handler Control. */ 973 s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0; 974 s->vectors[ARMV7M_EXCP_BUS].active = (value & (1 << 1)) != 0; 975 s->vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0; 976 s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0; 977 s->vectors[ARMV7M_EXCP_DEBUG].active = (value & (1 << 8)) != 0; 978 s->vectors[ARMV7M_EXCP_PENDSV].active = (value & (1 << 10)) != 0; 979 s->vectors[ARMV7M_EXCP_SYSTICK].active = (value & (1 << 11)) != 0; 980 s->vectors[ARMV7M_EXCP_USAGE].pending = (value & (1 << 12)) != 0; 981 s->vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0; 982 s->vectors[ARMV7M_EXCP_BUS].pending = (value & (1 << 14)) != 0; 983 s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0; 984 s->vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0; 985 s->vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0; 986 s->vectors[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0; 987 nvic_irq_update(s); 988 break; 989 case 0xd28: /* Configurable Fault Status. */ 990 cpu->env.v7m.cfsr[attrs.secure] &= ~value; /* W1C */ 991 if (attrs.secure) { 992 /* The BFSR bits [15:8] are shared between security states 993 * and we store them in the NS copy. 994 */ 995 cpu->env.v7m.cfsr[M_REG_NS] &= ~(value & R_V7M_CFSR_BFSR_MASK); 996 } 997 break; 998 case 0xd2c: /* Hard Fault Status. */ 999 cpu->env.v7m.hfsr &= ~value; /* W1C */ 1000 break; 1001 case 0xd30: /* Debug Fault Status. */ 1002 cpu->env.v7m.dfsr &= ~value; /* W1C */ 1003 break; 1004 case 0xd34: /* Mem Manage Address. */ 1005 cpu->env.v7m.mmfar[attrs.secure] = value; 1006 return; 1007 case 0xd38: /* Bus Fault Address. */ 1008 cpu->env.v7m.bfar = value; 1009 return; 1010 case 0xd3c: /* Aux Fault Status. */ 1011 qemu_log_mask(LOG_UNIMP, 1012 "NVIC: Aux fault status registers unimplemented\n"); 1013 break; 1014 case 0xd90: /* MPU_TYPE */ 1015 return; /* RO */ 1016 case 0xd94: /* MPU_CTRL */ 1017 if ((value & 1018 (R_V7M_MPU_CTRL_HFNMIENA_MASK | R_V7M_MPU_CTRL_ENABLE_MASK)) 1019 == R_V7M_MPU_CTRL_HFNMIENA_MASK) { 1020 qemu_log_mask(LOG_GUEST_ERROR, "MPU_CTRL: HFNMIENA and !ENABLE is " 1021 "UNPREDICTABLE\n"); 1022 } 1023 cpu->env.v7m.mpu_ctrl[attrs.secure] 1024 = value & (R_V7M_MPU_CTRL_ENABLE_MASK | 1025 R_V7M_MPU_CTRL_HFNMIENA_MASK | 1026 R_V7M_MPU_CTRL_PRIVDEFENA_MASK); 1027 tlb_flush(CPU(cpu)); 1028 break; 1029 case 0xd98: /* MPU_RNR */ 1030 if (value >= cpu->pmsav7_dregion) { 1031 qemu_log_mask(LOG_GUEST_ERROR, "MPU region out of range %" 1032 PRIu32 "/%" PRIu32 "\n", 1033 value, cpu->pmsav7_dregion); 1034 } else { 1035 cpu->env.pmsav7.rnr[attrs.secure] = value; 1036 } 1037 break; 1038 case 0xd9c: /* MPU_RBAR */ 1039 case 0xda4: /* MPU_RBAR_A1 */ 1040 case 0xdac: /* MPU_RBAR_A2 */ 1041 case 0xdb4: /* MPU_RBAR_A3 */ 1042 { 1043 int region; 1044 1045 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1046 /* PMSAv8M handling of the aliases is different from v7M: 1047 * aliases A1, A2, A3 override the low two bits of the region 1048 * number in MPU_RNR, and there is no 'region' field in the 1049 * RBAR register. 1050 */ 1051 int aliasno = (offset - 0xd9c) / 8; /* 0..3 */ 1052 1053 region = cpu->env.pmsav7.rnr[attrs.secure]; 1054 if (aliasno) { 1055 region = deposit32(region, 0, 2, aliasno); 1056 } 1057 if (region >= cpu->pmsav7_dregion) { 1058 return; 1059 } 1060 cpu->env.pmsav8.rbar[attrs.secure][region] = value; 1061 tlb_flush(CPU(cpu)); 1062 return; 1063 } 1064 1065 if (value & (1 << 4)) { 1066 /* VALID bit means use the region number specified in this 1067 * value and also update MPU_RNR.REGION with that value. 1068 */ 1069 region = extract32(value, 0, 4); 1070 if (region >= cpu->pmsav7_dregion) { 1071 qemu_log_mask(LOG_GUEST_ERROR, 1072 "MPU region out of range %u/%" PRIu32 "\n", 1073 region, cpu->pmsav7_dregion); 1074 return; 1075 } 1076 cpu->env.pmsav7.rnr[attrs.secure] = region; 1077 } else { 1078 region = cpu->env.pmsav7.rnr[attrs.secure]; 1079 } 1080 1081 if (region >= cpu->pmsav7_dregion) { 1082 return; 1083 } 1084 1085 cpu->env.pmsav7.drbar[region] = value & ~0x1f; 1086 tlb_flush(CPU(cpu)); 1087 break; 1088 } 1089 case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */ 1090 case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */ 1091 case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */ 1092 case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */ 1093 { 1094 int region = cpu->env.pmsav7.rnr[attrs.secure]; 1095 1096 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1097 /* PMSAv8M handling of the aliases is different from v7M: 1098 * aliases A1, A2, A3 override the low two bits of the region 1099 * number in MPU_RNR. 1100 */ 1101 int aliasno = (offset - 0xd9c) / 8; /* 0..3 */ 1102 1103 region = cpu->env.pmsav7.rnr[attrs.secure]; 1104 if (aliasno) { 1105 region = deposit32(region, 0, 2, aliasno); 1106 } 1107 if (region >= cpu->pmsav7_dregion) { 1108 return; 1109 } 1110 cpu->env.pmsav8.rlar[attrs.secure][region] = value; 1111 tlb_flush(CPU(cpu)); 1112 return; 1113 } 1114 1115 if (region >= cpu->pmsav7_dregion) { 1116 return; 1117 } 1118 1119 cpu->env.pmsav7.drsr[region] = value & 0xff3f; 1120 cpu->env.pmsav7.dracr[region] = (value >> 16) & 0x173f; 1121 tlb_flush(CPU(cpu)); 1122 break; 1123 } 1124 case 0xdc0: /* MPU_MAIR0 */ 1125 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1126 goto bad_offset; 1127 } 1128 if (cpu->pmsav7_dregion) { 1129 /* Register is RES0 if no MPU regions are implemented */ 1130 cpu->env.pmsav8.mair0[attrs.secure] = value; 1131 } 1132 /* We don't need to do anything else because memory attributes 1133 * only affect cacheability, and we don't implement caching. 1134 */ 1135 break; 1136 case 0xdc4: /* MPU_MAIR1 */ 1137 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1138 goto bad_offset; 1139 } 1140 if (cpu->pmsav7_dregion) { 1141 /* Register is RES0 if no MPU regions are implemented */ 1142 cpu->env.pmsav8.mair1[attrs.secure] = value; 1143 } 1144 /* We don't need to do anything else because memory attributes 1145 * only affect cacheability, and we don't implement caching. 1146 */ 1147 break; 1148 case 0xf00: /* Software Triggered Interrupt Register */ 1149 { 1150 int excnum = (value & 0x1ff) + NVIC_FIRST_IRQ; 1151 if (excnum < s->num_irq) { 1152 armv7m_nvic_set_pending(s, excnum, false); 1153 } 1154 break; 1155 } 1156 default: 1157 bad_offset: 1158 qemu_log_mask(LOG_GUEST_ERROR, 1159 "NVIC: Bad write offset 0x%x\n", offset); 1160 } 1161 } 1162 1163 static bool nvic_user_access_ok(NVICState *s, hwaddr offset, MemTxAttrs attrs) 1164 { 1165 /* Return true if unprivileged access to this register is permitted. */ 1166 switch (offset) { 1167 case 0xf00: /* STIR: accessible only if CCR.USERSETMPEND permits */ 1168 /* For access via STIR_NS it is the NS CCR.USERSETMPEND that 1169 * controls access even though the CPU is in Secure state (I_QDKX). 1170 */ 1171 return s->cpu->env.v7m.ccr[attrs.secure] & R_V7M_CCR_USERSETMPEND_MASK; 1172 default: 1173 /* All other user accesses cause a BusFault unconditionally */ 1174 return false; 1175 } 1176 } 1177 1178 static int shpr_bank(NVICState *s, int exc, MemTxAttrs attrs) 1179 { 1180 /* Behaviour for the SHPR register field for this exception: 1181 * return M_REG_NS to use the nonsecure vector (including for 1182 * non-banked exceptions), M_REG_S for the secure version of 1183 * a banked exception, and -1 if this field should RAZ/WI. 1184 */ 1185 switch (exc) { 1186 case ARMV7M_EXCP_MEM: 1187 case ARMV7M_EXCP_USAGE: 1188 case ARMV7M_EXCP_SVC: 1189 case ARMV7M_EXCP_PENDSV: 1190 case ARMV7M_EXCP_SYSTICK: 1191 /* Banked exceptions */ 1192 return attrs.secure; 1193 case ARMV7M_EXCP_BUS: 1194 /* Not banked, RAZ/WI from nonsecure if BFHFNMINS is zero */ 1195 if (!attrs.secure && 1196 !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { 1197 return -1; 1198 } 1199 return M_REG_NS; 1200 case ARMV7M_EXCP_SECURE: 1201 /* Not banked, RAZ/WI from nonsecure */ 1202 if (!attrs.secure) { 1203 return -1; 1204 } 1205 return M_REG_NS; 1206 case ARMV7M_EXCP_DEBUG: 1207 /* Not banked. TODO should RAZ/WI if DEMCR.SDME is set */ 1208 return M_REG_NS; 1209 case 8 ... 10: 1210 case 13: 1211 /* RES0 */ 1212 return -1; 1213 default: 1214 /* Not reachable due to decode of SHPR register addresses */ 1215 g_assert_not_reached(); 1216 } 1217 } 1218 1219 static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, 1220 uint64_t *data, unsigned size, 1221 MemTxAttrs attrs) 1222 { 1223 NVICState *s = (NVICState *)opaque; 1224 uint32_t offset = addr; 1225 unsigned i, startvec, end; 1226 uint32_t val; 1227 1228 if (attrs.user && !nvic_user_access_ok(s, addr, attrs)) { 1229 /* Generate BusFault for unprivileged accesses */ 1230 return MEMTX_ERROR; 1231 } 1232 1233 switch (offset) { 1234 /* reads of set and clear both return the status */ 1235 case 0x100 ... 0x13f: /* NVIC Set enable */ 1236 offset += 0x80; 1237 /* fall through */ 1238 case 0x180 ... 0x1bf: /* NVIC Clear enable */ 1239 val = 0; 1240 startvec = offset - 0x180 + NVIC_FIRST_IRQ; /* vector # */ 1241 1242 for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { 1243 if (s->vectors[startvec + i].enabled && 1244 (attrs.secure || s->itns[startvec + i])) { 1245 val |= (1 << i); 1246 } 1247 } 1248 break; 1249 case 0x200 ... 0x23f: /* NVIC Set pend */ 1250 offset += 0x80; 1251 /* fall through */ 1252 case 0x280 ... 0x2bf: /* NVIC Clear pend */ 1253 val = 0; 1254 startvec = offset - 0x280 + NVIC_FIRST_IRQ; /* vector # */ 1255 for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { 1256 if (s->vectors[startvec + i].pending && 1257 (attrs.secure || s->itns[startvec + i])) { 1258 val |= (1 << i); 1259 } 1260 } 1261 break; 1262 case 0x300 ... 0x33f: /* NVIC Active */ 1263 val = 0; 1264 startvec = offset - 0x300 + NVIC_FIRST_IRQ; /* vector # */ 1265 1266 for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { 1267 if (s->vectors[startvec + i].active && 1268 (attrs.secure || s->itns[startvec + i])) { 1269 val |= (1 << i); 1270 } 1271 } 1272 break; 1273 case 0x400 ... 0x5ef: /* NVIC Priority */ 1274 val = 0; 1275 startvec = offset - 0x400 + NVIC_FIRST_IRQ; /* vector # */ 1276 1277 for (i = 0; i < size && startvec + i < s->num_irq; i++) { 1278 if (attrs.secure || s->itns[startvec + i]) { 1279 val |= s->vectors[startvec + i].prio << (8 * i); 1280 } 1281 } 1282 break; 1283 case 0xd18 ... 0xd23: /* System Handler Priority (SHPR1, SHPR2, SHPR3) */ 1284 val = 0; 1285 for (i = 0; i < size; i++) { 1286 unsigned hdlidx = (offset - 0xd14) + i; 1287 int sbank = shpr_bank(s, hdlidx, attrs); 1288 1289 if (sbank < 0) { 1290 continue; 1291 } 1292 val = deposit32(val, i * 8, 8, get_prio(s, hdlidx, sbank)); 1293 } 1294 break; 1295 case 0xfe0 ... 0xfff: /* ID. */ 1296 if (offset & 3) { 1297 val = 0; 1298 } else { 1299 val = nvic_id[(offset - 0xfe0) >> 2]; 1300 } 1301 break; 1302 default: 1303 if (size == 4) { 1304 val = nvic_readl(s, offset, attrs); 1305 } else { 1306 qemu_log_mask(LOG_GUEST_ERROR, 1307 "NVIC: Bad read of size %d at offset 0x%x\n", 1308 size, offset); 1309 val = 0; 1310 } 1311 } 1312 1313 trace_nvic_sysreg_read(addr, val, size); 1314 *data = val; 1315 return MEMTX_OK; 1316 } 1317 1318 static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, 1319 uint64_t value, unsigned size, 1320 MemTxAttrs attrs) 1321 { 1322 NVICState *s = (NVICState *)opaque; 1323 uint32_t offset = addr; 1324 unsigned i, startvec, end; 1325 unsigned setval = 0; 1326 1327 trace_nvic_sysreg_write(addr, value, size); 1328 1329 if (attrs.user && !nvic_user_access_ok(s, addr, attrs)) { 1330 /* Generate BusFault for unprivileged accesses */ 1331 return MEMTX_ERROR; 1332 } 1333 1334 switch (offset) { 1335 case 0x100 ... 0x13f: /* NVIC Set enable */ 1336 offset += 0x80; 1337 setval = 1; 1338 /* fall through */ 1339 case 0x180 ... 0x1bf: /* NVIC Clear enable */ 1340 startvec = 8 * (offset - 0x180) + NVIC_FIRST_IRQ; 1341 1342 for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { 1343 if (value & (1 << i) && 1344 (attrs.secure || s->itns[startvec + i])) { 1345 s->vectors[startvec + i].enabled = setval; 1346 } 1347 } 1348 nvic_irq_update(s); 1349 return MEMTX_OK; 1350 case 0x200 ... 0x23f: /* NVIC Set pend */ 1351 /* the special logic in armv7m_nvic_set_pending() 1352 * is not needed since IRQs are never escalated 1353 */ 1354 offset += 0x80; 1355 setval = 1; 1356 /* fall through */ 1357 case 0x280 ... 0x2bf: /* NVIC Clear pend */ 1358 startvec = 8 * (offset - 0x280) + NVIC_FIRST_IRQ; /* vector # */ 1359 1360 for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { 1361 if (value & (1 << i) && 1362 (attrs.secure || s->itns[startvec + i])) { 1363 s->vectors[startvec + i].pending = setval; 1364 } 1365 } 1366 nvic_irq_update(s); 1367 return MEMTX_OK; 1368 case 0x300 ... 0x33f: /* NVIC Active */ 1369 return MEMTX_OK; /* R/O */ 1370 case 0x400 ... 0x5ef: /* NVIC Priority */ 1371 startvec = 8 * (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */ 1372 1373 for (i = 0; i < size && startvec + i < s->num_irq; i++) { 1374 if (attrs.secure || s->itns[startvec + i]) { 1375 set_prio(s, startvec + i, false, (value >> (i * 8)) & 0xff); 1376 } 1377 } 1378 nvic_irq_update(s); 1379 return MEMTX_OK; 1380 case 0xd18 ... 0xd23: /* System Handler Priority (SHPR1, SHPR2, SHPR3) */ 1381 for (i = 0; i < size; i++) { 1382 unsigned hdlidx = (offset - 0xd14) + i; 1383 int newprio = extract32(value, i * 8, 8); 1384 int sbank = shpr_bank(s, hdlidx, attrs); 1385 1386 if (sbank < 0) { 1387 continue; 1388 } 1389 set_prio(s, hdlidx, sbank, newprio); 1390 } 1391 nvic_irq_update(s); 1392 return MEMTX_OK; 1393 } 1394 if (size == 4) { 1395 nvic_writel(s, offset, value, attrs); 1396 return MEMTX_OK; 1397 } 1398 qemu_log_mask(LOG_GUEST_ERROR, 1399 "NVIC: Bad write of size %d at offset 0x%x\n", size, offset); 1400 /* This is UNPREDICTABLE; treat as RAZ/WI */ 1401 return MEMTX_OK; 1402 } 1403 1404 static const MemoryRegionOps nvic_sysreg_ops = { 1405 .read_with_attrs = nvic_sysreg_read, 1406 .write_with_attrs = nvic_sysreg_write, 1407 .endianness = DEVICE_NATIVE_ENDIAN, 1408 }; 1409 1410 static MemTxResult nvic_sysreg_ns_write(void *opaque, hwaddr addr, 1411 uint64_t value, unsigned size, 1412 MemTxAttrs attrs) 1413 { 1414 if (attrs.secure) { 1415 /* S accesses to the alias act like NS accesses to the real region */ 1416 attrs.secure = 0; 1417 return nvic_sysreg_write(opaque, addr, value, size, attrs); 1418 } else { 1419 /* NS attrs are RAZ/WI for privileged, and BusFault for user */ 1420 if (attrs.user) { 1421 return MEMTX_ERROR; 1422 } 1423 return MEMTX_OK; 1424 } 1425 } 1426 1427 static MemTxResult nvic_sysreg_ns_read(void *opaque, hwaddr addr, 1428 uint64_t *data, unsigned size, 1429 MemTxAttrs attrs) 1430 { 1431 if (attrs.secure) { 1432 /* S accesses to the alias act like NS accesses to the real region */ 1433 attrs.secure = 0; 1434 return nvic_sysreg_read(opaque, addr, data, size, attrs); 1435 } else { 1436 /* NS attrs are RAZ/WI for privileged, and BusFault for user */ 1437 if (attrs.user) { 1438 return MEMTX_ERROR; 1439 } 1440 *data = 0; 1441 return MEMTX_OK; 1442 } 1443 } 1444 1445 static const MemoryRegionOps nvic_sysreg_ns_ops = { 1446 .read_with_attrs = nvic_sysreg_ns_read, 1447 .write_with_attrs = nvic_sysreg_ns_write, 1448 .endianness = DEVICE_NATIVE_ENDIAN, 1449 }; 1450 1451 static int nvic_post_load(void *opaque, int version_id) 1452 { 1453 NVICState *s = opaque; 1454 unsigned i; 1455 1456 /* Check for out of range priority settings */ 1457 if (s->vectors[ARMV7M_EXCP_RESET].prio != -3 || 1458 s->vectors[ARMV7M_EXCP_NMI].prio != -2 || 1459 s->vectors[ARMV7M_EXCP_HARD].prio != -1) { 1460 return 1; 1461 } 1462 for (i = ARMV7M_EXCP_MEM; i < s->num_irq; i++) { 1463 if (s->vectors[i].prio & ~0xff) { 1464 return 1; 1465 } 1466 } 1467 1468 nvic_recompute_state(s); 1469 1470 return 0; 1471 } 1472 1473 static const VMStateDescription vmstate_VecInfo = { 1474 .name = "armv7m_nvic_info", 1475 .version_id = 1, 1476 .minimum_version_id = 1, 1477 .fields = (VMStateField[]) { 1478 VMSTATE_INT16(prio, VecInfo), 1479 VMSTATE_UINT8(enabled, VecInfo), 1480 VMSTATE_UINT8(pending, VecInfo), 1481 VMSTATE_UINT8(active, VecInfo), 1482 VMSTATE_UINT8(level, VecInfo), 1483 VMSTATE_END_OF_LIST() 1484 } 1485 }; 1486 1487 static bool nvic_security_needed(void *opaque) 1488 { 1489 NVICState *s = opaque; 1490 1491 return arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY); 1492 } 1493 1494 static int nvic_security_post_load(void *opaque, int version_id) 1495 { 1496 NVICState *s = opaque; 1497 int i; 1498 1499 /* Check for out of range priority settings */ 1500 if (s->sec_vectors[ARMV7M_EXCP_HARD].prio != -1) { 1501 return 1; 1502 } 1503 for (i = ARMV7M_EXCP_MEM; i < ARRAY_SIZE(s->sec_vectors); i++) { 1504 if (s->sec_vectors[i].prio & ~0xff) { 1505 return 1; 1506 } 1507 } 1508 return 0; 1509 } 1510 1511 static const VMStateDescription vmstate_nvic_security = { 1512 .name = "nvic/m-security", 1513 .version_id = 1, 1514 .minimum_version_id = 1, 1515 .needed = nvic_security_needed, 1516 .post_load = &nvic_security_post_load, 1517 .fields = (VMStateField[]) { 1518 VMSTATE_STRUCT_ARRAY(sec_vectors, NVICState, NVIC_INTERNAL_VECTORS, 1, 1519 vmstate_VecInfo, VecInfo), 1520 VMSTATE_UINT32(prigroup[M_REG_S], NVICState), 1521 VMSTATE_BOOL_ARRAY(itns, NVICState, NVIC_MAX_VECTORS), 1522 VMSTATE_END_OF_LIST() 1523 } 1524 }; 1525 1526 static const VMStateDescription vmstate_nvic = { 1527 .name = "armv7m_nvic", 1528 .version_id = 4, 1529 .minimum_version_id = 4, 1530 .post_load = &nvic_post_load, 1531 .fields = (VMStateField[]) { 1532 VMSTATE_STRUCT_ARRAY(vectors, NVICState, NVIC_MAX_VECTORS, 1, 1533 vmstate_VecInfo, VecInfo), 1534 VMSTATE_UINT32(prigroup[M_REG_NS], NVICState), 1535 VMSTATE_END_OF_LIST() 1536 }, 1537 .subsections = (const VMStateDescription*[]) { 1538 &vmstate_nvic_security, 1539 NULL 1540 } 1541 }; 1542 1543 static Property props_nvic[] = { 1544 /* Number of external IRQ lines (so excluding the 16 internal exceptions) */ 1545 DEFINE_PROP_UINT32("num-irq", NVICState, num_irq, 64), 1546 DEFINE_PROP_END_OF_LIST() 1547 }; 1548 1549 static void armv7m_nvic_reset(DeviceState *dev) 1550 { 1551 NVICState *s = NVIC(dev); 1552 1553 s->vectors[ARMV7M_EXCP_NMI].enabled = 1; 1554 s->vectors[ARMV7M_EXCP_HARD].enabled = 1; 1555 /* MEM, BUS, and USAGE are enabled through 1556 * the System Handler Control register 1557 */ 1558 s->vectors[ARMV7M_EXCP_SVC].enabled = 1; 1559 s->vectors[ARMV7M_EXCP_DEBUG].enabled = 1; 1560 s->vectors[ARMV7M_EXCP_PENDSV].enabled = 1; 1561 s->vectors[ARMV7M_EXCP_SYSTICK].enabled = 1; 1562 1563 s->vectors[ARMV7M_EXCP_RESET].prio = -3; 1564 s->vectors[ARMV7M_EXCP_NMI].prio = -2; 1565 s->vectors[ARMV7M_EXCP_HARD].prio = -1; 1566 1567 if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) { 1568 s->sec_vectors[ARMV7M_EXCP_HARD].enabled = 1; 1569 s->sec_vectors[ARMV7M_EXCP_SVC].enabled = 1; 1570 s->sec_vectors[ARMV7M_EXCP_PENDSV].enabled = 1; 1571 s->sec_vectors[ARMV7M_EXCP_SYSTICK].enabled = 1; 1572 1573 /* AIRCR.BFHFNMINS resets to 0 so Secure HF is priority -1 (R_CMTC) */ 1574 s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1; 1575 } 1576 1577 /* Strictly speaking the reset handler should be enabled. 1578 * However, we don't simulate soft resets through the NVIC, 1579 * and the reset vector should never be pended. 1580 * So we leave it disabled to catch logic errors. 1581 */ 1582 1583 s->exception_prio = NVIC_NOEXC_PRIO; 1584 s->vectpending = 0; 1585 s->vectpending_is_s_banked = false; 1586 s->vectpending_prio = NVIC_NOEXC_PRIO; 1587 1588 if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) { 1589 memset(s->itns, 0, sizeof(s->itns)); 1590 } else { 1591 /* This state is constant and not guest accessible in a non-security 1592 * NVIC; we set the bits to true to avoid having to do a feature 1593 * bit check in the NVIC enable/pend/etc register accessors. 1594 */ 1595 int i; 1596 1597 for (i = NVIC_FIRST_IRQ; i < ARRAY_SIZE(s->itns); i++) { 1598 s->itns[i] = true; 1599 } 1600 } 1601 } 1602 1603 static void nvic_systick_trigger(void *opaque, int n, int level) 1604 { 1605 NVICState *s = opaque; 1606 1607 if (level) { 1608 /* SysTick just asked us to pend its exception. 1609 * (This is different from an external interrupt line's 1610 * behaviour.) 1611 * TODO: when we implement the banked systicks we must make 1612 * this pend the correct banked exception. 1613 */ 1614 armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, false); 1615 } 1616 } 1617 1618 static void armv7m_nvic_realize(DeviceState *dev, Error **errp) 1619 { 1620 NVICState *s = NVIC(dev); 1621 SysBusDevice *systick_sbd; 1622 Error *err = NULL; 1623 int regionlen; 1624 1625 s->cpu = ARM_CPU(qemu_get_cpu(0)); 1626 assert(s->cpu); 1627 1628 if (s->num_irq > NVIC_MAX_IRQ) { 1629 error_setg(errp, "num-irq %d exceeds NVIC maximum", s->num_irq); 1630 return; 1631 } 1632 1633 qdev_init_gpio_in(dev, set_irq_level, s->num_irq); 1634 1635 /* include space for internal exception vectors */ 1636 s->num_irq += NVIC_FIRST_IRQ; 1637 1638 object_property_set_bool(OBJECT(&s->systick), true, "realized", &err); 1639 if (err != NULL) { 1640 error_propagate(errp, err); 1641 return; 1642 } 1643 systick_sbd = SYS_BUS_DEVICE(&s->systick); 1644 sysbus_connect_irq(systick_sbd, 0, 1645 qdev_get_gpio_in_named(dev, "systick-trigger", 0)); 1646 1647 /* The NVIC and System Control Space (SCS) starts at 0xe000e000 1648 * and looks like this: 1649 * 0x004 - ICTR 1650 * 0x010 - 0xff - systick 1651 * 0x100..0x7ec - NVIC 1652 * 0x7f0..0xcff - Reserved 1653 * 0xd00..0xd3c - SCS registers 1654 * 0xd40..0xeff - Reserved or Not implemented 1655 * 0xf00 - STIR 1656 * 1657 * Some registers within this space are banked between security states. 1658 * In v8M there is a second range 0xe002e000..0xe002efff which is the 1659 * NonSecure alias SCS; secure accesses to this behave like NS accesses 1660 * to the main SCS range, and non-secure accesses (including when 1661 * the security extension is not implemented) are RAZ/WI. 1662 * Note that both the main SCS range and the alias range are defined 1663 * to be exempt from memory attribution (R_BLJT) and so the memory 1664 * transaction attribute always matches the current CPU security 1665 * state (attrs.secure == env->v7m.secure). In the nvic_sysreg_ns_ops 1666 * wrappers we change attrs.secure to indicate the NS access; so 1667 * generally code determining which banked register to use should 1668 * use attrs.secure; code determining actual behaviour of the system 1669 * should use env->v7m.secure. 1670 */ 1671 regionlen = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? 0x21000 : 0x1000; 1672 memory_region_init(&s->container, OBJECT(s), "nvic", regionlen); 1673 /* The system register region goes at the bottom of the priority 1674 * stack as it covers the whole page. 1675 */ 1676 memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s, 1677 "nvic_sysregs", 0x1000); 1678 memory_region_add_subregion(&s->container, 0, &s->sysregmem); 1679 memory_region_add_subregion_overlap(&s->container, 0x10, 1680 sysbus_mmio_get_region(systick_sbd, 0), 1681 1); 1682 1683 if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) { 1684 memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s), 1685 &nvic_sysreg_ns_ops, s, 1686 "nvic_sysregs_ns", 0x1000); 1687 memory_region_add_subregion(&s->container, 0x20000, &s->sysreg_ns_mem); 1688 } 1689 1690 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container); 1691 } 1692 1693 static void armv7m_nvic_instance_init(Object *obj) 1694 { 1695 /* We have a different default value for the num-irq property 1696 * than our superclass. This function runs after qdev init 1697 * has set the defaults from the Property array and before 1698 * any user-specified property setting, so just modify the 1699 * value in the GICState struct. 1700 */ 1701 DeviceState *dev = DEVICE(obj); 1702 NVICState *nvic = NVIC(obj); 1703 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1704 1705 object_initialize(&nvic->systick, sizeof(nvic->systick), TYPE_SYSTICK); 1706 qdev_set_parent_bus(DEVICE(&nvic->systick), sysbus_get_default()); 1707 1708 sysbus_init_irq(sbd, &nvic->excpout); 1709 qdev_init_gpio_out_named(dev, &nvic->sysresetreq, "SYSRESETREQ", 1); 1710 qdev_init_gpio_in_named(dev, nvic_systick_trigger, "systick-trigger", 1); 1711 } 1712 1713 static void armv7m_nvic_class_init(ObjectClass *klass, void *data) 1714 { 1715 DeviceClass *dc = DEVICE_CLASS(klass); 1716 1717 dc->vmsd = &vmstate_nvic; 1718 dc->props = props_nvic; 1719 dc->reset = armv7m_nvic_reset; 1720 dc->realize = armv7m_nvic_realize; 1721 } 1722 1723 static const TypeInfo armv7m_nvic_info = { 1724 .name = TYPE_NVIC, 1725 .parent = TYPE_SYS_BUS_DEVICE, 1726 .instance_init = armv7m_nvic_instance_init, 1727 .instance_size = sizeof(NVICState), 1728 .class_init = armv7m_nvic_class_init, 1729 .class_size = sizeof(SysBusDeviceClass), 1730 }; 1731 1732 static void armv7m_nvic_register_types(void) 1733 { 1734 type_register_static(&armv7m_nvic_info); 1735 } 1736 1737 type_init(armv7m_nvic_register_types) 1738