xref: /openbmc/qemu/hw/intc/armv7m_nvic.c (revision 49c80c380d665bcc7d5b68ea1ec3617e51a90d73)
1 /*
2  * ARM Nested Vectored Interrupt Controller
3  *
4  * Copyright (c) 2006-2007 CodeSourcery.
5  * Written by Paul Brook
6  *
7  * This code is licensed under the GPL.
8  *
9  * The ARMv7M System controller is fairly tightly tied in with the
10  * NVIC.  Much of that is also implemented here.
11  */
12 
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
15 #include "qemu-common.h"
16 #include "cpu.h"
17 #include "hw/sysbus.h"
18 #include "qemu/timer.h"
19 #include "hw/arm/arm.h"
20 #include "hw/intc/armv7m_nvic.h"
21 #include "target/arm/cpu.h"
22 #include "exec/exec-all.h"
23 #include "qemu/log.h"
24 #include "trace.h"
25 
26 /* IRQ number counting:
27  *
28  * the num-irq property counts the number of external IRQ lines
29  *
30  * NVICState::num_irq counts the total number of exceptions
31  * (external IRQs, the 15 internal exceptions including reset,
32  * and one for the unused exception number 0).
33  *
34  * NVIC_MAX_IRQ is the highest permitted number of external IRQ lines.
35  *
36  * NVIC_MAX_VECTORS is the highest permitted number of exceptions.
37  *
38  * Iterating through all exceptions should typically be done with
39  * for (i = 1; i < s->num_irq; i++) to avoid the unused slot 0.
40  *
41  * The external qemu_irq lines are the NVIC's external IRQ lines,
42  * so line 0 is exception 16.
43  *
44  * In the terminology of the architecture manual, "interrupts" are
45  * a subcategory of exception referring to the external interrupts
46  * (which are exception numbers NVIC_FIRST_IRQ and upward).
47  * For historical reasons QEMU tends to use "interrupt" and
48  * "exception" more or less interchangeably.
49  */
50 #define NVIC_FIRST_IRQ NVIC_INTERNAL_VECTORS
51 #define NVIC_MAX_IRQ (NVIC_MAX_VECTORS - NVIC_FIRST_IRQ)
52 
53 /* Effective running priority of the CPU when no exception is active
54  * (higher than the highest possible priority value)
55  */
56 #define NVIC_NOEXC_PRIO 0x100
57 /* Maximum priority of non-secure exceptions when AIRCR.PRIS is set */
58 #define NVIC_NS_PRIO_LIMIT 0x80
59 
60 static const uint8_t nvic_id[] = {
61     0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
62 };
63 
64 static int nvic_pending_prio(NVICState *s)
65 {
66     /* return the group priority of the current pending interrupt,
67      * or NVIC_NOEXC_PRIO if no interrupt is pending
68      */
69     return s->vectpending_prio;
70 }
71 
72 /* Return the value of the ISCR RETTOBASE bit:
73  * 1 if there is exactly one active exception
74  * 0 if there is more than one active exception
75  * UNKNOWN if there are no active exceptions (we choose 1,
76  * which matches the choice Cortex-M3 is documented as making).
77  *
78  * NB: some versions of the documentation talk about this
79  * counting "active exceptions other than the one shown by IPSR";
80  * this is only different in the obscure corner case where guest
81  * code has manually deactivated an exception and is about
82  * to fail an exception-return integrity check. The definition
83  * above is the one from the v8M ARM ARM and is also in line
84  * with the behaviour documented for the Cortex-M3.
85  */
86 static bool nvic_rettobase(NVICState *s)
87 {
88     int irq, nhand = 0;
89     bool check_sec = arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY);
90 
91     for (irq = ARMV7M_EXCP_RESET; irq < s->num_irq; irq++) {
92         if (s->vectors[irq].active ||
93             (check_sec && irq < NVIC_INTERNAL_VECTORS &&
94              s->sec_vectors[irq].active)) {
95             nhand++;
96             if (nhand == 2) {
97                 return 0;
98             }
99         }
100     }
101 
102     return 1;
103 }
104 
105 /* Return the value of the ISCR ISRPENDING bit:
106  * 1 if an external interrupt is pending
107  * 0 if no external interrupt is pending
108  */
109 static bool nvic_isrpending(NVICState *s)
110 {
111     int irq;
112 
113     /* We can shortcut if the highest priority pending interrupt
114      * happens to be external or if there is nothing pending.
115      */
116     if (s->vectpending > NVIC_FIRST_IRQ) {
117         return true;
118     }
119     if (s->vectpending == 0) {
120         return false;
121     }
122 
123     for (irq = NVIC_FIRST_IRQ; irq < s->num_irq; irq++) {
124         if (s->vectors[irq].pending) {
125             return true;
126         }
127     }
128     return false;
129 }
130 
131 static bool exc_is_banked(int exc)
132 {
133     /* Return true if this is one of the limited set of exceptions which
134      * are banked (and thus have state in sec_vectors[])
135      */
136     return exc == ARMV7M_EXCP_HARD ||
137         exc == ARMV7M_EXCP_MEM ||
138         exc == ARMV7M_EXCP_USAGE ||
139         exc == ARMV7M_EXCP_SVC ||
140         exc == ARMV7M_EXCP_PENDSV ||
141         exc == ARMV7M_EXCP_SYSTICK;
142 }
143 
144 /* Return a mask word which clears the subpriority bits from
145  * a priority value for an M-profile exception, leaving only
146  * the group priority.
147  */
148 static inline uint32_t nvic_gprio_mask(NVICState *s, bool secure)
149 {
150     return ~0U << (s->prigroup[secure] + 1);
151 }
152 
153 static bool exc_targets_secure(NVICState *s, int exc)
154 {
155     /* Return true if this non-banked exception targets Secure state. */
156     if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
157         return false;
158     }
159 
160     if (exc >= NVIC_FIRST_IRQ) {
161         return !s->itns[exc];
162     }
163 
164     /* Function shouldn't be called for banked exceptions. */
165     assert(!exc_is_banked(exc));
166 
167     switch (exc) {
168     case ARMV7M_EXCP_NMI:
169     case ARMV7M_EXCP_BUS:
170         return !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK);
171     case ARMV7M_EXCP_SECURE:
172         return true;
173     case ARMV7M_EXCP_DEBUG:
174         /* TODO: controlled by DEMCR.SDME, which we don't yet implement */
175         return false;
176     default:
177         /* reset, and reserved (unused) low exception numbers.
178          * We'll get called by code that loops through all the exception
179          * numbers, but it doesn't matter what we return here as these
180          * non-existent exceptions will never be pended or active.
181          */
182         return true;
183     }
184 }
185 
186 static int exc_group_prio(NVICState *s, int rawprio, bool targets_secure)
187 {
188     /* Return the group priority for this exception, given its raw
189      * (group-and-subgroup) priority value and whether it is targeting
190      * secure state or not.
191      */
192     if (rawprio < 0) {
193         return rawprio;
194     }
195     rawprio &= nvic_gprio_mask(s, targets_secure);
196     /* AIRCR.PRIS causes us to squash all NS priorities into the
197      * lower half of the total range
198      */
199     if (!targets_secure &&
200         (s->cpu->env.v7m.aircr & R_V7M_AIRCR_PRIS_MASK)) {
201         rawprio = (rawprio >> 1) + NVIC_NS_PRIO_LIMIT;
202     }
203     return rawprio;
204 }
205 
206 /* Recompute vectpending and exception_prio for a CPU which implements
207  * the Security extension
208  */
209 static void nvic_recompute_state_secure(NVICState *s)
210 {
211     int i, bank;
212     int pend_prio = NVIC_NOEXC_PRIO;
213     int active_prio = NVIC_NOEXC_PRIO;
214     int pend_irq = 0;
215     bool pending_is_s_banked = false;
216 
217     /* R_CQRV: precedence is by:
218      *  - lowest group priority; if both the same then
219      *  - lowest subpriority; if both the same then
220      *  - lowest exception number; if both the same (ie banked) then
221      *  - secure exception takes precedence
222      * Compare pseudocode RawExecutionPriority.
223      * Annoyingly, now we have two prigroup values (for S and NS)
224      * we can't do the loop comparison on raw priority values.
225      */
226     for (i = 1; i < s->num_irq; i++) {
227         for (bank = M_REG_S; bank >= M_REG_NS; bank--) {
228             VecInfo *vec;
229             int prio;
230             bool targets_secure;
231 
232             if (bank == M_REG_S) {
233                 if (!exc_is_banked(i)) {
234                     continue;
235                 }
236                 vec = &s->sec_vectors[i];
237                 targets_secure = true;
238             } else {
239                 vec = &s->vectors[i];
240                 targets_secure = !exc_is_banked(i) && exc_targets_secure(s, i);
241             }
242 
243             prio = exc_group_prio(s, vec->prio, targets_secure);
244             if (vec->enabled && vec->pending && prio < pend_prio) {
245                 pend_prio = prio;
246                 pend_irq = i;
247                 pending_is_s_banked = (bank == M_REG_S);
248             }
249             if (vec->active && prio < active_prio) {
250                 active_prio = prio;
251             }
252         }
253     }
254 
255     s->vectpending_is_s_banked = pending_is_s_banked;
256     s->vectpending = pend_irq;
257     s->vectpending_prio = pend_prio;
258     s->exception_prio = active_prio;
259 
260     trace_nvic_recompute_state_secure(s->vectpending,
261                                       s->vectpending_is_s_banked,
262                                       s->vectpending_prio,
263                                       s->exception_prio);
264 }
265 
266 /* Recompute vectpending and exception_prio */
267 static void nvic_recompute_state(NVICState *s)
268 {
269     int i;
270     int pend_prio = NVIC_NOEXC_PRIO;
271     int active_prio = NVIC_NOEXC_PRIO;
272     int pend_irq = 0;
273 
274     /* In theory we could write one function that handled both
275      * the "security extension present" and "not present"; however
276      * the security related changes significantly complicate the
277      * recomputation just by themselves and mixing both cases together
278      * would be even worse, so we retain a separate non-secure-only
279      * version for CPUs which don't implement the security extension.
280      */
281     if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
282         nvic_recompute_state_secure(s);
283         return;
284     }
285 
286     for (i = 1; i < s->num_irq; i++) {
287         VecInfo *vec = &s->vectors[i];
288 
289         if (vec->enabled && vec->pending && vec->prio < pend_prio) {
290             pend_prio = vec->prio;
291             pend_irq = i;
292         }
293         if (vec->active && vec->prio < active_prio) {
294             active_prio = vec->prio;
295         }
296     }
297 
298     if (active_prio > 0) {
299         active_prio &= nvic_gprio_mask(s, false);
300     }
301 
302     if (pend_prio > 0) {
303         pend_prio &= nvic_gprio_mask(s, false);
304     }
305 
306     s->vectpending = pend_irq;
307     s->vectpending_prio = pend_prio;
308     s->exception_prio = active_prio;
309 
310     trace_nvic_recompute_state(s->vectpending,
311                                s->vectpending_prio,
312                                s->exception_prio);
313 }
314 
315 /* Return the current execution priority of the CPU
316  * (equivalent to the pseudocode ExecutionPriority function).
317  * This is a value between -2 (NMI priority) and NVIC_NOEXC_PRIO.
318  */
319 static inline int nvic_exec_prio(NVICState *s)
320 {
321     CPUARMState *env = &s->cpu->env;
322     int running = NVIC_NOEXC_PRIO;
323 
324     if (env->v7m.basepri[M_REG_NS] > 0) {
325         running = exc_group_prio(s, env->v7m.basepri[M_REG_NS], M_REG_NS);
326     }
327 
328     if (env->v7m.basepri[M_REG_S] > 0) {
329         int basepri = exc_group_prio(s, env->v7m.basepri[M_REG_S], M_REG_S);
330         if (running > basepri) {
331             running = basepri;
332         }
333     }
334 
335     if (env->v7m.primask[M_REG_NS]) {
336         if (env->v7m.aircr & R_V7M_AIRCR_PRIS_MASK) {
337             if (running > NVIC_NS_PRIO_LIMIT) {
338                 running = NVIC_NS_PRIO_LIMIT;
339             }
340         } else {
341             running = 0;
342         }
343     }
344 
345     if (env->v7m.primask[M_REG_S]) {
346         running = 0;
347     }
348 
349     if (env->v7m.faultmask[M_REG_NS]) {
350         if (env->v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
351             running = -1;
352         } else {
353             if (env->v7m.aircr & R_V7M_AIRCR_PRIS_MASK) {
354                 if (running > NVIC_NS_PRIO_LIMIT) {
355                     running = NVIC_NS_PRIO_LIMIT;
356                 }
357             } else {
358                 running = 0;
359             }
360         }
361     }
362 
363     if (env->v7m.faultmask[M_REG_S]) {
364         running = (env->v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) ? -3 : -1;
365     }
366 
367     /* consider priority of active handler */
368     return MIN(running, s->exception_prio);
369 }
370 
371 bool armv7m_nvic_can_take_pending_exception(void *opaque)
372 {
373     NVICState *s = opaque;
374 
375     return nvic_exec_prio(s) > nvic_pending_prio(s);
376 }
377 
378 int armv7m_nvic_raw_execution_priority(void *opaque)
379 {
380     NVICState *s = opaque;
381 
382     return s->exception_prio;
383 }
384 
385 /* caller must call nvic_irq_update() after this.
386  * secure indicates the bank to use for banked exceptions (we assert if
387  * we are passed secure=true for a non-banked exception).
388  */
389 static void set_prio(NVICState *s, unsigned irq, bool secure, uint8_t prio)
390 {
391     assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */
392     assert(irq < s->num_irq);
393 
394     if (secure) {
395         assert(exc_is_banked(irq));
396         s->sec_vectors[irq].prio = prio;
397     } else {
398         s->vectors[irq].prio = prio;
399     }
400 
401     trace_nvic_set_prio(irq, secure, prio);
402 }
403 
404 /* Return the current raw priority register value.
405  * secure indicates the bank to use for banked exceptions (we assert if
406  * we are passed secure=true for a non-banked exception).
407  */
408 static int get_prio(NVICState *s, unsigned irq, bool secure)
409 {
410     assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */
411     assert(irq < s->num_irq);
412 
413     if (secure) {
414         assert(exc_is_banked(irq));
415         return s->sec_vectors[irq].prio;
416     } else {
417         return s->vectors[irq].prio;
418     }
419 }
420 
421 /* Recompute state and assert irq line accordingly.
422  * Must be called after changes to:
423  *  vec->active, vec->enabled, vec->pending or vec->prio for any vector
424  *  prigroup
425  */
426 static void nvic_irq_update(NVICState *s)
427 {
428     int lvl;
429     int pend_prio;
430 
431     nvic_recompute_state(s);
432     pend_prio = nvic_pending_prio(s);
433 
434     /* Raise NVIC output if this IRQ would be taken, except that we
435      * ignore the effects of the BASEPRI, FAULTMASK and PRIMASK (which
436      * will be checked for in arm_v7m_cpu_exec_interrupt()); changes
437      * to those CPU registers don't cause us to recalculate the NVIC
438      * pending info.
439      */
440     lvl = (pend_prio < s->exception_prio);
441     trace_nvic_irq_update(s->vectpending, pend_prio, s->exception_prio, lvl);
442     qemu_set_irq(s->excpout, lvl);
443 }
444 
445 /**
446  * armv7m_nvic_clear_pending: mark the specified exception as not pending
447  * @opaque: the NVIC
448  * @irq: the exception number to mark as not pending
449  * @secure: false for non-banked exceptions or for the nonsecure
450  * version of a banked exception, true for the secure version of a banked
451  * exception.
452  *
453  * Marks the specified exception as not pending. Note that we will assert()
454  * if @secure is true and @irq does not specify one of the fixed set
455  * of architecturally banked exceptions.
456  */
457 static void armv7m_nvic_clear_pending(void *opaque, int irq, bool secure)
458 {
459     NVICState *s = (NVICState *)opaque;
460     VecInfo *vec;
461 
462     assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
463 
464     if (secure) {
465         assert(exc_is_banked(irq));
466         vec = &s->sec_vectors[irq];
467     } else {
468         vec = &s->vectors[irq];
469     }
470     trace_nvic_clear_pending(irq, secure, vec->enabled, vec->prio);
471     if (vec->pending) {
472         vec->pending = 0;
473         nvic_irq_update(s);
474     }
475 }
476 
477 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
478 {
479     NVICState *s = (NVICState *)opaque;
480     bool banked = exc_is_banked(irq);
481     VecInfo *vec;
482 
483     assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
484     assert(!secure || banked);
485 
486     vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq];
487 
488     trace_nvic_set_pending(irq, secure, vec->enabled, vec->prio);
489 
490     if (irq >= ARMV7M_EXCP_HARD && irq < ARMV7M_EXCP_PENDSV) {
491         /* If a synchronous exception is pending then it may be
492          * escalated to HardFault if:
493          *  * it is equal or lower priority to current execution
494          *  * it is disabled
495          * (ie we need to take it immediately but we can't do so).
496          * Asynchronous exceptions (and interrupts) simply remain pending.
497          *
498          * For QEMU, we don't have any imprecise (asynchronous) faults,
499          * so we can assume that PREFETCH_ABORT and DATA_ABORT are always
500          * synchronous.
501          * Debug exceptions are awkward because only Debug exceptions
502          * resulting from the BKPT instruction should be escalated,
503          * but we don't currently implement any Debug exceptions other
504          * than those that result from BKPT, so we treat all debug exceptions
505          * as needing escalation.
506          *
507          * This all means we can identify whether to escalate based only on
508          * the exception number and don't (yet) need the caller to explicitly
509          * tell us whether this exception is synchronous or not.
510          */
511         int running = nvic_exec_prio(s);
512         bool escalate = false;
513 
514         if (exc_group_prio(s, vec->prio, secure) >= running) {
515             trace_nvic_escalate_prio(irq, vec->prio, running);
516             escalate = true;
517         } else if (!vec->enabled) {
518             trace_nvic_escalate_disabled(irq);
519             escalate = true;
520         }
521 
522         if (escalate) {
523 
524             /* We need to escalate this exception to a synchronous HardFault.
525              * If BFHFNMINS is set then we escalate to the banked HF for
526              * the target security state of the original exception; otherwise
527              * we take a Secure HardFault.
528              */
529             irq = ARMV7M_EXCP_HARD;
530             if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) &&
531                 (secure ||
532                  !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK))) {
533                 vec = &s->sec_vectors[irq];
534             } else {
535                 vec = &s->vectors[irq];
536             }
537             if (running <= vec->prio) {
538                 /* We want to escalate to HardFault but we can't take the
539                  * synchronous HardFault at this point either. This is a
540                  * Lockup condition due to a guest bug. We don't model
541                  * Lockup, so report via cpu_abort() instead.
542                  */
543                 cpu_abort(&s->cpu->parent_obj,
544                           "Lockup: can't escalate %d to HardFault "
545                           "(current priority %d)\n", irq, running);
546             }
547 
548             /* HF may be banked but there is only one shared HFSR */
549             s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK;
550         }
551     }
552 
553     if (!vec->pending) {
554         vec->pending = 1;
555         nvic_irq_update(s);
556     }
557 }
558 
559 /* Make pending IRQ active.  */
560 void armv7m_nvic_acknowledge_irq(void *opaque)
561 {
562     NVICState *s = (NVICState *)opaque;
563     CPUARMState *env = &s->cpu->env;
564     const int pending = s->vectpending;
565     const int running = nvic_exec_prio(s);
566     VecInfo *vec;
567 
568     assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq);
569 
570     vec = &s->vectors[pending];
571 
572     assert(vec->enabled);
573     assert(vec->pending);
574 
575     assert(s->vectpending_prio < running);
576 
577     trace_nvic_acknowledge_irq(pending, s->vectpending_prio);
578 
579     vec->active = 1;
580     vec->pending = 0;
581 
582     env->v7m.exception = s->vectpending;
583 
584     nvic_irq_update(s);
585 }
586 
587 int armv7m_nvic_complete_irq(void *opaque, int irq)
588 {
589     NVICState *s = (NVICState *)opaque;
590     VecInfo *vec;
591     int ret;
592 
593     assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
594 
595     vec = &s->vectors[irq];
596 
597     trace_nvic_complete_irq(irq);
598 
599     if (!vec->active) {
600         /* Tell the caller this was an illegal exception return */
601         return -1;
602     }
603 
604     ret = nvic_rettobase(s);
605 
606     vec->active = 0;
607     if (vec->level) {
608         /* Re-pend the exception if it's still held high; only
609          * happens for extenal IRQs
610          */
611         assert(irq >= NVIC_FIRST_IRQ);
612         vec->pending = 1;
613     }
614 
615     nvic_irq_update(s);
616 
617     return ret;
618 }
619 
620 /* callback when external interrupt line is changed */
621 static void set_irq_level(void *opaque, int n, int level)
622 {
623     NVICState *s = opaque;
624     VecInfo *vec;
625 
626     n += NVIC_FIRST_IRQ;
627 
628     assert(n >= NVIC_FIRST_IRQ && n < s->num_irq);
629 
630     trace_nvic_set_irq_level(n, level);
631 
632     /* The pending status of an external interrupt is
633      * latched on rising edge and exception handler return.
634      *
635      * Pulsing the IRQ will always run the handler
636      * once, and the handler will re-run until the
637      * level is low when the handler completes.
638      */
639     vec = &s->vectors[n];
640     if (level != vec->level) {
641         vec->level = level;
642         if (level) {
643             armv7m_nvic_set_pending(s, n, false);
644         }
645     }
646 }
647 
648 static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
649 {
650     ARMCPU *cpu = s->cpu;
651     uint32_t val;
652 
653     switch (offset) {
654     case 4: /* Interrupt Control Type.  */
655         return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1;
656     case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
657     {
658         int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ;
659         int i;
660 
661         if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
662             goto bad_offset;
663         }
664         if (!attrs.secure) {
665             return 0;
666         }
667         val = 0;
668         for (i = 0; i < 32 && startvec + i < s->num_irq; i++) {
669             if (s->itns[startvec + i]) {
670                 val |= (1 << i);
671             }
672         }
673         return val;
674     }
675     case 0xd00: /* CPUID Base.  */
676         return cpu->midr;
677     case 0xd04: /* Interrupt Control State.  */
678         /* VECTACTIVE */
679         val = cpu->env.v7m.exception;
680         /* VECTPENDING */
681         val |= (s->vectpending & 0xff) << 12;
682         /* ISRPENDING - set if any external IRQ is pending */
683         if (nvic_isrpending(s)) {
684             val |= (1 << 22);
685         }
686         /* RETTOBASE - set if only one handler is active */
687         if (nvic_rettobase(s)) {
688             val |= (1 << 11);
689         }
690         /* PENDSTSET */
691         if (s->vectors[ARMV7M_EXCP_SYSTICK].pending) {
692             val |= (1 << 26);
693         }
694         /* PENDSVSET */
695         if (s->vectors[ARMV7M_EXCP_PENDSV].pending) {
696             val |= (1 << 28);
697         }
698         /* NMIPENDSET */
699         if (s->vectors[ARMV7M_EXCP_NMI].pending) {
700             val |= (1 << 31);
701         }
702         /* ISRPREEMPT not implemented */
703         return val;
704     case 0xd08: /* Vector Table Offset.  */
705         return cpu->env.v7m.vecbase[attrs.secure];
706     case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */
707         val = 0xfa050000 | (s->prigroup[attrs.secure] << 8);
708         if (attrs.secure) {
709             /* s->aircr stores PRIS, BFHFNMINS, SYSRESETREQS */
710             val |= cpu->env.v7m.aircr;
711         } else {
712             if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
713                 /* BFHFNMINS is R/O from NS; other bits are RAZ/WI. If
714                  * security isn't supported then BFHFNMINS is RAO (and
715                  * the bit in env.v7m.aircr is always set).
716                  */
717                 val |= cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK;
718             }
719         }
720         return val;
721     case 0xd10: /* System Control.  */
722         /* TODO: Implement SLEEPONEXIT.  */
723         return 0;
724     case 0xd14: /* Configuration Control.  */
725         /* The BFHFNMIGN bit is the only non-banked bit; we
726          * keep it in the non-secure copy of the register.
727          */
728         val = cpu->env.v7m.ccr[attrs.secure];
729         val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK;
730         return val;
731     case 0xd24: /* System Handler Status.  */
732         val = 0;
733         if (s->vectors[ARMV7M_EXCP_MEM].active) {
734             val |= (1 << 0);
735         }
736         if (s->vectors[ARMV7M_EXCP_BUS].active) {
737             val |= (1 << 1);
738         }
739         if (s->vectors[ARMV7M_EXCP_USAGE].active) {
740             val |= (1 << 3);
741         }
742         if (s->vectors[ARMV7M_EXCP_SVC].active) {
743             val |= (1 << 7);
744         }
745         if (s->vectors[ARMV7M_EXCP_DEBUG].active) {
746             val |= (1 << 8);
747         }
748         if (s->vectors[ARMV7M_EXCP_PENDSV].active) {
749             val |= (1 << 10);
750         }
751         if (s->vectors[ARMV7M_EXCP_SYSTICK].active) {
752             val |= (1 << 11);
753         }
754         if (s->vectors[ARMV7M_EXCP_USAGE].pending) {
755             val |= (1 << 12);
756         }
757         if (s->vectors[ARMV7M_EXCP_MEM].pending) {
758             val |= (1 << 13);
759         }
760         if (s->vectors[ARMV7M_EXCP_BUS].pending) {
761             val |= (1 << 14);
762         }
763         if (s->vectors[ARMV7M_EXCP_SVC].pending) {
764             val |= (1 << 15);
765         }
766         if (s->vectors[ARMV7M_EXCP_MEM].enabled) {
767             val |= (1 << 16);
768         }
769         if (s->vectors[ARMV7M_EXCP_BUS].enabled) {
770             val |= (1 << 17);
771         }
772         if (s->vectors[ARMV7M_EXCP_USAGE].enabled) {
773             val |= (1 << 18);
774         }
775         return val;
776     case 0xd28: /* Configurable Fault Status.  */
777         /* The BFSR bits [15:8] are shared between security states
778          * and we store them in the NS copy
779          */
780         val = cpu->env.v7m.cfsr[attrs.secure];
781         val |= cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK;
782         return val;
783     case 0xd2c: /* Hard Fault Status.  */
784         return cpu->env.v7m.hfsr;
785     case 0xd30: /* Debug Fault Status.  */
786         return cpu->env.v7m.dfsr;
787     case 0xd34: /* MMFAR MemManage Fault Address */
788         return cpu->env.v7m.mmfar[attrs.secure];
789     case 0xd38: /* Bus Fault Address.  */
790         return cpu->env.v7m.bfar;
791     case 0xd3c: /* Aux Fault Status.  */
792         /* TODO: Implement fault status registers.  */
793         qemu_log_mask(LOG_UNIMP,
794                       "Aux Fault status registers unimplemented\n");
795         return 0;
796     case 0xd40: /* PFR0.  */
797         return 0x00000030;
798     case 0xd44: /* PRF1.  */
799         return 0x00000200;
800     case 0xd48: /* DFR0.  */
801         return 0x00100000;
802     case 0xd4c: /* AFR0.  */
803         return 0x00000000;
804     case 0xd50: /* MMFR0.  */
805         return 0x00000030;
806     case 0xd54: /* MMFR1.  */
807         return 0x00000000;
808     case 0xd58: /* MMFR2.  */
809         return 0x00000000;
810     case 0xd5c: /* MMFR3.  */
811         return 0x00000000;
812     case 0xd60: /* ISAR0.  */
813         return 0x01141110;
814     case 0xd64: /* ISAR1.  */
815         return 0x02111000;
816     case 0xd68: /* ISAR2.  */
817         return 0x21112231;
818     case 0xd6c: /* ISAR3.  */
819         return 0x01111110;
820     case 0xd70: /* ISAR4.  */
821         return 0x01310102;
822     /* TODO: Implement debug registers.  */
823     case 0xd90: /* MPU_TYPE */
824         /* Unified MPU; if the MPU is not present this value is zero */
825         return cpu->pmsav7_dregion << 8;
826         break;
827     case 0xd94: /* MPU_CTRL */
828         return cpu->env.v7m.mpu_ctrl[attrs.secure];
829     case 0xd98: /* MPU_RNR */
830         return cpu->env.pmsav7.rnr[attrs.secure];
831     case 0xd9c: /* MPU_RBAR */
832     case 0xda4: /* MPU_RBAR_A1 */
833     case 0xdac: /* MPU_RBAR_A2 */
834     case 0xdb4: /* MPU_RBAR_A3 */
835     {
836         int region = cpu->env.pmsav7.rnr[attrs.secure];
837 
838         if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
839             /* PMSAv8M handling of the aliases is different from v7M:
840              * aliases A1, A2, A3 override the low two bits of the region
841              * number in MPU_RNR, and there is no 'region' field in the
842              * RBAR register.
843              */
844             int aliasno = (offset - 0xd9c) / 8; /* 0..3 */
845             if (aliasno) {
846                 region = deposit32(region, 0, 2, aliasno);
847             }
848             if (region >= cpu->pmsav7_dregion) {
849                 return 0;
850             }
851             return cpu->env.pmsav8.rbar[attrs.secure][region];
852         }
853 
854         if (region >= cpu->pmsav7_dregion) {
855             return 0;
856         }
857         return (cpu->env.pmsav7.drbar[region] & 0x1f) | (region & 0xf);
858     }
859     case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */
860     case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */
861     case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */
862     case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */
863     {
864         int region = cpu->env.pmsav7.rnr[attrs.secure];
865 
866         if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
867             /* PMSAv8M handling of the aliases is different from v7M:
868              * aliases A1, A2, A3 override the low two bits of the region
869              * number in MPU_RNR.
870              */
871             int aliasno = (offset - 0xda0) / 8; /* 0..3 */
872             if (aliasno) {
873                 region = deposit32(region, 0, 2, aliasno);
874             }
875             if (region >= cpu->pmsav7_dregion) {
876                 return 0;
877             }
878             return cpu->env.pmsav8.rlar[attrs.secure][region];
879         }
880 
881         if (region >= cpu->pmsav7_dregion) {
882             return 0;
883         }
884         return ((cpu->env.pmsav7.dracr[region] & 0xffff) << 16) |
885             (cpu->env.pmsav7.drsr[region] & 0xffff);
886     }
887     case 0xdc0: /* MPU_MAIR0 */
888         if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
889             goto bad_offset;
890         }
891         return cpu->env.pmsav8.mair0[attrs.secure];
892     case 0xdc4: /* MPU_MAIR1 */
893         if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
894             goto bad_offset;
895         }
896         return cpu->env.pmsav8.mair1[attrs.secure];
897     default:
898     bad_offset:
899         qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset);
900         return 0;
901     }
902 }
903 
904 static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
905                         MemTxAttrs attrs)
906 {
907     ARMCPU *cpu = s->cpu;
908 
909     switch (offset) {
910     case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
911     {
912         int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ;
913         int i;
914 
915         if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
916             goto bad_offset;
917         }
918         if (!attrs.secure) {
919             break;
920         }
921         for (i = 0; i < 32 && startvec + i < s->num_irq; i++) {
922             s->itns[startvec + i] = (value >> i) & 1;
923         }
924         nvic_irq_update(s);
925         break;
926     }
927     case 0xd04: /* Interrupt Control State.  */
928         if (value & (1 << 31)) {
929             armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false);
930         }
931         if (value & (1 << 28)) {
932             armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure);
933         } else if (value & (1 << 27)) {
934             armv7m_nvic_clear_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure);
935         }
936         if (value & (1 << 26)) {
937             armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, attrs.secure);
938         } else if (value & (1 << 25)) {
939             armv7m_nvic_clear_pending(s, ARMV7M_EXCP_SYSTICK, attrs.secure);
940         }
941         break;
942     case 0xd08: /* Vector Table Offset.  */
943         cpu->env.v7m.vecbase[attrs.secure] = value & 0xffffff80;
944         break;
945     case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */
946         if ((value >> R_V7M_AIRCR_VECTKEY_SHIFT) == 0x05fa) {
947             if (value & R_V7M_AIRCR_SYSRESETREQ_MASK) {
948                 if (attrs.secure ||
949                     !(cpu->env.v7m.aircr & R_V7M_AIRCR_SYSRESETREQS_MASK)) {
950                     qemu_irq_pulse(s->sysresetreq);
951                 }
952             }
953             if (value & R_V7M_AIRCR_VECTCLRACTIVE_MASK) {
954                 qemu_log_mask(LOG_GUEST_ERROR,
955                               "Setting VECTCLRACTIVE when not in DEBUG mode "
956                               "is UNPREDICTABLE\n");
957             }
958             if (value & R_V7M_AIRCR_VECTRESET_MASK) {
959                 /* NB: this bit is RES0 in v8M */
960                 qemu_log_mask(LOG_GUEST_ERROR,
961                               "Setting VECTRESET when not in DEBUG mode "
962                               "is UNPREDICTABLE\n");
963             }
964             s->prigroup[attrs.secure] = extract32(value,
965                                                   R_V7M_AIRCR_PRIGROUP_SHIFT,
966                                                   R_V7M_AIRCR_PRIGROUP_LENGTH);
967             if (attrs.secure) {
968                 /* These bits are only writable by secure */
969                 cpu->env.v7m.aircr = value &
970                     (R_V7M_AIRCR_SYSRESETREQS_MASK |
971                      R_V7M_AIRCR_BFHFNMINS_MASK |
972                      R_V7M_AIRCR_PRIS_MASK);
973                 /* BFHFNMINS changes the priority of Secure HardFault, and
974                  * allows a pending Non-secure HardFault to preempt (which
975                  * we implement by marking it enabled).
976                  */
977                 if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
978                     s->sec_vectors[ARMV7M_EXCP_HARD].prio = -3;
979                     s->vectors[ARMV7M_EXCP_HARD].enabled = 1;
980                 } else {
981                     s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;
982                     s->vectors[ARMV7M_EXCP_HARD].enabled = 0;
983                 }
984             }
985             nvic_irq_update(s);
986         }
987         break;
988     case 0xd10: /* System Control.  */
989         /* TODO: Implement control registers.  */
990         qemu_log_mask(LOG_UNIMP, "NVIC: SCR unimplemented\n");
991         break;
992     case 0xd14: /* Configuration Control.  */
993         /* Enforce RAZ/WI on reserved and must-RAZ/WI bits */
994         value &= (R_V7M_CCR_STKALIGN_MASK |
995                   R_V7M_CCR_BFHFNMIGN_MASK |
996                   R_V7M_CCR_DIV_0_TRP_MASK |
997                   R_V7M_CCR_UNALIGN_TRP_MASK |
998                   R_V7M_CCR_USERSETMPEND_MASK |
999                   R_V7M_CCR_NONBASETHRDENA_MASK);
1000 
1001         if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1002             /* v8M makes NONBASETHRDENA and STKALIGN be RES1 */
1003             value |= R_V7M_CCR_NONBASETHRDENA_MASK
1004                 | R_V7M_CCR_STKALIGN_MASK;
1005         }
1006         if (attrs.secure) {
1007             /* the BFHFNMIGN bit is not banked; keep that in the NS copy */
1008             cpu->env.v7m.ccr[M_REG_NS] =
1009                 (cpu->env.v7m.ccr[M_REG_NS] & ~R_V7M_CCR_BFHFNMIGN_MASK)
1010                 | (value & R_V7M_CCR_BFHFNMIGN_MASK);
1011             value &= ~R_V7M_CCR_BFHFNMIGN_MASK;
1012         }
1013 
1014         cpu->env.v7m.ccr[attrs.secure] = value;
1015         break;
1016     case 0xd24: /* System Handler Control.  */
1017         s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;
1018         s->vectors[ARMV7M_EXCP_BUS].active = (value & (1 << 1)) != 0;
1019         s->vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0;
1020         s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;
1021         s->vectors[ARMV7M_EXCP_DEBUG].active = (value & (1 << 8)) != 0;
1022         s->vectors[ARMV7M_EXCP_PENDSV].active = (value & (1 << 10)) != 0;
1023         s->vectors[ARMV7M_EXCP_SYSTICK].active = (value & (1 << 11)) != 0;
1024         s->vectors[ARMV7M_EXCP_USAGE].pending = (value & (1 << 12)) != 0;
1025         s->vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0;
1026         s->vectors[ARMV7M_EXCP_BUS].pending = (value & (1 << 14)) != 0;
1027         s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;
1028         s->vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
1029         s->vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
1030         s->vectors[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;
1031         nvic_irq_update(s);
1032         break;
1033     case 0xd28: /* Configurable Fault Status.  */
1034         cpu->env.v7m.cfsr[attrs.secure] &= ~value; /* W1C */
1035         if (attrs.secure) {
1036             /* The BFSR bits [15:8] are shared between security states
1037              * and we store them in the NS copy.
1038              */
1039             cpu->env.v7m.cfsr[M_REG_NS] &= ~(value & R_V7M_CFSR_BFSR_MASK);
1040         }
1041         break;
1042     case 0xd2c: /* Hard Fault Status.  */
1043         cpu->env.v7m.hfsr &= ~value; /* W1C */
1044         break;
1045     case 0xd30: /* Debug Fault Status.  */
1046         cpu->env.v7m.dfsr &= ~value; /* W1C */
1047         break;
1048     case 0xd34: /* Mem Manage Address.  */
1049         cpu->env.v7m.mmfar[attrs.secure] = value;
1050         return;
1051     case 0xd38: /* Bus Fault Address.  */
1052         cpu->env.v7m.bfar = value;
1053         return;
1054     case 0xd3c: /* Aux Fault Status.  */
1055         qemu_log_mask(LOG_UNIMP,
1056                       "NVIC: Aux fault status registers unimplemented\n");
1057         break;
1058     case 0xd90: /* MPU_TYPE */
1059         return; /* RO */
1060     case 0xd94: /* MPU_CTRL */
1061         if ((value &
1062              (R_V7M_MPU_CTRL_HFNMIENA_MASK | R_V7M_MPU_CTRL_ENABLE_MASK))
1063             == R_V7M_MPU_CTRL_HFNMIENA_MASK) {
1064             qemu_log_mask(LOG_GUEST_ERROR, "MPU_CTRL: HFNMIENA and !ENABLE is "
1065                           "UNPREDICTABLE\n");
1066         }
1067         cpu->env.v7m.mpu_ctrl[attrs.secure]
1068             = value & (R_V7M_MPU_CTRL_ENABLE_MASK |
1069                        R_V7M_MPU_CTRL_HFNMIENA_MASK |
1070                        R_V7M_MPU_CTRL_PRIVDEFENA_MASK);
1071         tlb_flush(CPU(cpu));
1072         break;
1073     case 0xd98: /* MPU_RNR */
1074         if (value >= cpu->pmsav7_dregion) {
1075             qemu_log_mask(LOG_GUEST_ERROR, "MPU region out of range %"
1076                           PRIu32 "/%" PRIu32 "\n",
1077                           value, cpu->pmsav7_dregion);
1078         } else {
1079             cpu->env.pmsav7.rnr[attrs.secure] = value;
1080         }
1081         break;
1082     case 0xd9c: /* MPU_RBAR */
1083     case 0xda4: /* MPU_RBAR_A1 */
1084     case 0xdac: /* MPU_RBAR_A2 */
1085     case 0xdb4: /* MPU_RBAR_A3 */
1086     {
1087         int region;
1088 
1089         if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1090             /* PMSAv8M handling of the aliases is different from v7M:
1091              * aliases A1, A2, A3 override the low two bits of the region
1092              * number in MPU_RNR, and there is no 'region' field in the
1093              * RBAR register.
1094              */
1095             int aliasno = (offset - 0xd9c) / 8; /* 0..3 */
1096 
1097             region = cpu->env.pmsav7.rnr[attrs.secure];
1098             if (aliasno) {
1099                 region = deposit32(region, 0, 2, aliasno);
1100             }
1101             if (region >= cpu->pmsav7_dregion) {
1102                 return;
1103             }
1104             cpu->env.pmsav8.rbar[attrs.secure][region] = value;
1105             tlb_flush(CPU(cpu));
1106             return;
1107         }
1108 
1109         if (value & (1 << 4)) {
1110             /* VALID bit means use the region number specified in this
1111              * value and also update MPU_RNR.REGION with that value.
1112              */
1113             region = extract32(value, 0, 4);
1114             if (region >= cpu->pmsav7_dregion) {
1115                 qemu_log_mask(LOG_GUEST_ERROR,
1116                               "MPU region out of range %u/%" PRIu32 "\n",
1117                               region, cpu->pmsav7_dregion);
1118                 return;
1119             }
1120             cpu->env.pmsav7.rnr[attrs.secure] = region;
1121         } else {
1122             region = cpu->env.pmsav7.rnr[attrs.secure];
1123         }
1124 
1125         if (region >= cpu->pmsav7_dregion) {
1126             return;
1127         }
1128 
1129         cpu->env.pmsav7.drbar[region] = value & ~0x1f;
1130         tlb_flush(CPU(cpu));
1131         break;
1132     }
1133     case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */
1134     case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */
1135     case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */
1136     case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */
1137     {
1138         int region = cpu->env.pmsav7.rnr[attrs.secure];
1139 
1140         if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1141             /* PMSAv8M handling of the aliases is different from v7M:
1142              * aliases A1, A2, A3 override the low two bits of the region
1143              * number in MPU_RNR.
1144              */
1145             int aliasno = (offset - 0xd9c) / 8; /* 0..3 */
1146 
1147             region = cpu->env.pmsav7.rnr[attrs.secure];
1148             if (aliasno) {
1149                 region = deposit32(region, 0, 2, aliasno);
1150             }
1151             if (region >= cpu->pmsav7_dregion) {
1152                 return;
1153             }
1154             cpu->env.pmsav8.rlar[attrs.secure][region] = value;
1155             tlb_flush(CPU(cpu));
1156             return;
1157         }
1158 
1159         if (region >= cpu->pmsav7_dregion) {
1160             return;
1161         }
1162 
1163         cpu->env.pmsav7.drsr[region] = value & 0xff3f;
1164         cpu->env.pmsav7.dracr[region] = (value >> 16) & 0x173f;
1165         tlb_flush(CPU(cpu));
1166         break;
1167     }
1168     case 0xdc0: /* MPU_MAIR0 */
1169         if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1170             goto bad_offset;
1171         }
1172         if (cpu->pmsav7_dregion) {
1173             /* Register is RES0 if no MPU regions are implemented */
1174             cpu->env.pmsav8.mair0[attrs.secure] = value;
1175         }
1176         /* We don't need to do anything else because memory attributes
1177          * only affect cacheability, and we don't implement caching.
1178          */
1179         break;
1180     case 0xdc4: /* MPU_MAIR1 */
1181         if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1182             goto bad_offset;
1183         }
1184         if (cpu->pmsav7_dregion) {
1185             /* Register is RES0 if no MPU regions are implemented */
1186             cpu->env.pmsav8.mair1[attrs.secure] = value;
1187         }
1188         /* We don't need to do anything else because memory attributes
1189          * only affect cacheability, and we don't implement caching.
1190          */
1191         break;
1192     case 0xf00: /* Software Triggered Interrupt Register */
1193     {
1194         int excnum = (value & 0x1ff) + NVIC_FIRST_IRQ;
1195         if (excnum < s->num_irq) {
1196             armv7m_nvic_set_pending(s, excnum, false);
1197         }
1198         break;
1199     }
1200     default:
1201     bad_offset:
1202         qemu_log_mask(LOG_GUEST_ERROR,
1203                       "NVIC: Bad write offset 0x%x\n", offset);
1204     }
1205 }
1206 
1207 static bool nvic_user_access_ok(NVICState *s, hwaddr offset, MemTxAttrs attrs)
1208 {
1209     /* Return true if unprivileged access to this register is permitted. */
1210     switch (offset) {
1211     case 0xf00: /* STIR: accessible only if CCR.USERSETMPEND permits */
1212         /* For access via STIR_NS it is the NS CCR.USERSETMPEND that
1213          * controls access even though the CPU is in Secure state (I_QDKX).
1214          */
1215         return s->cpu->env.v7m.ccr[attrs.secure] & R_V7M_CCR_USERSETMPEND_MASK;
1216     default:
1217         /* All other user accesses cause a BusFault unconditionally */
1218         return false;
1219     }
1220 }
1221 
1222 static int shpr_bank(NVICState *s, int exc, MemTxAttrs attrs)
1223 {
1224     /* Behaviour for the SHPR register field for this exception:
1225      * return M_REG_NS to use the nonsecure vector (including for
1226      * non-banked exceptions), M_REG_S for the secure version of
1227      * a banked exception, and -1 if this field should RAZ/WI.
1228      */
1229     switch (exc) {
1230     case ARMV7M_EXCP_MEM:
1231     case ARMV7M_EXCP_USAGE:
1232     case ARMV7M_EXCP_SVC:
1233     case ARMV7M_EXCP_PENDSV:
1234     case ARMV7M_EXCP_SYSTICK:
1235         /* Banked exceptions */
1236         return attrs.secure;
1237     case ARMV7M_EXCP_BUS:
1238         /* Not banked, RAZ/WI from nonsecure if BFHFNMINS is zero */
1239         if (!attrs.secure &&
1240             !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
1241             return -1;
1242         }
1243         return M_REG_NS;
1244     case ARMV7M_EXCP_SECURE:
1245         /* Not banked, RAZ/WI from nonsecure */
1246         if (!attrs.secure) {
1247             return -1;
1248         }
1249         return M_REG_NS;
1250     case ARMV7M_EXCP_DEBUG:
1251         /* Not banked. TODO should RAZ/WI if DEMCR.SDME is set */
1252         return M_REG_NS;
1253     case 8 ... 10:
1254     case 13:
1255         /* RES0 */
1256         return -1;
1257     default:
1258         /* Not reachable due to decode of SHPR register addresses */
1259         g_assert_not_reached();
1260     }
1261 }
1262 
1263 static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
1264                                     uint64_t *data, unsigned size,
1265                                     MemTxAttrs attrs)
1266 {
1267     NVICState *s = (NVICState *)opaque;
1268     uint32_t offset = addr;
1269     unsigned i, startvec, end;
1270     uint32_t val;
1271 
1272     if (attrs.user && !nvic_user_access_ok(s, addr, attrs)) {
1273         /* Generate BusFault for unprivileged accesses */
1274         return MEMTX_ERROR;
1275     }
1276 
1277     switch (offset) {
1278     /* reads of set and clear both return the status */
1279     case 0x100 ... 0x13f: /* NVIC Set enable */
1280         offset += 0x80;
1281         /* fall through */
1282     case 0x180 ... 0x1bf: /* NVIC Clear enable */
1283         val = 0;
1284         startvec = offset - 0x180 + NVIC_FIRST_IRQ; /* vector # */
1285 
1286         for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
1287             if (s->vectors[startvec + i].enabled &&
1288                 (attrs.secure || s->itns[startvec + i])) {
1289                 val |= (1 << i);
1290             }
1291         }
1292         break;
1293     case 0x200 ... 0x23f: /* NVIC Set pend */
1294         offset += 0x80;
1295         /* fall through */
1296     case 0x280 ... 0x2bf: /* NVIC Clear pend */
1297         val = 0;
1298         startvec = offset - 0x280 + NVIC_FIRST_IRQ; /* vector # */
1299         for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
1300             if (s->vectors[startvec + i].pending &&
1301                 (attrs.secure || s->itns[startvec + i])) {
1302                 val |= (1 << i);
1303             }
1304         }
1305         break;
1306     case 0x300 ... 0x33f: /* NVIC Active */
1307         val = 0;
1308         startvec = offset - 0x300 + NVIC_FIRST_IRQ; /* vector # */
1309 
1310         for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
1311             if (s->vectors[startvec + i].active &&
1312                 (attrs.secure || s->itns[startvec + i])) {
1313                 val |= (1 << i);
1314             }
1315         }
1316         break;
1317     case 0x400 ... 0x5ef: /* NVIC Priority */
1318         val = 0;
1319         startvec = offset - 0x400 + NVIC_FIRST_IRQ; /* vector # */
1320 
1321         for (i = 0; i < size && startvec + i < s->num_irq; i++) {
1322             if (attrs.secure || s->itns[startvec + i]) {
1323                 val |= s->vectors[startvec + i].prio << (8 * i);
1324             }
1325         }
1326         break;
1327     case 0xd18 ... 0xd23: /* System Handler Priority (SHPR1, SHPR2, SHPR3) */
1328         val = 0;
1329         for (i = 0; i < size; i++) {
1330             unsigned hdlidx = (offset - 0xd14) + i;
1331             int sbank = shpr_bank(s, hdlidx, attrs);
1332 
1333             if (sbank < 0) {
1334                 continue;
1335             }
1336             val = deposit32(val, i * 8, 8, get_prio(s, hdlidx, sbank));
1337         }
1338         break;
1339     case 0xfe0 ... 0xfff: /* ID.  */
1340         if (offset & 3) {
1341             val = 0;
1342         } else {
1343             val = nvic_id[(offset - 0xfe0) >> 2];
1344         }
1345         break;
1346     default:
1347         if (size == 4) {
1348             val = nvic_readl(s, offset, attrs);
1349         } else {
1350             qemu_log_mask(LOG_GUEST_ERROR,
1351                           "NVIC: Bad read of size %d at offset 0x%x\n",
1352                           size, offset);
1353             val = 0;
1354         }
1355     }
1356 
1357     trace_nvic_sysreg_read(addr, val, size);
1358     *data = val;
1359     return MEMTX_OK;
1360 }
1361 
1362 static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
1363                                      uint64_t value, unsigned size,
1364                                      MemTxAttrs attrs)
1365 {
1366     NVICState *s = (NVICState *)opaque;
1367     uint32_t offset = addr;
1368     unsigned i, startvec, end;
1369     unsigned setval = 0;
1370 
1371     trace_nvic_sysreg_write(addr, value, size);
1372 
1373     if (attrs.user && !nvic_user_access_ok(s, addr, attrs)) {
1374         /* Generate BusFault for unprivileged accesses */
1375         return MEMTX_ERROR;
1376     }
1377 
1378     switch (offset) {
1379     case 0x100 ... 0x13f: /* NVIC Set enable */
1380         offset += 0x80;
1381         setval = 1;
1382         /* fall through */
1383     case 0x180 ... 0x1bf: /* NVIC Clear enable */
1384         startvec = 8 * (offset - 0x180) + NVIC_FIRST_IRQ;
1385 
1386         for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
1387             if (value & (1 << i) &&
1388                 (attrs.secure || s->itns[startvec + i])) {
1389                 s->vectors[startvec + i].enabled = setval;
1390             }
1391         }
1392         nvic_irq_update(s);
1393         return MEMTX_OK;
1394     case 0x200 ... 0x23f: /* NVIC Set pend */
1395         /* the special logic in armv7m_nvic_set_pending()
1396          * is not needed since IRQs are never escalated
1397          */
1398         offset += 0x80;
1399         setval = 1;
1400         /* fall through */
1401     case 0x280 ... 0x2bf: /* NVIC Clear pend */
1402         startvec = 8 * (offset - 0x280) + NVIC_FIRST_IRQ; /* vector # */
1403 
1404         for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
1405             if (value & (1 << i) &&
1406                 (attrs.secure || s->itns[startvec + i])) {
1407                 s->vectors[startvec + i].pending = setval;
1408             }
1409         }
1410         nvic_irq_update(s);
1411         return MEMTX_OK;
1412     case 0x300 ... 0x33f: /* NVIC Active */
1413         return MEMTX_OK; /* R/O */
1414     case 0x400 ... 0x5ef: /* NVIC Priority */
1415         startvec = 8 * (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */
1416 
1417         for (i = 0; i < size && startvec + i < s->num_irq; i++) {
1418             if (attrs.secure || s->itns[startvec + i]) {
1419                 set_prio(s, startvec + i, false, (value >> (i * 8)) & 0xff);
1420             }
1421         }
1422         nvic_irq_update(s);
1423         return MEMTX_OK;
1424     case 0xd18 ... 0xd23: /* System Handler Priority (SHPR1, SHPR2, SHPR3) */
1425         for (i = 0; i < size; i++) {
1426             unsigned hdlidx = (offset - 0xd14) + i;
1427             int newprio = extract32(value, i * 8, 8);
1428             int sbank = shpr_bank(s, hdlidx, attrs);
1429 
1430             if (sbank < 0) {
1431                 continue;
1432             }
1433             set_prio(s, hdlidx, sbank, newprio);
1434         }
1435         nvic_irq_update(s);
1436         return MEMTX_OK;
1437     }
1438     if (size == 4) {
1439         nvic_writel(s, offset, value, attrs);
1440         return MEMTX_OK;
1441     }
1442     qemu_log_mask(LOG_GUEST_ERROR,
1443                   "NVIC: Bad write of size %d at offset 0x%x\n", size, offset);
1444     /* This is UNPREDICTABLE; treat as RAZ/WI */
1445     return MEMTX_OK;
1446 }
1447 
1448 static const MemoryRegionOps nvic_sysreg_ops = {
1449     .read_with_attrs = nvic_sysreg_read,
1450     .write_with_attrs = nvic_sysreg_write,
1451     .endianness = DEVICE_NATIVE_ENDIAN,
1452 };
1453 
1454 static MemTxResult nvic_sysreg_ns_write(void *opaque, hwaddr addr,
1455                                         uint64_t value, unsigned size,
1456                                         MemTxAttrs attrs)
1457 {
1458     if (attrs.secure) {
1459         /* S accesses to the alias act like NS accesses to the real region */
1460         attrs.secure = 0;
1461         return nvic_sysreg_write(opaque, addr, value, size, attrs);
1462     } else {
1463         /* NS attrs are RAZ/WI for privileged, and BusFault for user */
1464         if (attrs.user) {
1465             return MEMTX_ERROR;
1466         }
1467         return MEMTX_OK;
1468     }
1469 }
1470 
1471 static MemTxResult nvic_sysreg_ns_read(void *opaque, hwaddr addr,
1472                                        uint64_t *data, unsigned size,
1473                                        MemTxAttrs attrs)
1474 {
1475     if (attrs.secure) {
1476         /* S accesses to the alias act like NS accesses to the real region */
1477         attrs.secure = 0;
1478         return nvic_sysreg_read(opaque, addr, data, size, attrs);
1479     } else {
1480         /* NS attrs are RAZ/WI for privileged, and BusFault for user */
1481         if (attrs.user) {
1482             return MEMTX_ERROR;
1483         }
1484         *data = 0;
1485         return MEMTX_OK;
1486     }
1487 }
1488 
1489 static const MemoryRegionOps nvic_sysreg_ns_ops = {
1490     .read_with_attrs = nvic_sysreg_ns_read,
1491     .write_with_attrs = nvic_sysreg_ns_write,
1492     .endianness = DEVICE_NATIVE_ENDIAN,
1493 };
1494 
1495 static int nvic_post_load(void *opaque, int version_id)
1496 {
1497     NVICState *s = opaque;
1498     unsigned i;
1499     int resetprio;
1500 
1501     /* Check for out of range priority settings */
1502     resetprio = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? -4 : -3;
1503 
1504     if (s->vectors[ARMV7M_EXCP_RESET].prio != resetprio ||
1505         s->vectors[ARMV7M_EXCP_NMI].prio != -2 ||
1506         s->vectors[ARMV7M_EXCP_HARD].prio != -1) {
1507         return 1;
1508     }
1509     for (i = ARMV7M_EXCP_MEM; i < s->num_irq; i++) {
1510         if (s->vectors[i].prio & ~0xff) {
1511             return 1;
1512         }
1513     }
1514 
1515     nvic_recompute_state(s);
1516 
1517     return 0;
1518 }
1519 
1520 static const VMStateDescription vmstate_VecInfo = {
1521     .name = "armv7m_nvic_info",
1522     .version_id = 1,
1523     .minimum_version_id = 1,
1524     .fields = (VMStateField[]) {
1525         VMSTATE_INT16(prio, VecInfo),
1526         VMSTATE_UINT8(enabled, VecInfo),
1527         VMSTATE_UINT8(pending, VecInfo),
1528         VMSTATE_UINT8(active, VecInfo),
1529         VMSTATE_UINT8(level, VecInfo),
1530         VMSTATE_END_OF_LIST()
1531     }
1532 };
1533 
1534 static bool nvic_security_needed(void *opaque)
1535 {
1536     NVICState *s = opaque;
1537 
1538     return arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY);
1539 }
1540 
1541 static int nvic_security_post_load(void *opaque, int version_id)
1542 {
1543     NVICState *s = opaque;
1544     int i;
1545 
1546     /* Check for out of range priority settings */
1547     if (s->sec_vectors[ARMV7M_EXCP_HARD].prio != -1
1548         && s->sec_vectors[ARMV7M_EXCP_HARD].prio != -3) {
1549         /* We can't cross-check against AIRCR.BFHFNMINS as we don't know
1550          * if the CPU state has been migrated yet; a mismatch won't
1551          * cause the emulation to blow up, though.
1552          */
1553         return 1;
1554     }
1555     for (i = ARMV7M_EXCP_MEM; i < ARRAY_SIZE(s->sec_vectors); i++) {
1556         if (s->sec_vectors[i].prio & ~0xff) {
1557             return 1;
1558         }
1559     }
1560     return 0;
1561 }
1562 
1563 static const VMStateDescription vmstate_nvic_security = {
1564     .name = "nvic/m-security",
1565     .version_id = 1,
1566     .minimum_version_id = 1,
1567     .needed = nvic_security_needed,
1568     .post_load = &nvic_security_post_load,
1569     .fields = (VMStateField[]) {
1570         VMSTATE_STRUCT_ARRAY(sec_vectors, NVICState, NVIC_INTERNAL_VECTORS, 1,
1571                              vmstate_VecInfo, VecInfo),
1572         VMSTATE_UINT32(prigroup[M_REG_S], NVICState),
1573         VMSTATE_BOOL_ARRAY(itns, NVICState, NVIC_MAX_VECTORS),
1574         VMSTATE_END_OF_LIST()
1575     }
1576 };
1577 
1578 static const VMStateDescription vmstate_nvic = {
1579     .name = "armv7m_nvic",
1580     .version_id = 4,
1581     .minimum_version_id = 4,
1582     .post_load = &nvic_post_load,
1583     .fields = (VMStateField[]) {
1584         VMSTATE_STRUCT_ARRAY(vectors, NVICState, NVIC_MAX_VECTORS, 1,
1585                              vmstate_VecInfo, VecInfo),
1586         VMSTATE_UINT32(prigroup[M_REG_NS], NVICState),
1587         VMSTATE_END_OF_LIST()
1588     },
1589     .subsections = (const VMStateDescription*[]) {
1590         &vmstate_nvic_security,
1591         NULL
1592     }
1593 };
1594 
1595 static Property props_nvic[] = {
1596     /* Number of external IRQ lines (so excluding the 16 internal exceptions) */
1597     DEFINE_PROP_UINT32("num-irq", NVICState, num_irq, 64),
1598     DEFINE_PROP_END_OF_LIST()
1599 };
1600 
1601 static void armv7m_nvic_reset(DeviceState *dev)
1602 {
1603     int resetprio;
1604     NVICState *s = NVIC(dev);
1605 
1606     s->vectors[ARMV7M_EXCP_NMI].enabled = 1;
1607     /* MEM, BUS, and USAGE are enabled through
1608      * the System Handler Control register
1609      */
1610     s->vectors[ARMV7M_EXCP_SVC].enabled = 1;
1611     s->vectors[ARMV7M_EXCP_DEBUG].enabled = 1;
1612     s->vectors[ARMV7M_EXCP_PENDSV].enabled = 1;
1613     s->vectors[ARMV7M_EXCP_SYSTICK].enabled = 1;
1614 
1615     resetprio = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? -4 : -3;
1616     s->vectors[ARMV7M_EXCP_RESET].prio = resetprio;
1617     s->vectors[ARMV7M_EXCP_NMI].prio = -2;
1618     s->vectors[ARMV7M_EXCP_HARD].prio = -1;
1619 
1620     if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
1621         s->sec_vectors[ARMV7M_EXCP_HARD].enabled = 1;
1622         s->sec_vectors[ARMV7M_EXCP_SVC].enabled = 1;
1623         s->sec_vectors[ARMV7M_EXCP_PENDSV].enabled = 1;
1624         s->sec_vectors[ARMV7M_EXCP_SYSTICK].enabled = 1;
1625 
1626         /* AIRCR.BFHFNMINS resets to 0 so Secure HF is priority -1 (R_CMTC) */
1627         s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;
1628         /* If AIRCR.BFHFNMINS is 0 then NS HF is (effectively) disabled */
1629         s->vectors[ARMV7M_EXCP_HARD].enabled = 0;
1630     } else {
1631         s->vectors[ARMV7M_EXCP_HARD].enabled = 1;
1632     }
1633 
1634     /* Strictly speaking the reset handler should be enabled.
1635      * However, we don't simulate soft resets through the NVIC,
1636      * and the reset vector should never be pended.
1637      * So we leave it disabled to catch logic errors.
1638      */
1639 
1640     s->exception_prio = NVIC_NOEXC_PRIO;
1641     s->vectpending = 0;
1642     s->vectpending_is_s_banked = false;
1643     s->vectpending_prio = NVIC_NOEXC_PRIO;
1644 
1645     if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
1646         memset(s->itns, 0, sizeof(s->itns));
1647     } else {
1648         /* This state is constant and not guest accessible in a non-security
1649          * NVIC; we set the bits to true to avoid having to do a feature
1650          * bit check in the NVIC enable/pend/etc register accessors.
1651          */
1652         int i;
1653 
1654         for (i = NVIC_FIRST_IRQ; i < ARRAY_SIZE(s->itns); i++) {
1655             s->itns[i] = true;
1656         }
1657     }
1658 }
1659 
1660 static void nvic_systick_trigger(void *opaque, int n, int level)
1661 {
1662     NVICState *s = opaque;
1663 
1664     if (level) {
1665         /* SysTick just asked us to pend its exception.
1666          * (This is different from an external interrupt line's
1667          * behaviour.)
1668          * TODO: when we implement the banked systicks we must make
1669          * this pend the correct banked exception.
1670          */
1671         armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, false);
1672     }
1673 }
1674 
1675 static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
1676 {
1677     NVICState *s = NVIC(dev);
1678     SysBusDevice *systick_sbd;
1679     Error *err = NULL;
1680     int regionlen;
1681 
1682     s->cpu = ARM_CPU(qemu_get_cpu(0));
1683     assert(s->cpu);
1684 
1685     if (s->num_irq > NVIC_MAX_IRQ) {
1686         error_setg(errp, "num-irq %d exceeds NVIC maximum", s->num_irq);
1687         return;
1688     }
1689 
1690     qdev_init_gpio_in(dev, set_irq_level, s->num_irq);
1691 
1692     /* include space for internal exception vectors */
1693     s->num_irq += NVIC_FIRST_IRQ;
1694 
1695     object_property_set_bool(OBJECT(&s->systick), true, "realized", &err);
1696     if (err != NULL) {
1697         error_propagate(errp, err);
1698         return;
1699     }
1700     systick_sbd = SYS_BUS_DEVICE(&s->systick);
1701     sysbus_connect_irq(systick_sbd, 0,
1702                        qdev_get_gpio_in_named(dev, "systick-trigger", 0));
1703 
1704     /* The NVIC and System Control Space (SCS) starts at 0xe000e000
1705      * and looks like this:
1706      *  0x004 - ICTR
1707      *  0x010 - 0xff - systick
1708      *  0x100..0x7ec - NVIC
1709      *  0x7f0..0xcff - Reserved
1710      *  0xd00..0xd3c - SCS registers
1711      *  0xd40..0xeff - Reserved or Not implemented
1712      *  0xf00 - STIR
1713      *
1714      * Some registers within this space are banked between security states.
1715      * In v8M there is a second range 0xe002e000..0xe002efff which is the
1716      * NonSecure alias SCS; secure accesses to this behave like NS accesses
1717      * to the main SCS range, and non-secure accesses (including when
1718      * the security extension is not implemented) are RAZ/WI.
1719      * Note that both the main SCS range and the alias range are defined
1720      * to be exempt from memory attribution (R_BLJT) and so the memory
1721      * transaction attribute always matches the current CPU security
1722      * state (attrs.secure == env->v7m.secure). In the nvic_sysreg_ns_ops
1723      * wrappers we change attrs.secure to indicate the NS access; so
1724      * generally code determining which banked register to use should
1725      * use attrs.secure; code determining actual behaviour of the system
1726      * should use env->v7m.secure.
1727      */
1728     regionlen = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? 0x21000 : 0x1000;
1729     memory_region_init(&s->container, OBJECT(s), "nvic", regionlen);
1730     /* The system register region goes at the bottom of the priority
1731      * stack as it covers the whole page.
1732      */
1733     memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s,
1734                           "nvic_sysregs", 0x1000);
1735     memory_region_add_subregion(&s->container, 0, &s->sysregmem);
1736     memory_region_add_subregion_overlap(&s->container, 0x10,
1737                                         sysbus_mmio_get_region(systick_sbd, 0),
1738                                         1);
1739 
1740     if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) {
1741         memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s),
1742                               &nvic_sysreg_ns_ops, s,
1743                               "nvic_sysregs_ns", 0x1000);
1744         memory_region_add_subregion(&s->container, 0x20000, &s->sysreg_ns_mem);
1745     }
1746 
1747     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
1748 }
1749 
1750 static void armv7m_nvic_instance_init(Object *obj)
1751 {
1752     /* We have a different default value for the num-irq property
1753      * than our superclass. This function runs after qdev init
1754      * has set the defaults from the Property array and before
1755      * any user-specified property setting, so just modify the
1756      * value in the GICState struct.
1757      */
1758     DeviceState *dev = DEVICE(obj);
1759     NVICState *nvic = NVIC(obj);
1760     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1761 
1762     object_initialize(&nvic->systick, sizeof(nvic->systick), TYPE_SYSTICK);
1763     qdev_set_parent_bus(DEVICE(&nvic->systick), sysbus_get_default());
1764 
1765     sysbus_init_irq(sbd, &nvic->excpout);
1766     qdev_init_gpio_out_named(dev, &nvic->sysresetreq, "SYSRESETREQ", 1);
1767     qdev_init_gpio_in_named(dev, nvic_systick_trigger, "systick-trigger", 1);
1768 }
1769 
1770 static void armv7m_nvic_class_init(ObjectClass *klass, void *data)
1771 {
1772     DeviceClass *dc = DEVICE_CLASS(klass);
1773 
1774     dc->vmsd  = &vmstate_nvic;
1775     dc->props = props_nvic;
1776     dc->reset = armv7m_nvic_reset;
1777     dc->realize = armv7m_nvic_realize;
1778 }
1779 
1780 static const TypeInfo armv7m_nvic_info = {
1781     .name          = TYPE_NVIC,
1782     .parent        = TYPE_SYS_BUS_DEVICE,
1783     .instance_init = armv7m_nvic_instance_init,
1784     .instance_size = sizeof(NVICState),
1785     .class_init    = armv7m_nvic_class_init,
1786     .class_size    = sizeof(SysBusDeviceClass),
1787 };
1788 
1789 static void armv7m_nvic_register_types(void)
1790 {
1791     type_register_static(&armv7m_nvic_info);
1792 }
1793 
1794 type_init(armv7m_nvic_register_types)
1795