1 /* 2 * ARM Nested Vectored Interrupt Controller 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 * 9 * The ARMv7M System controller is fairly tightly tied in with the 10 * NVIC. Much of that is also implemented here. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "qapi/error.h" 15 #include "qemu-common.h" 16 #include "cpu.h" 17 #include "hw/sysbus.h" 18 #include "qemu/timer.h" 19 #include "hw/arm/arm.h" 20 #include "hw/intc/armv7m_nvic.h" 21 #include "target/arm/cpu.h" 22 #include "exec/exec-all.h" 23 #include "qemu/log.h" 24 #include "trace.h" 25 26 /* IRQ number counting: 27 * 28 * the num-irq property counts the number of external IRQ lines 29 * 30 * NVICState::num_irq counts the total number of exceptions 31 * (external IRQs, the 15 internal exceptions including reset, 32 * and one for the unused exception number 0). 33 * 34 * NVIC_MAX_IRQ is the highest permitted number of external IRQ lines. 35 * 36 * NVIC_MAX_VECTORS is the highest permitted number of exceptions. 37 * 38 * Iterating through all exceptions should typically be done with 39 * for (i = 1; i < s->num_irq; i++) to avoid the unused slot 0. 40 * 41 * The external qemu_irq lines are the NVIC's external IRQ lines, 42 * so line 0 is exception 16. 43 * 44 * In the terminology of the architecture manual, "interrupts" are 45 * a subcategory of exception referring to the external interrupts 46 * (which are exception numbers NVIC_FIRST_IRQ and upward). 47 * For historical reasons QEMU tends to use "interrupt" and 48 * "exception" more or less interchangeably. 49 */ 50 #define NVIC_FIRST_IRQ NVIC_INTERNAL_VECTORS 51 #define NVIC_MAX_IRQ (NVIC_MAX_VECTORS - NVIC_FIRST_IRQ) 52 53 /* Effective running priority of the CPU when no exception is active 54 * (higher than the highest possible priority value) 55 */ 56 #define NVIC_NOEXC_PRIO 0x100 57 /* Maximum priority of non-secure exceptions when AIRCR.PRIS is set */ 58 #define NVIC_NS_PRIO_LIMIT 0x80 59 60 static const uint8_t nvic_id[] = { 61 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1 62 }; 63 64 static int nvic_pending_prio(NVICState *s) 65 { 66 /* return the group priority of the current pending interrupt, 67 * or NVIC_NOEXC_PRIO if no interrupt is pending 68 */ 69 return s->vectpending_prio; 70 } 71 72 /* Return the value of the ISCR RETTOBASE bit: 73 * 1 if there is exactly one active exception 74 * 0 if there is more than one active exception 75 * UNKNOWN if there are no active exceptions (we choose 1, 76 * which matches the choice Cortex-M3 is documented as making). 77 * 78 * NB: some versions of the documentation talk about this 79 * counting "active exceptions other than the one shown by IPSR"; 80 * this is only different in the obscure corner case where guest 81 * code has manually deactivated an exception and is about 82 * to fail an exception-return integrity check. The definition 83 * above is the one from the v8M ARM ARM and is also in line 84 * with the behaviour documented for the Cortex-M3. 85 */ 86 static bool nvic_rettobase(NVICState *s) 87 { 88 int irq, nhand = 0; 89 bool check_sec = arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY); 90 91 for (irq = ARMV7M_EXCP_RESET; irq < s->num_irq; irq++) { 92 if (s->vectors[irq].active || 93 (check_sec && irq < NVIC_INTERNAL_VECTORS && 94 s->sec_vectors[irq].active)) { 95 nhand++; 96 if (nhand == 2) { 97 return 0; 98 } 99 } 100 } 101 102 return 1; 103 } 104 105 /* Return the value of the ISCR ISRPENDING bit: 106 * 1 if an external interrupt is pending 107 * 0 if no external interrupt is pending 108 */ 109 static bool nvic_isrpending(NVICState *s) 110 { 111 int irq; 112 113 /* We can shortcut if the highest priority pending interrupt 114 * happens to be external or if there is nothing pending. 115 */ 116 if (s->vectpending > NVIC_FIRST_IRQ) { 117 return true; 118 } 119 if (s->vectpending == 0) { 120 return false; 121 } 122 123 for (irq = NVIC_FIRST_IRQ; irq < s->num_irq; irq++) { 124 if (s->vectors[irq].pending) { 125 return true; 126 } 127 } 128 return false; 129 } 130 131 static bool exc_is_banked(int exc) 132 { 133 /* Return true if this is one of the limited set of exceptions which 134 * are banked (and thus have state in sec_vectors[]) 135 */ 136 return exc == ARMV7M_EXCP_HARD || 137 exc == ARMV7M_EXCP_MEM || 138 exc == ARMV7M_EXCP_USAGE || 139 exc == ARMV7M_EXCP_SVC || 140 exc == ARMV7M_EXCP_PENDSV || 141 exc == ARMV7M_EXCP_SYSTICK; 142 } 143 144 /* Return a mask word which clears the subpriority bits from 145 * a priority value for an M-profile exception, leaving only 146 * the group priority. 147 */ 148 static inline uint32_t nvic_gprio_mask(NVICState *s, bool secure) 149 { 150 return ~0U << (s->prigroup[secure] + 1); 151 } 152 153 static bool exc_targets_secure(NVICState *s, int exc) 154 { 155 /* Return true if this non-banked exception targets Secure state. */ 156 if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) { 157 return false; 158 } 159 160 if (exc >= NVIC_FIRST_IRQ) { 161 return !s->itns[exc]; 162 } 163 164 /* Function shouldn't be called for banked exceptions. */ 165 assert(!exc_is_banked(exc)); 166 167 switch (exc) { 168 case ARMV7M_EXCP_NMI: 169 case ARMV7M_EXCP_BUS: 170 return !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK); 171 case ARMV7M_EXCP_SECURE: 172 return true; 173 case ARMV7M_EXCP_DEBUG: 174 /* TODO: controlled by DEMCR.SDME, which we don't yet implement */ 175 return false; 176 default: 177 /* reset, and reserved (unused) low exception numbers. 178 * We'll get called by code that loops through all the exception 179 * numbers, but it doesn't matter what we return here as these 180 * non-existent exceptions will never be pended or active. 181 */ 182 return true; 183 } 184 } 185 186 static int exc_group_prio(NVICState *s, int rawprio, bool targets_secure) 187 { 188 /* Return the group priority for this exception, given its raw 189 * (group-and-subgroup) priority value and whether it is targeting 190 * secure state or not. 191 */ 192 if (rawprio < 0) { 193 return rawprio; 194 } 195 rawprio &= nvic_gprio_mask(s, targets_secure); 196 /* AIRCR.PRIS causes us to squash all NS priorities into the 197 * lower half of the total range 198 */ 199 if (!targets_secure && 200 (s->cpu->env.v7m.aircr & R_V7M_AIRCR_PRIS_MASK)) { 201 rawprio = (rawprio >> 1) + NVIC_NS_PRIO_LIMIT; 202 } 203 return rawprio; 204 } 205 206 /* Recompute vectpending and exception_prio for a CPU which implements 207 * the Security extension 208 */ 209 static void nvic_recompute_state_secure(NVICState *s) 210 { 211 int i, bank; 212 int pend_prio = NVIC_NOEXC_PRIO; 213 int active_prio = NVIC_NOEXC_PRIO; 214 int pend_irq = 0; 215 bool pending_is_s_banked = false; 216 217 /* R_CQRV: precedence is by: 218 * - lowest group priority; if both the same then 219 * - lowest subpriority; if both the same then 220 * - lowest exception number; if both the same (ie banked) then 221 * - secure exception takes precedence 222 * Compare pseudocode RawExecutionPriority. 223 * Annoyingly, now we have two prigroup values (for S and NS) 224 * we can't do the loop comparison on raw priority values. 225 */ 226 for (i = 1; i < s->num_irq; i++) { 227 for (bank = M_REG_S; bank >= M_REG_NS; bank--) { 228 VecInfo *vec; 229 int prio; 230 bool targets_secure; 231 232 if (bank == M_REG_S) { 233 if (!exc_is_banked(i)) { 234 continue; 235 } 236 vec = &s->sec_vectors[i]; 237 targets_secure = true; 238 } else { 239 vec = &s->vectors[i]; 240 targets_secure = !exc_is_banked(i) && exc_targets_secure(s, i); 241 } 242 243 prio = exc_group_prio(s, vec->prio, targets_secure); 244 if (vec->enabled && vec->pending && prio < pend_prio) { 245 pend_prio = prio; 246 pend_irq = i; 247 pending_is_s_banked = (bank == M_REG_S); 248 } 249 if (vec->active && prio < active_prio) { 250 active_prio = prio; 251 } 252 } 253 } 254 255 s->vectpending_is_s_banked = pending_is_s_banked; 256 s->vectpending = pend_irq; 257 s->vectpending_prio = pend_prio; 258 s->exception_prio = active_prio; 259 260 trace_nvic_recompute_state_secure(s->vectpending, 261 s->vectpending_is_s_banked, 262 s->vectpending_prio, 263 s->exception_prio); 264 } 265 266 /* Recompute vectpending and exception_prio */ 267 static void nvic_recompute_state(NVICState *s) 268 { 269 int i; 270 int pend_prio = NVIC_NOEXC_PRIO; 271 int active_prio = NVIC_NOEXC_PRIO; 272 int pend_irq = 0; 273 274 /* In theory we could write one function that handled both 275 * the "security extension present" and "not present"; however 276 * the security related changes significantly complicate the 277 * recomputation just by themselves and mixing both cases together 278 * would be even worse, so we retain a separate non-secure-only 279 * version for CPUs which don't implement the security extension. 280 */ 281 if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) { 282 nvic_recompute_state_secure(s); 283 return; 284 } 285 286 for (i = 1; i < s->num_irq; i++) { 287 VecInfo *vec = &s->vectors[i]; 288 289 if (vec->enabled && vec->pending && vec->prio < pend_prio) { 290 pend_prio = vec->prio; 291 pend_irq = i; 292 } 293 if (vec->active && vec->prio < active_prio) { 294 active_prio = vec->prio; 295 } 296 } 297 298 if (active_prio > 0) { 299 active_prio &= nvic_gprio_mask(s, false); 300 } 301 302 if (pend_prio > 0) { 303 pend_prio &= nvic_gprio_mask(s, false); 304 } 305 306 s->vectpending = pend_irq; 307 s->vectpending_prio = pend_prio; 308 s->exception_prio = active_prio; 309 310 trace_nvic_recompute_state(s->vectpending, 311 s->vectpending_prio, 312 s->exception_prio); 313 } 314 315 /* Return the current execution priority of the CPU 316 * (equivalent to the pseudocode ExecutionPriority function). 317 * This is a value between -2 (NMI priority) and NVIC_NOEXC_PRIO. 318 */ 319 static inline int nvic_exec_prio(NVICState *s) 320 { 321 CPUARMState *env = &s->cpu->env; 322 int running = NVIC_NOEXC_PRIO; 323 324 if (env->v7m.basepri[M_REG_NS] > 0) { 325 running = exc_group_prio(s, env->v7m.basepri[M_REG_NS], M_REG_NS); 326 } 327 328 if (env->v7m.basepri[M_REG_S] > 0) { 329 int basepri = exc_group_prio(s, env->v7m.basepri[M_REG_S], M_REG_S); 330 if (running > basepri) { 331 running = basepri; 332 } 333 } 334 335 if (env->v7m.primask[M_REG_NS]) { 336 if (env->v7m.aircr & R_V7M_AIRCR_PRIS_MASK) { 337 if (running > NVIC_NS_PRIO_LIMIT) { 338 running = NVIC_NS_PRIO_LIMIT; 339 } 340 } else { 341 running = 0; 342 } 343 } 344 345 if (env->v7m.primask[M_REG_S]) { 346 running = 0; 347 } 348 349 if (env->v7m.faultmask[M_REG_NS]) { 350 if (env->v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) { 351 running = -1; 352 } else { 353 if (env->v7m.aircr & R_V7M_AIRCR_PRIS_MASK) { 354 if (running > NVIC_NS_PRIO_LIMIT) { 355 running = NVIC_NS_PRIO_LIMIT; 356 } 357 } else { 358 running = 0; 359 } 360 } 361 } 362 363 if (env->v7m.faultmask[M_REG_S]) { 364 running = (env->v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) ? -3 : -1; 365 } 366 367 /* consider priority of active handler */ 368 return MIN(running, s->exception_prio); 369 } 370 371 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 372 { 373 /* Return true if the requested execution priority is negative 374 * for the specified security state, ie that security state 375 * has an active NMI or HardFault or has set its FAULTMASK. 376 * Note that this is not the same as whether the execution 377 * priority is actually negative (for instance AIRCR.PRIS may 378 * mean we don't allow FAULTMASK_NS to actually make the execution 379 * priority negative). Compare pseudocode IsReqExcPriNeg(). 380 */ 381 NVICState *s = opaque; 382 383 if (s->cpu->env.v7m.faultmask[secure]) { 384 return true; 385 } 386 387 if (secure ? s->sec_vectors[ARMV7M_EXCP_HARD].active : 388 s->vectors[ARMV7M_EXCP_HARD].active) { 389 return true; 390 } 391 392 if (s->vectors[ARMV7M_EXCP_NMI].active && 393 exc_targets_secure(s, ARMV7M_EXCP_NMI) == secure) { 394 return true; 395 } 396 397 return false; 398 } 399 400 bool armv7m_nvic_can_take_pending_exception(void *opaque) 401 { 402 NVICState *s = opaque; 403 404 return nvic_exec_prio(s) > nvic_pending_prio(s); 405 } 406 407 int armv7m_nvic_raw_execution_priority(void *opaque) 408 { 409 NVICState *s = opaque; 410 411 return s->exception_prio; 412 } 413 414 /* caller must call nvic_irq_update() after this. 415 * secure indicates the bank to use for banked exceptions (we assert if 416 * we are passed secure=true for a non-banked exception). 417 */ 418 static void set_prio(NVICState *s, unsigned irq, bool secure, uint8_t prio) 419 { 420 assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */ 421 assert(irq < s->num_irq); 422 423 if (secure) { 424 assert(exc_is_banked(irq)); 425 s->sec_vectors[irq].prio = prio; 426 } else { 427 s->vectors[irq].prio = prio; 428 } 429 430 trace_nvic_set_prio(irq, secure, prio); 431 } 432 433 /* Return the current raw priority register value. 434 * secure indicates the bank to use for banked exceptions (we assert if 435 * we are passed secure=true for a non-banked exception). 436 */ 437 static int get_prio(NVICState *s, unsigned irq, bool secure) 438 { 439 assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */ 440 assert(irq < s->num_irq); 441 442 if (secure) { 443 assert(exc_is_banked(irq)); 444 return s->sec_vectors[irq].prio; 445 } else { 446 return s->vectors[irq].prio; 447 } 448 } 449 450 /* Recompute state and assert irq line accordingly. 451 * Must be called after changes to: 452 * vec->active, vec->enabled, vec->pending or vec->prio for any vector 453 * prigroup 454 */ 455 static void nvic_irq_update(NVICState *s) 456 { 457 int lvl; 458 int pend_prio; 459 460 nvic_recompute_state(s); 461 pend_prio = nvic_pending_prio(s); 462 463 /* Raise NVIC output if this IRQ would be taken, except that we 464 * ignore the effects of the BASEPRI, FAULTMASK and PRIMASK (which 465 * will be checked for in arm_v7m_cpu_exec_interrupt()); changes 466 * to those CPU registers don't cause us to recalculate the NVIC 467 * pending info. 468 */ 469 lvl = (pend_prio < s->exception_prio); 470 trace_nvic_irq_update(s->vectpending, pend_prio, s->exception_prio, lvl); 471 qemu_set_irq(s->excpout, lvl); 472 } 473 474 /** 475 * armv7m_nvic_clear_pending: mark the specified exception as not pending 476 * @opaque: the NVIC 477 * @irq: the exception number to mark as not pending 478 * @secure: false for non-banked exceptions or for the nonsecure 479 * version of a banked exception, true for the secure version of a banked 480 * exception. 481 * 482 * Marks the specified exception as not pending. Note that we will assert() 483 * if @secure is true and @irq does not specify one of the fixed set 484 * of architecturally banked exceptions. 485 */ 486 static void armv7m_nvic_clear_pending(void *opaque, int irq, bool secure) 487 { 488 NVICState *s = (NVICState *)opaque; 489 VecInfo *vec; 490 491 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); 492 493 if (secure) { 494 assert(exc_is_banked(irq)); 495 vec = &s->sec_vectors[irq]; 496 } else { 497 vec = &s->vectors[irq]; 498 } 499 trace_nvic_clear_pending(irq, secure, vec->enabled, vec->prio); 500 if (vec->pending) { 501 vec->pending = 0; 502 nvic_irq_update(s); 503 } 504 } 505 506 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure) 507 { 508 NVICState *s = (NVICState *)opaque; 509 bool banked = exc_is_banked(irq); 510 VecInfo *vec; 511 512 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); 513 assert(!secure || banked); 514 515 vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq]; 516 517 trace_nvic_set_pending(irq, secure, vec->enabled, vec->prio); 518 519 if (irq >= ARMV7M_EXCP_HARD && irq < ARMV7M_EXCP_PENDSV) { 520 /* If a synchronous exception is pending then it may be 521 * escalated to HardFault if: 522 * * it is equal or lower priority to current execution 523 * * it is disabled 524 * (ie we need to take it immediately but we can't do so). 525 * Asynchronous exceptions (and interrupts) simply remain pending. 526 * 527 * For QEMU, we don't have any imprecise (asynchronous) faults, 528 * so we can assume that PREFETCH_ABORT and DATA_ABORT are always 529 * synchronous. 530 * Debug exceptions are awkward because only Debug exceptions 531 * resulting from the BKPT instruction should be escalated, 532 * but we don't currently implement any Debug exceptions other 533 * than those that result from BKPT, so we treat all debug exceptions 534 * as needing escalation. 535 * 536 * This all means we can identify whether to escalate based only on 537 * the exception number and don't (yet) need the caller to explicitly 538 * tell us whether this exception is synchronous or not. 539 */ 540 int running = nvic_exec_prio(s); 541 bool escalate = false; 542 543 if (exc_group_prio(s, vec->prio, secure) >= running) { 544 trace_nvic_escalate_prio(irq, vec->prio, running); 545 escalate = true; 546 } else if (!vec->enabled) { 547 trace_nvic_escalate_disabled(irq); 548 escalate = true; 549 } 550 551 if (escalate) { 552 553 /* We need to escalate this exception to a synchronous HardFault. 554 * If BFHFNMINS is set then we escalate to the banked HF for 555 * the target security state of the original exception; otherwise 556 * we take a Secure HardFault. 557 */ 558 irq = ARMV7M_EXCP_HARD; 559 if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) && 560 (secure || 561 !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK))) { 562 vec = &s->sec_vectors[irq]; 563 } else { 564 vec = &s->vectors[irq]; 565 } 566 if (running <= vec->prio) { 567 /* We want to escalate to HardFault but we can't take the 568 * synchronous HardFault at this point either. This is a 569 * Lockup condition due to a guest bug. We don't model 570 * Lockup, so report via cpu_abort() instead. 571 */ 572 cpu_abort(&s->cpu->parent_obj, 573 "Lockup: can't escalate %d to HardFault " 574 "(current priority %d)\n", irq, running); 575 } 576 577 /* HF may be banked but there is only one shared HFSR */ 578 s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK; 579 } 580 } 581 582 if (!vec->pending) { 583 vec->pending = 1; 584 nvic_irq_update(s); 585 } 586 } 587 588 /* Make pending IRQ active. */ 589 void armv7m_nvic_acknowledge_irq(void *opaque) 590 { 591 NVICState *s = (NVICState *)opaque; 592 CPUARMState *env = &s->cpu->env; 593 const int pending = s->vectpending; 594 const int running = nvic_exec_prio(s); 595 VecInfo *vec; 596 597 assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq); 598 599 vec = &s->vectors[pending]; 600 601 assert(vec->enabled); 602 assert(vec->pending); 603 604 assert(s->vectpending_prio < running); 605 606 trace_nvic_acknowledge_irq(pending, s->vectpending_prio); 607 608 vec->active = 1; 609 vec->pending = 0; 610 611 env->v7m.exception = s->vectpending; 612 613 nvic_irq_update(s); 614 } 615 616 int armv7m_nvic_complete_irq(void *opaque, int irq) 617 { 618 NVICState *s = (NVICState *)opaque; 619 VecInfo *vec; 620 int ret; 621 622 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); 623 624 vec = &s->vectors[irq]; 625 626 trace_nvic_complete_irq(irq); 627 628 if (!vec->active) { 629 /* Tell the caller this was an illegal exception return */ 630 return -1; 631 } 632 633 ret = nvic_rettobase(s); 634 635 vec->active = 0; 636 if (vec->level) { 637 /* Re-pend the exception if it's still held high; only 638 * happens for extenal IRQs 639 */ 640 assert(irq >= NVIC_FIRST_IRQ); 641 vec->pending = 1; 642 } 643 644 nvic_irq_update(s); 645 646 return ret; 647 } 648 649 /* callback when external interrupt line is changed */ 650 static void set_irq_level(void *opaque, int n, int level) 651 { 652 NVICState *s = opaque; 653 VecInfo *vec; 654 655 n += NVIC_FIRST_IRQ; 656 657 assert(n >= NVIC_FIRST_IRQ && n < s->num_irq); 658 659 trace_nvic_set_irq_level(n, level); 660 661 /* The pending status of an external interrupt is 662 * latched on rising edge and exception handler return. 663 * 664 * Pulsing the IRQ will always run the handler 665 * once, and the handler will re-run until the 666 * level is low when the handler completes. 667 */ 668 vec = &s->vectors[n]; 669 if (level != vec->level) { 670 vec->level = level; 671 if (level) { 672 armv7m_nvic_set_pending(s, n, false); 673 } 674 } 675 } 676 677 static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) 678 { 679 ARMCPU *cpu = s->cpu; 680 uint32_t val; 681 682 switch (offset) { 683 case 4: /* Interrupt Control Type. */ 684 return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1; 685 case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */ 686 { 687 int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ; 688 int i; 689 690 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 691 goto bad_offset; 692 } 693 if (!attrs.secure) { 694 return 0; 695 } 696 val = 0; 697 for (i = 0; i < 32 && startvec + i < s->num_irq; i++) { 698 if (s->itns[startvec + i]) { 699 val |= (1 << i); 700 } 701 } 702 return val; 703 } 704 case 0xd00: /* CPUID Base. */ 705 return cpu->midr; 706 case 0xd04: /* Interrupt Control State (ICSR) */ 707 /* VECTACTIVE */ 708 val = cpu->env.v7m.exception; 709 /* VECTPENDING */ 710 val |= (s->vectpending & 0xff) << 12; 711 /* ISRPENDING - set if any external IRQ is pending */ 712 if (nvic_isrpending(s)) { 713 val |= (1 << 22); 714 } 715 /* RETTOBASE - set if only one handler is active */ 716 if (nvic_rettobase(s)) { 717 val |= (1 << 11); 718 } 719 if (attrs.secure) { 720 /* PENDSTSET */ 721 if (s->sec_vectors[ARMV7M_EXCP_SYSTICK].pending) { 722 val |= (1 << 26); 723 } 724 /* PENDSVSET */ 725 if (s->sec_vectors[ARMV7M_EXCP_PENDSV].pending) { 726 val |= (1 << 28); 727 } 728 } else { 729 /* PENDSTSET */ 730 if (s->vectors[ARMV7M_EXCP_SYSTICK].pending) { 731 val |= (1 << 26); 732 } 733 /* PENDSVSET */ 734 if (s->vectors[ARMV7M_EXCP_PENDSV].pending) { 735 val |= (1 << 28); 736 } 737 } 738 /* NMIPENDSET */ 739 if ((cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) && 740 s->vectors[ARMV7M_EXCP_NMI].pending) { 741 val |= (1 << 31); 742 } 743 /* ISRPREEMPT: RES0 when halting debug not implemented */ 744 /* STTNS: RES0 for the Main Extension */ 745 return val; 746 case 0xd08: /* Vector Table Offset. */ 747 return cpu->env.v7m.vecbase[attrs.secure]; 748 case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */ 749 val = 0xfa050000 | (s->prigroup[attrs.secure] << 8); 750 if (attrs.secure) { 751 /* s->aircr stores PRIS, BFHFNMINS, SYSRESETREQS */ 752 val |= cpu->env.v7m.aircr; 753 } else { 754 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 755 /* BFHFNMINS is R/O from NS; other bits are RAZ/WI. If 756 * security isn't supported then BFHFNMINS is RAO (and 757 * the bit in env.v7m.aircr is always set). 758 */ 759 val |= cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK; 760 } 761 } 762 return val; 763 case 0xd10: /* System Control. */ 764 /* TODO: Implement SLEEPONEXIT. */ 765 return 0; 766 case 0xd14: /* Configuration Control. */ 767 /* The BFHFNMIGN bit is the only non-banked bit; we 768 * keep it in the non-secure copy of the register. 769 */ 770 val = cpu->env.v7m.ccr[attrs.secure]; 771 val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK; 772 return val; 773 case 0xd24: /* System Handler Control and State (SHCSR) */ 774 val = 0; 775 if (attrs.secure) { 776 if (s->sec_vectors[ARMV7M_EXCP_MEM].active) { 777 val |= (1 << 0); 778 } 779 if (s->sec_vectors[ARMV7M_EXCP_HARD].active) { 780 val |= (1 << 2); 781 } 782 if (s->sec_vectors[ARMV7M_EXCP_USAGE].active) { 783 val |= (1 << 3); 784 } 785 if (s->sec_vectors[ARMV7M_EXCP_SVC].active) { 786 val |= (1 << 7); 787 } 788 if (s->sec_vectors[ARMV7M_EXCP_PENDSV].active) { 789 val |= (1 << 10); 790 } 791 if (s->sec_vectors[ARMV7M_EXCP_SYSTICK].active) { 792 val |= (1 << 11); 793 } 794 if (s->sec_vectors[ARMV7M_EXCP_USAGE].pending) { 795 val |= (1 << 12); 796 } 797 if (s->sec_vectors[ARMV7M_EXCP_MEM].pending) { 798 val |= (1 << 13); 799 } 800 if (s->sec_vectors[ARMV7M_EXCP_SVC].pending) { 801 val |= (1 << 15); 802 } 803 if (s->sec_vectors[ARMV7M_EXCP_MEM].enabled) { 804 val |= (1 << 16); 805 } 806 if (s->sec_vectors[ARMV7M_EXCP_USAGE].enabled) { 807 val |= (1 << 18); 808 } 809 if (s->sec_vectors[ARMV7M_EXCP_HARD].pending) { 810 val |= (1 << 21); 811 } 812 /* SecureFault is not banked but is always RAZ/WI to NS */ 813 if (s->vectors[ARMV7M_EXCP_SECURE].active) { 814 val |= (1 << 4); 815 } 816 if (s->vectors[ARMV7M_EXCP_SECURE].enabled) { 817 val |= (1 << 19); 818 } 819 if (s->vectors[ARMV7M_EXCP_SECURE].pending) { 820 val |= (1 << 20); 821 } 822 } else { 823 if (s->vectors[ARMV7M_EXCP_MEM].active) { 824 val |= (1 << 0); 825 } 826 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 827 /* HARDFAULTACT, HARDFAULTPENDED not present in v7M */ 828 if (s->vectors[ARMV7M_EXCP_HARD].active) { 829 val |= (1 << 2); 830 } 831 if (s->vectors[ARMV7M_EXCP_HARD].pending) { 832 val |= (1 << 21); 833 } 834 } 835 if (s->vectors[ARMV7M_EXCP_USAGE].active) { 836 val |= (1 << 3); 837 } 838 if (s->vectors[ARMV7M_EXCP_SVC].active) { 839 val |= (1 << 7); 840 } 841 if (s->vectors[ARMV7M_EXCP_PENDSV].active) { 842 val |= (1 << 10); 843 } 844 if (s->vectors[ARMV7M_EXCP_SYSTICK].active) { 845 val |= (1 << 11); 846 } 847 if (s->vectors[ARMV7M_EXCP_USAGE].pending) { 848 val |= (1 << 12); 849 } 850 if (s->vectors[ARMV7M_EXCP_MEM].pending) { 851 val |= (1 << 13); 852 } 853 if (s->vectors[ARMV7M_EXCP_SVC].pending) { 854 val |= (1 << 15); 855 } 856 if (s->vectors[ARMV7M_EXCP_MEM].enabled) { 857 val |= (1 << 16); 858 } 859 if (s->vectors[ARMV7M_EXCP_USAGE].enabled) { 860 val |= (1 << 18); 861 } 862 } 863 if (attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { 864 if (s->vectors[ARMV7M_EXCP_BUS].active) { 865 val |= (1 << 1); 866 } 867 if (s->vectors[ARMV7M_EXCP_BUS].pending) { 868 val |= (1 << 14); 869 } 870 if (s->vectors[ARMV7M_EXCP_BUS].enabled) { 871 val |= (1 << 17); 872 } 873 if (arm_feature(&cpu->env, ARM_FEATURE_V8) && 874 s->vectors[ARMV7M_EXCP_NMI].active) { 875 /* NMIACT is not present in v7M */ 876 val |= (1 << 5); 877 } 878 } 879 880 /* TODO: this is RAZ/WI from NS if DEMCR.SDME is set */ 881 if (s->vectors[ARMV7M_EXCP_DEBUG].active) { 882 val |= (1 << 8); 883 } 884 return val; 885 case 0xd28: /* Configurable Fault Status. */ 886 /* The BFSR bits [15:8] are shared between security states 887 * and we store them in the NS copy 888 */ 889 val = cpu->env.v7m.cfsr[attrs.secure]; 890 val |= cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK; 891 return val; 892 case 0xd2c: /* Hard Fault Status. */ 893 return cpu->env.v7m.hfsr; 894 case 0xd30: /* Debug Fault Status. */ 895 return cpu->env.v7m.dfsr; 896 case 0xd34: /* MMFAR MemManage Fault Address */ 897 return cpu->env.v7m.mmfar[attrs.secure]; 898 case 0xd38: /* Bus Fault Address. */ 899 return cpu->env.v7m.bfar; 900 case 0xd3c: /* Aux Fault Status. */ 901 /* TODO: Implement fault status registers. */ 902 qemu_log_mask(LOG_UNIMP, 903 "Aux Fault status registers unimplemented\n"); 904 return 0; 905 case 0xd40: /* PFR0. */ 906 return 0x00000030; 907 case 0xd44: /* PRF1. */ 908 return 0x00000200; 909 case 0xd48: /* DFR0. */ 910 return 0x00100000; 911 case 0xd4c: /* AFR0. */ 912 return 0x00000000; 913 case 0xd50: /* MMFR0. */ 914 return 0x00000030; 915 case 0xd54: /* MMFR1. */ 916 return 0x00000000; 917 case 0xd58: /* MMFR2. */ 918 return 0x00000000; 919 case 0xd5c: /* MMFR3. */ 920 return 0x00000000; 921 case 0xd60: /* ISAR0. */ 922 return 0x01141110; 923 case 0xd64: /* ISAR1. */ 924 return 0x02111000; 925 case 0xd68: /* ISAR2. */ 926 return 0x21112231; 927 case 0xd6c: /* ISAR3. */ 928 return 0x01111110; 929 case 0xd70: /* ISAR4. */ 930 return 0x01310102; 931 /* TODO: Implement debug registers. */ 932 case 0xd90: /* MPU_TYPE */ 933 /* Unified MPU; if the MPU is not present this value is zero */ 934 return cpu->pmsav7_dregion << 8; 935 break; 936 case 0xd94: /* MPU_CTRL */ 937 return cpu->env.v7m.mpu_ctrl[attrs.secure]; 938 case 0xd98: /* MPU_RNR */ 939 return cpu->env.pmsav7.rnr[attrs.secure]; 940 case 0xd9c: /* MPU_RBAR */ 941 case 0xda4: /* MPU_RBAR_A1 */ 942 case 0xdac: /* MPU_RBAR_A2 */ 943 case 0xdb4: /* MPU_RBAR_A3 */ 944 { 945 int region = cpu->env.pmsav7.rnr[attrs.secure]; 946 947 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 948 /* PMSAv8M handling of the aliases is different from v7M: 949 * aliases A1, A2, A3 override the low two bits of the region 950 * number in MPU_RNR, and there is no 'region' field in the 951 * RBAR register. 952 */ 953 int aliasno = (offset - 0xd9c) / 8; /* 0..3 */ 954 if (aliasno) { 955 region = deposit32(region, 0, 2, aliasno); 956 } 957 if (region >= cpu->pmsav7_dregion) { 958 return 0; 959 } 960 return cpu->env.pmsav8.rbar[attrs.secure][region]; 961 } 962 963 if (region >= cpu->pmsav7_dregion) { 964 return 0; 965 } 966 return (cpu->env.pmsav7.drbar[region] & 0x1f) | (region & 0xf); 967 } 968 case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */ 969 case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */ 970 case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */ 971 case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */ 972 { 973 int region = cpu->env.pmsav7.rnr[attrs.secure]; 974 975 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 976 /* PMSAv8M handling of the aliases is different from v7M: 977 * aliases A1, A2, A3 override the low two bits of the region 978 * number in MPU_RNR. 979 */ 980 int aliasno = (offset - 0xda0) / 8; /* 0..3 */ 981 if (aliasno) { 982 region = deposit32(region, 0, 2, aliasno); 983 } 984 if (region >= cpu->pmsav7_dregion) { 985 return 0; 986 } 987 return cpu->env.pmsav8.rlar[attrs.secure][region]; 988 } 989 990 if (region >= cpu->pmsav7_dregion) { 991 return 0; 992 } 993 return ((cpu->env.pmsav7.dracr[region] & 0xffff) << 16) | 994 (cpu->env.pmsav7.drsr[region] & 0xffff); 995 } 996 case 0xdc0: /* MPU_MAIR0 */ 997 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 998 goto bad_offset; 999 } 1000 return cpu->env.pmsav8.mair0[attrs.secure]; 1001 case 0xdc4: /* MPU_MAIR1 */ 1002 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1003 goto bad_offset; 1004 } 1005 return cpu->env.pmsav8.mair1[attrs.secure]; 1006 default: 1007 bad_offset: 1008 qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset); 1009 return 0; 1010 } 1011 } 1012 1013 static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, 1014 MemTxAttrs attrs) 1015 { 1016 ARMCPU *cpu = s->cpu; 1017 1018 switch (offset) { 1019 case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */ 1020 { 1021 int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ; 1022 int i; 1023 1024 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1025 goto bad_offset; 1026 } 1027 if (!attrs.secure) { 1028 break; 1029 } 1030 for (i = 0; i < 32 && startvec + i < s->num_irq; i++) { 1031 s->itns[startvec + i] = (value >> i) & 1; 1032 } 1033 nvic_irq_update(s); 1034 break; 1035 } 1036 case 0xd04: /* Interrupt Control State (ICSR) */ 1037 if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) { 1038 if (value & (1 << 31)) { 1039 armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false); 1040 } else if (value & (1 << 30) && 1041 arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1042 /* PENDNMICLR didn't exist in v7M */ 1043 armv7m_nvic_clear_pending(s, ARMV7M_EXCP_NMI, false); 1044 } 1045 } 1046 if (value & (1 << 28)) { 1047 armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure); 1048 } else if (value & (1 << 27)) { 1049 armv7m_nvic_clear_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure); 1050 } 1051 if (value & (1 << 26)) { 1052 armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, attrs.secure); 1053 } else if (value & (1 << 25)) { 1054 armv7m_nvic_clear_pending(s, ARMV7M_EXCP_SYSTICK, attrs.secure); 1055 } 1056 break; 1057 case 0xd08: /* Vector Table Offset. */ 1058 cpu->env.v7m.vecbase[attrs.secure] = value & 0xffffff80; 1059 break; 1060 case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */ 1061 if ((value >> R_V7M_AIRCR_VECTKEY_SHIFT) == 0x05fa) { 1062 if (value & R_V7M_AIRCR_SYSRESETREQ_MASK) { 1063 if (attrs.secure || 1064 !(cpu->env.v7m.aircr & R_V7M_AIRCR_SYSRESETREQS_MASK)) { 1065 qemu_irq_pulse(s->sysresetreq); 1066 } 1067 } 1068 if (value & R_V7M_AIRCR_VECTCLRACTIVE_MASK) { 1069 qemu_log_mask(LOG_GUEST_ERROR, 1070 "Setting VECTCLRACTIVE when not in DEBUG mode " 1071 "is UNPREDICTABLE\n"); 1072 } 1073 if (value & R_V7M_AIRCR_VECTRESET_MASK) { 1074 /* NB: this bit is RES0 in v8M */ 1075 qemu_log_mask(LOG_GUEST_ERROR, 1076 "Setting VECTRESET when not in DEBUG mode " 1077 "is UNPREDICTABLE\n"); 1078 } 1079 s->prigroup[attrs.secure] = extract32(value, 1080 R_V7M_AIRCR_PRIGROUP_SHIFT, 1081 R_V7M_AIRCR_PRIGROUP_LENGTH); 1082 if (attrs.secure) { 1083 /* These bits are only writable by secure */ 1084 cpu->env.v7m.aircr = value & 1085 (R_V7M_AIRCR_SYSRESETREQS_MASK | 1086 R_V7M_AIRCR_BFHFNMINS_MASK | 1087 R_V7M_AIRCR_PRIS_MASK); 1088 /* BFHFNMINS changes the priority of Secure HardFault, and 1089 * allows a pending Non-secure HardFault to preempt (which 1090 * we implement by marking it enabled). 1091 */ 1092 if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) { 1093 s->sec_vectors[ARMV7M_EXCP_HARD].prio = -3; 1094 s->vectors[ARMV7M_EXCP_HARD].enabled = 1; 1095 } else { 1096 s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1; 1097 s->vectors[ARMV7M_EXCP_HARD].enabled = 0; 1098 } 1099 } 1100 nvic_irq_update(s); 1101 } 1102 break; 1103 case 0xd10: /* System Control. */ 1104 /* TODO: Implement control registers. */ 1105 qemu_log_mask(LOG_UNIMP, "NVIC: SCR unimplemented\n"); 1106 break; 1107 case 0xd14: /* Configuration Control. */ 1108 /* Enforce RAZ/WI on reserved and must-RAZ/WI bits */ 1109 value &= (R_V7M_CCR_STKALIGN_MASK | 1110 R_V7M_CCR_BFHFNMIGN_MASK | 1111 R_V7M_CCR_DIV_0_TRP_MASK | 1112 R_V7M_CCR_UNALIGN_TRP_MASK | 1113 R_V7M_CCR_USERSETMPEND_MASK | 1114 R_V7M_CCR_NONBASETHRDENA_MASK); 1115 1116 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1117 /* v8M makes NONBASETHRDENA and STKALIGN be RES1 */ 1118 value |= R_V7M_CCR_NONBASETHRDENA_MASK 1119 | R_V7M_CCR_STKALIGN_MASK; 1120 } 1121 if (attrs.secure) { 1122 /* the BFHFNMIGN bit is not banked; keep that in the NS copy */ 1123 cpu->env.v7m.ccr[M_REG_NS] = 1124 (cpu->env.v7m.ccr[M_REG_NS] & ~R_V7M_CCR_BFHFNMIGN_MASK) 1125 | (value & R_V7M_CCR_BFHFNMIGN_MASK); 1126 value &= ~R_V7M_CCR_BFHFNMIGN_MASK; 1127 } 1128 1129 cpu->env.v7m.ccr[attrs.secure] = value; 1130 break; 1131 case 0xd24: /* System Handler Control and State (SHCSR) */ 1132 if (attrs.secure) { 1133 s->sec_vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0; 1134 /* Secure HardFault active bit cannot be written */ 1135 s->sec_vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0; 1136 s->sec_vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0; 1137 s->sec_vectors[ARMV7M_EXCP_PENDSV].active = 1138 (value & (1 << 10)) != 0; 1139 s->sec_vectors[ARMV7M_EXCP_SYSTICK].active = 1140 (value & (1 << 11)) != 0; 1141 s->sec_vectors[ARMV7M_EXCP_USAGE].pending = 1142 (value & (1 << 12)) != 0; 1143 s->sec_vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0; 1144 s->sec_vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0; 1145 s->sec_vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0; 1146 s->sec_vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0; 1147 s->sec_vectors[ARMV7M_EXCP_USAGE].enabled = 1148 (value & (1 << 18)) != 0; 1149 /* SecureFault not banked, but RAZ/WI to NS */ 1150 s->vectors[ARMV7M_EXCP_SECURE].active = (value & (1 << 4)) != 0; 1151 s->vectors[ARMV7M_EXCP_SECURE].enabled = (value & (1 << 19)) != 0; 1152 s->vectors[ARMV7M_EXCP_SECURE].pending = (value & (1 << 20)) != 0; 1153 } else { 1154 s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0; 1155 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1156 /* HARDFAULTPENDED is not present in v7M */ 1157 s->vectors[ARMV7M_EXCP_HARD].pending = (value & (1 << 21)) != 0; 1158 } 1159 s->vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0; 1160 s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0; 1161 s->vectors[ARMV7M_EXCP_PENDSV].active = (value & (1 << 10)) != 0; 1162 s->vectors[ARMV7M_EXCP_SYSTICK].active = (value & (1 << 11)) != 0; 1163 s->vectors[ARMV7M_EXCP_USAGE].pending = (value & (1 << 12)) != 0; 1164 s->vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0; 1165 s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0; 1166 s->vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0; 1167 s->vectors[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0; 1168 } 1169 if (attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { 1170 s->vectors[ARMV7M_EXCP_BUS].active = (value & (1 << 1)) != 0; 1171 s->vectors[ARMV7M_EXCP_BUS].pending = (value & (1 << 14)) != 0; 1172 s->vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0; 1173 } 1174 /* NMIACT can only be written if the write is of a zero, with 1175 * BFHFNMINS 1, and by the CPU in secure state via the NS alias. 1176 */ 1177 if (!attrs.secure && cpu->env.v7m.secure && 1178 (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) && 1179 (value & (1 << 5)) == 0) { 1180 s->vectors[ARMV7M_EXCP_NMI].active = 0; 1181 } 1182 /* HARDFAULTACT can only be written if the write is of a zero 1183 * to the non-secure HardFault state by the CPU in secure state. 1184 * The only case where we can be targeting the non-secure HF state 1185 * when in secure state is if this is a write via the NS alias 1186 * and BFHFNMINS is 1. 1187 */ 1188 if (!attrs.secure && cpu->env.v7m.secure && 1189 (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) && 1190 (value & (1 << 2)) == 0) { 1191 s->vectors[ARMV7M_EXCP_HARD].active = 0; 1192 } 1193 1194 /* TODO: this is RAZ/WI from NS if DEMCR.SDME is set */ 1195 s->vectors[ARMV7M_EXCP_DEBUG].active = (value & (1 << 8)) != 0; 1196 nvic_irq_update(s); 1197 break; 1198 case 0xd28: /* Configurable Fault Status. */ 1199 cpu->env.v7m.cfsr[attrs.secure] &= ~value; /* W1C */ 1200 if (attrs.secure) { 1201 /* The BFSR bits [15:8] are shared between security states 1202 * and we store them in the NS copy. 1203 */ 1204 cpu->env.v7m.cfsr[M_REG_NS] &= ~(value & R_V7M_CFSR_BFSR_MASK); 1205 } 1206 break; 1207 case 0xd2c: /* Hard Fault Status. */ 1208 cpu->env.v7m.hfsr &= ~value; /* W1C */ 1209 break; 1210 case 0xd30: /* Debug Fault Status. */ 1211 cpu->env.v7m.dfsr &= ~value; /* W1C */ 1212 break; 1213 case 0xd34: /* Mem Manage Address. */ 1214 cpu->env.v7m.mmfar[attrs.secure] = value; 1215 return; 1216 case 0xd38: /* Bus Fault Address. */ 1217 cpu->env.v7m.bfar = value; 1218 return; 1219 case 0xd3c: /* Aux Fault Status. */ 1220 qemu_log_mask(LOG_UNIMP, 1221 "NVIC: Aux fault status registers unimplemented\n"); 1222 break; 1223 case 0xd90: /* MPU_TYPE */ 1224 return; /* RO */ 1225 case 0xd94: /* MPU_CTRL */ 1226 if ((value & 1227 (R_V7M_MPU_CTRL_HFNMIENA_MASK | R_V7M_MPU_CTRL_ENABLE_MASK)) 1228 == R_V7M_MPU_CTRL_HFNMIENA_MASK) { 1229 qemu_log_mask(LOG_GUEST_ERROR, "MPU_CTRL: HFNMIENA and !ENABLE is " 1230 "UNPREDICTABLE\n"); 1231 } 1232 cpu->env.v7m.mpu_ctrl[attrs.secure] 1233 = value & (R_V7M_MPU_CTRL_ENABLE_MASK | 1234 R_V7M_MPU_CTRL_HFNMIENA_MASK | 1235 R_V7M_MPU_CTRL_PRIVDEFENA_MASK); 1236 tlb_flush(CPU(cpu)); 1237 break; 1238 case 0xd98: /* MPU_RNR */ 1239 if (value >= cpu->pmsav7_dregion) { 1240 qemu_log_mask(LOG_GUEST_ERROR, "MPU region out of range %" 1241 PRIu32 "/%" PRIu32 "\n", 1242 value, cpu->pmsav7_dregion); 1243 } else { 1244 cpu->env.pmsav7.rnr[attrs.secure] = value; 1245 } 1246 break; 1247 case 0xd9c: /* MPU_RBAR */ 1248 case 0xda4: /* MPU_RBAR_A1 */ 1249 case 0xdac: /* MPU_RBAR_A2 */ 1250 case 0xdb4: /* MPU_RBAR_A3 */ 1251 { 1252 int region; 1253 1254 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1255 /* PMSAv8M handling of the aliases is different from v7M: 1256 * aliases A1, A2, A3 override the low two bits of the region 1257 * number in MPU_RNR, and there is no 'region' field in the 1258 * RBAR register. 1259 */ 1260 int aliasno = (offset - 0xd9c) / 8; /* 0..3 */ 1261 1262 region = cpu->env.pmsav7.rnr[attrs.secure]; 1263 if (aliasno) { 1264 region = deposit32(region, 0, 2, aliasno); 1265 } 1266 if (region >= cpu->pmsav7_dregion) { 1267 return; 1268 } 1269 cpu->env.pmsav8.rbar[attrs.secure][region] = value; 1270 tlb_flush(CPU(cpu)); 1271 return; 1272 } 1273 1274 if (value & (1 << 4)) { 1275 /* VALID bit means use the region number specified in this 1276 * value and also update MPU_RNR.REGION with that value. 1277 */ 1278 region = extract32(value, 0, 4); 1279 if (region >= cpu->pmsav7_dregion) { 1280 qemu_log_mask(LOG_GUEST_ERROR, 1281 "MPU region out of range %u/%" PRIu32 "\n", 1282 region, cpu->pmsav7_dregion); 1283 return; 1284 } 1285 cpu->env.pmsav7.rnr[attrs.secure] = region; 1286 } else { 1287 region = cpu->env.pmsav7.rnr[attrs.secure]; 1288 } 1289 1290 if (region >= cpu->pmsav7_dregion) { 1291 return; 1292 } 1293 1294 cpu->env.pmsav7.drbar[region] = value & ~0x1f; 1295 tlb_flush(CPU(cpu)); 1296 break; 1297 } 1298 case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */ 1299 case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */ 1300 case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */ 1301 case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */ 1302 { 1303 int region = cpu->env.pmsav7.rnr[attrs.secure]; 1304 1305 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1306 /* PMSAv8M handling of the aliases is different from v7M: 1307 * aliases A1, A2, A3 override the low two bits of the region 1308 * number in MPU_RNR. 1309 */ 1310 int aliasno = (offset - 0xd9c) / 8; /* 0..3 */ 1311 1312 region = cpu->env.pmsav7.rnr[attrs.secure]; 1313 if (aliasno) { 1314 region = deposit32(region, 0, 2, aliasno); 1315 } 1316 if (region >= cpu->pmsav7_dregion) { 1317 return; 1318 } 1319 cpu->env.pmsav8.rlar[attrs.secure][region] = value; 1320 tlb_flush(CPU(cpu)); 1321 return; 1322 } 1323 1324 if (region >= cpu->pmsav7_dregion) { 1325 return; 1326 } 1327 1328 cpu->env.pmsav7.drsr[region] = value & 0xff3f; 1329 cpu->env.pmsav7.dracr[region] = (value >> 16) & 0x173f; 1330 tlb_flush(CPU(cpu)); 1331 break; 1332 } 1333 case 0xdc0: /* MPU_MAIR0 */ 1334 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1335 goto bad_offset; 1336 } 1337 if (cpu->pmsav7_dregion) { 1338 /* Register is RES0 if no MPU regions are implemented */ 1339 cpu->env.pmsav8.mair0[attrs.secure] = value; 1340 } 1341 /* We don't need to do anything else because memory attributes 1342 * only affect cacheability, and we don't implement caching. 1343 */ 1344 break; 1345 case 0xdc4: /* MPU_MAIR1 */ 1346 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1347 goto bad_offset; 1348 } 1349 if (cpu->pmsav7_dregion) { 1350 /* Register is RES0 if no MPU regions are implemented */ 1351 cpu->env.pmsav8.mair1[attrs.secure] = value; 1352 } 1353 /* We don't need to do anything else because memory attributes 1354 * only affect cacheability, and we don't implement caching. 1355 */ 1356 break; 1357 case 0xf00: /* Software Triggered Interrupt Register */ 1358 { 1359 int excnum = (value & 0x1ff) + NVIC_FIRST_IRQ; 1360 if (excnum < s->num_irq) { 1361 armv7m_nvic_set_pending(s, excnum, false); 1362 } 1363 break; 1364 } 1365 default: 1366 bad_offset: 1367 qemu_log_mask(LOG_GUEST_ERROR, 1368 "NVIC: Bad write offset 0x%x\n", offset); 1369 } 1370 } 1371 1372 static bool nvic_user_access_ok(NVICState *s, hwaddr offset, MemTxAttrs attrs) 1373 { 1374 /* Return true if unprivileged access to this register is permitted. */ 1375 switch (offset) { 1376 case 0xf00: /* STIR: accessible only if CCR.USERSETMPEND permits */ 1377 /* For access via STIR_NS it is the NS CCR.USERSETMPEND that 1378 * controls access even though the CPU is in Secure state (I_QDKX). 1379 */ 1380 return s->cpu->env.v7m.ccr[attrs.secure] & R_V7M_CCR_USERSETMPEND_MASK; 1381 default: 1382 /* All other user accesses cause a BusFault unconditionally */ 1383 return false; 1384 } 1385 } 1386 1387 static int shpr_bank(NVICState *s, int exc, MemTxAttrs attrs) 1388 { 1389 /* Behaviour for the SHPR register field for this exception: 1390 * return M_REG_NS to use the nonsecure vector (including for 1391 * non-banked exceptions), M_REG_S for the secure version of 1392 * a banked exception, and -1 if this field should RAZ/WI. 1393 */ 1394 switch (exc) { 1395 case ARMV7M_EXCP_MEM: 1396 case ARMV7M_EXCP_USAGE: 1397 case ARMV7M_EXCP_SVC: 1398 case ARMV7M_EXCP_PENDSV: 1399 case ARMV7M_EXCP_SYSTICK: 1400 /* Banked exceptions */ 1401 return attrs.secure; 1402 case ARMV7M_EXCP_BUS: 1403 /* Not banked, RAZ/WI from nonsecure if BFHFNMINS is zero */ 1404 if (!attrs.secure && 1405 !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { 1406 return -1; 1407 } 1408 return M_REG_NS; 1409 case ARMV7M_EXCP_SECURE: 1410 /* Not banked, RAZ/WI from nonsecure */ 1411 if (!attrs.secure) { 1412 return -1; 1413 } 1414 return M_REG_NS; 1415 case ARMV7M_EXCP_DEBUG: 1416 /* Not banked. TODO should RAZ/WI if DEMCR.SDME is set */ 1417 return M_REG_NS; 1418 case 8 ... 10: 1419 case 13: 1420 /* RES0 */ 1421 return -1; 1422 default: 1423 /* Not reachable due to decode of SHPR register addresses */ 1424 g_assert_not_reached(); 1425 } 1426 } 1427 1428 static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, 1429 uint64_t *data, unsigned size, 1430 MemTxAttrs attrs) 1431 { 1432 NVICState *s = (NVICState *)opaque; 1433 uint32_t offset = addr; 1434 unsigned i, startvec, end; 1435 uint32_t val; 1436 1437 if (attrs.user && !nvic_user_access_ok(s, addr, attrs)) { 1438 /* Generate BusFault for unprivileged accesses */ 1439 return MEMTX_ERROR; 1440 } 1441 1442 switch (offset) { 1443 /* reads of set and clear both return the status */ 1444 case 0x100 ... 0x13f: /* NVIC Set enable */ 1445 offset += 0x80; 1446 /* fall through */ 1447 case 0x180 ... 0x1bf: /* NVIC Clear enable */ 1448 val = 0; 1449 startvec = offset - 0x180 + NVIC_FIRST_IRQ; /* vector # */ 1450 1451 for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { 1452 if (s->vectors[startvec + i].enabled && 1453 (attrs.secure || s->itns[startvec + i])) { 1454 val |= (1 << i); 1455 } 1456 } 1457 break; 1458 case 0x200 ... 0x23f: /* NVIC Set pend */ 1459 offset += 0x80; 1460 /* fall through */ 1461 case 0x280 ... 0x2bf: /* NVIC Clear pend */ 1462 val = 0; 1463 startvec = offset - 0x280 + NVIC_FIRST_IRQ; /* vector # */ 1464 for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { 1465 if (s->vectors[startvec + i].pending && 1466 (attrs.secure || s->itns[startvec + i])) { 1467 val |= (1 << i); 1468 } 1469 } 1470 break; 1471 case 0x300 ... 0x33f: /* NVIC Active */ 1472 val = 0; 1473 startvec = offset - 0x300 + NVIC_FIRST_IRQ; /* vector # */ 1474 1475 for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { 1476 if (s->vectors[startvec + i].active && 1477 (attrs.secure || s->itns[startvec + i])) { 1478 val |= (1 << i); 1479 } 1480 } 1481 break; 1482 case 0x400 ... 0x5ef: /* NVIC Priority */ 1483 val = 0; 1484 startvec = offset - 0x400 + NVIC_FIRST_IRQ; /* vector # */ 1485 1486 for (i = 0; i < size && startvec + i < s->num_irq; i++) { 1487 if (attrs.secure || s->itns[startvec + i]) { 1488 val |= s->vectors[startvec + i].prio << (8 * i); 1489 } 1490 } 1491 break; 1492 case 0xd18 ... 0xd23: /* System Handler Priority (SHPR1, SHPR2, SHPR3) */ 1493 val = 0; 1494 for (i = 0; i < size; i++) { 1495 unsigned hdlidx = (offset - 0xd14) + i; 1496 int sbank = shpr_bank(s, hdlidx, attrs); 1497 1498 if (sbank < 0) { 1499 continue; 1500 } 1501 val = deposit32(val, i * 8, 8, get_prio(s, hdlidx, sbank)); 1502 } 1503 break; 1504 case 0xfe0 ... 0xfff: /* ID. */ 1505 if (offset & 3) { 1506 val = 0; 1507 } else { 1508 val = nvic_id[(offset - 0xfe0) >> 2]; 1509 } 1510 break; 1511 default: 1512 if (size == 4) { 1513 val = nvic_readl(s, offset, attrs); 1514 } else { 1515 qemu_log_mask(LOG_GUEST_ERROR, 1516 "NVIC: Bad read of size %d at offset 0x%x\n", 1517 size, offset); 1518 val = 0; 1519 } 1520 } 1521 1522 trace_nvic_sysreg_read(addr, val, size); 1523 *data = val; 1524 return MEMTX_OK; 1525 } 1526 1527 static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, 1528 uint64_t value, unsigned size, 1529 MemTxAttrs attrs) 1530 { 1531 NVICState *s = (NVICState *)opaque; 1532 uint32_t offset = addr; 1533 unsigned i, startvec, end; 1534 unsigned setval = 0; 1535 1536 trace_nvic_sysreg_write(addr, value, size); 1537 1538 if (attrs.user && !nvic_user_access_ok(s, addr, attrs)) { 1539 /* Generate BusFault for unprivileged accesses */ 1540 return MEMTX_ERROR; 1541 } 1542 1543 switch (offset) { 1544 case 0x100 ... 0x13f: /* NVIC Set enable */ 1545 offset += 0x80; 1546 setval = 1; 1547 /* fall through */ 1548 case 0x180 ... 0x1bf: /* NVIC Clear enable */ 1549 startvec = 8 * (offset - 0x180) + NVIC_FIRST_IRQ; 1550 1551 for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { 1552 if (value & (1 << i) && 1553 (attrs.secure || s->itns[startvec + i])) { 1554 s->vectors[startvec + i].enabled = setval; 1555 } 1556 } 1557 nvic_irq_update(s); 1558 return MEMTX_OK; 1559 case 0x200 ... 0x23f: /* NVIC Set pend */ 1560 /* the special logic in armv7m_nvic_set_pending() 1561 * is not needed since IRQs are never escalated 1562 */ 1563 offset += 0x80; 1564 setval = 1; 1565 /* fall through */ 1566 case 0x280 ... 0x2bf: /* NVIC Clear pend */ 1567 startvec = 8 * (offset - 0x280) + NVIC_FIRST_IRQ; /* vector # */ 1568 1569 for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { 1570 if (value & (1 << i) && 1571 (attrs.secure || s->itns[startvec + i])) { 1572 s->vectors[startvec + i].pending = setval; 1573 } 1574 } 1575 nvic_irq_update(s); 1576 return MEMTX_OK; 1577 case 0x300 ... 0x33f: /* NVIC Active */ 1578 return MEMTX_OK; /* R/O */ 1579 case 0x400 ... 0x5ef: /* NVIC Priority */ 1580 startvec = 8 * (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */ 1581 1582 for (i = 0; i < size && startvec + i < s->num_irq; i++) { 1583 if (attrs.secure || s->itns[startvec + i]) { 1584 set_prio(s, startvec + i, false, (value >> (i * 8)) & 0xff); 1585 } 1586 } 1587 nvic_irq_update(s); 1588 return MEMTX_OK; 1589 case 0xd18 ... 0xd23: /* System Handler Priority (SHPR1, SHPR2, SHPR3) */ 1590 for (i = 0; i < size; i++) { 1591 unsigned hdlidx = (offset - 0xd14) + i; 1592 int newprio = extract32(value, i * 8, 8); 1593 int sbank = shpr_bank(s, hdlidx, attrs); 1594 1595 if (sbank < 0) { 1596 continue; 1597 } 1598 set_prio(s, hdlidx, sbank, newprio); 1599 } 1600 nvic_irq_update(s); 1601 return MEMTX_OK; 1602 } 1603 if (size == 4) { 1604 nvic_writel(s, offset, value, attrs); 1605 return MEMTX_OK; 1606 } 1607 qemu_log_mask(LOG_GUEST_ERROR, 1608 "NVIC: Bad write of size %d at offset 0x%x\n", size, offset); 1609 /* This is UNPREDICTABLE; treat as RAZ/WI */ 1610 return MEMTX_OK; 1611 } 1612 1613 static const MemoryRegionOps nvic_sysreg_ops = { 1614 .read_with_attrs = nvic_sysreg_read, 1615 .write_with_attrs = nvic_sysreg_write, 1616 .endianness = DEVICE_NATIVE_ENDIAN, 1617 }; 1618 1619 static MemTxResult nvic_sysreg_ns_write(void *opaque, hwaddr addr, 1620 uint64_t value, unsigned size, 1621 MemTxAttrs attrs) 1622 { 1623 if (attrs.secure) { 1624 /* S accesses to the alias act like NS accesses to the real region */ 1625 attrs.secure = 0; 1626 return nvic_sysreg_write(opaque, addr, value, size, attrs); 1627 } else { 1628 /* NS attrs are RAZ/WI for privileged, and BusFault for user */ 1629 if (attrs.user) { 1630 return MEMTX_ERROR; 1631 } 1632 return MEMTX_OK; 1633 } 1634 } 1635 1636 static MemTxResult nvic_sysreg_ns_read(void *opaque, hwaddr addr, 1637 uint64_t *data, unsigned size, 1638 MemTxAttrs attrs) 1639 { 1640 if (attrs.secure) { 1641 /* S accesses to the alias act like NS accesses to the real region */ 1642 attrs.secure = 0; 1643 return nvic_sysreg_read(opaque, addr, data, size, attrs); 1644 } else { 1645 /* NS attrs are RAZ/WI for privileged, and BusFault for user */ 1646 if (attrs.user) { 1647 return MEMTX_ERROR; 1648 } 1649 *data = 0; 1650 return MEMTX_OK; 1651 } 1652 } 1653 1654 static const MemoryRegionOps nvic_sysreg_ns_ops = { 1655 .read_with_attrs = nvic_sysreg_ns_read, 1656 .write_with_attrs = nvic_sysreg_ns_write, 1657 .endianness = DEVICE_NATIVE_ENDIAN, 1658 }; 1659 1660 static int nvic_post_load(void *opaque, int version_id) 1661 { 1662 NVICState *s = opaque; 1663 unsigned i; 1664 int resetprio; 1665 1666 /* Check for out of range priority settings */ 1667 resetprio = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? -4 : -3; 1668 1669 if (s->vectors[ARMV7M_EXCP_RESET].prio != resetprio || 1670 s->vectors[ARMV7M_EXCP_NMI].prio != -2 || 1671 s->vectors[ARMV7M_EXCP_HARD].prio != -1) { 1672 return 1; 1673 } 1674 for (i = ARMV7M_EXCP_MEM; i < s->num_irq; i++) { 1675 if (s->vectors[i].prio & ~0xff) { 1676 return 1; 1677 } 1678 } 1679 1680 nvic_recompute_state(s); 1681 1682 return 0; 1683 } 1684 1685 static const VMStateDescription vmstate_VecInfo = { 1686 .name = "armv7m_nvic_info", 1687 .version_id = 1, 1688 .minimum_version_id = 1, 1689 .fields = (VMStateField[]) { 1690 VMSTATE_INT16(prio, VecInfo), 1691 VMSTATE_UINT8(enabled, VecInfo), 1692 VMSTATE_UINT8(pending, VecInfo), 1693 VMSTATE_UINT8(active, VecInfo), 1694 VMSTATE_UINT8(level, VecInfo), 1695 VMSTATE_END_OF_LIST() 1696 } 1697 }; 1698 1699 static bool nvic_security_needed(void *opaque) 1700 { 1701 NVICState *s = opaque; 1702 1703 return arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY); 1704 } 1705 1706 static int nvic_security_post_load(void *opaque, int version_id) 1707 { 1708 NVICState *s = opaque; 1709 int i; 1710 1711 /* Check for out of range priority settings */ 1712 if (s->sec_vectors[ARMV7M_EXCP_HARD].prio != -1 1713 && s->sec_vectors[ARMV7M_EXCP_HARD].prio != -3) { 1714 /* We can't cross-check against AIRCR.BFHFNMINS as we don't know 1715 * if the CPU state has been migrated yet; a mismatch won't 1716 * cause the emulation to blow up, though. 1717 */ 1718 return 1; 1719 } 1720 for (i = ARMV7M_EXCP_MEM; i < ARRAY_SIZE(s->sec_vectors); i++) { 1721 if (s->sec_vectors[i].prio & ~0xff) { 1722 return 1; 1723 } 1724 } 1725 return 0; 1726 } 1727 1728 static const VMStateDescription vmstate_nvic_security = { 1729 .name = "nvic/m-security", 1730 .version_id = 1, 1731 .minimum_version_id = 1, 1732 .needed = nvic_security_needed, 1733 .post_load = &nvic_security_post_load, 1734 .fields = (VMStateField[]) { 1735 VMSTATE_STRUCT_ARRAY(sec_vectors, NVICState, NVIC_INTERNAL_VECTORS, 1, 1736 vmstate_VecInfo, VecInfo), 1737 VMSTATE_UINT32(prigroup[M_REG_S], NVICState), 1738 VMSTATE_BOOL_ARRAY(itns, NVICState, NVIC_MAX_VECTORS), 1739 VMSTATE_END_OF_LIST() 1740 } 1741 }; 1742 1743 static const VMStateDescription vmstate_nvic = { 1744 .name = "armv7m_nvic", 1745 .version_id = 4, 1746 .minimum_version_id = 4, 1747 .post_load = &nvic_post_load, 1748 .fields = (VMStateField[]) { 1749 VMSTATE_STRUCT_ARRAY(vectors, NVICState, NVIC_MAX_VECTORS, 1, 1750 vmstate_VecInfo, VecInfo), 1751 VMSTATE_UINT32(prigroup[M_REG_NS], NVICState), 1752 VMSTATE_END_OF_LIST() 1753 }, 1754 .subsections = (const VMStateDescription*[]) { 1755 &vmstate_nvic_security, 1756 NULL 1757 } 1758 }; 1759 1760 static Property props_nvic[] = { 1761 /* Number of external IRQ lines (so excluding the 16 internal exceptions) */ 1762 DEFINE_PROP_UINT32("num-irq", NVICState, num_irq, 64), 1763 DEFINE_PROP_END_OF_LIST() 1764 }; 1765 1766 static void armv7m_nvic_reset(DeviceState *dev) 1767 { 1768 int resetprio; 1769 NVICState *s = NVIC(dev); 1770 1771 s->vectors[ARMV7M_EXCP_NMI].enabled = 1; 1772 /* MEM, BUS, and USAGE are enabled through 1773 * the System Handler Control register 1774 */ 1775 s->vectors[ARMV7M_EXCP_SVC].enabled = 1; 1776 s->vectors[ARMV7M_EXCP_DEBUG].enabled = 1; 1777 s->vectors[ARMV7M_EXCP_PENDSV].enabled = 1; 1778 s->vectors[ARMV7M_EXCP_SYSTICK].enabled = 1; 1779 1780 resetprio = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? -4 : -3; 1781 s->vectors[ARMV7M_EXCP_RESET].prio = resetprio; 1782 s->vectors[ARMV7M_EXCP_NMI].prio = -2; 1783 s->vectors[ARMV7M_EXCP_HARD].prio = -1; 1784 1785 if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) { 1786 s->sec_vectors[ARMV7M_EXCP_HARD].enabled = 1; 1787 s->sec_vectors[ARMV7M_EXCP_SVC].enabled = 1; 1788 s->sec_vectors[ARMV7M_EXCP_PENDSV].enabled = 1; 1789 s->sec_vectors[ARMV7M_EXCP_SYSTICK].enabled = 1; 1790 1791 /* AIRCR.BFHFNMINS resets to 0 so Secure HF is priority -1 (R_CMTC) */ 1792 s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1; 1793 /* If AIRCR.BFHFNMINS is 0 then NS HF is (effectively) disabled */ 1794 s->vectors[ARMV7M_EXCP_HARD].enabled = 0; 1795 } else { 1796 s->vectors[ARMV7M_EXCP_HARD].enabled = 1; 1797 } 1798 1799 /* Strictly speaking the reset handler should be enabled. 1800 * However, we don't simulate soft resets through the NVIC, 1801 * and the reset vector should never be pended. 1802 * So we leave it disabled to catch logic errors. 1803 */ 1804 1805 s->exception_prio = NVIC_NOEXC_PRIO; 1806 s->vectpending = 0; 1807 s->vectpending_is_s_banked = false; 1808 s->vectpending_prio = NVIC_NOEXC_PRIO; 1809 1810 if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) { 1811 memset(s->itns, 0, sizeof(s->itns)); 1812 } else { 1813 /* This state is constant and not guest accessible in a non-security 1814 * NVIC; we set the bits to true to avoid having to do a feature 1815 * bit check in the NVIC enable/pend/etc register accessors. 1816 */ 1817 int i; 1818 1819 for (i = NVIC_FIRST_IRQ; i < ARRAY_SIZE(s->itns); i++) { 1820 s->itns[i] = true; 1821 } 1822 } 1823 } 1824 1825 static void nvic_systick_trigger(void *opaque, int n, int level) 1826 { 1827 NVICState *s = opaque; 1828 1829 if (level) { 1830 /* SysTick just asked us to pend its exception. 1831 * (This is different from an external interrupt line's 1832 * behaviour.) 1833 * TODO: when we implement the banked systicks we must make 1834 * this pend the correct banked exception. 1835 */ 1836 armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, false); 1837 } 1838 } 1839 1840 static void armv7m_nvic_realize(DeviceState *dev, Error **errp) 1841 { 1842 NVICState *s = NVIC(dev); 1843 SysBusDevice *systick_sbd; 1844 Error *err = NULL; 1845 int regionlen; 1846 1847 s->cpu = ARM_CPU(qemu_get_cpu(0)); 1848 assert(s->cpu); 1849 1850 if (s->num_irq > NVIC_MAX_IRQ) { 1851 error_setg(errp, "num-irq %d exceeds NVIC maximum", s->num_irq); 1852 return; 1853 } 1854 1855 qdev_init_gpio_in(dev, set_irq_level, s->num_irq); 1856 1857 /* include space for internal exception vectors */ 1858 s->num_irq += NVIC_FIRST_IRQ; 1859 1860 object_property_set_bool(OBJECT(&s->systick), true, "realized", &err); 1861 if (err != NULL) { 1862 error_propagate(errp, err); 1863 return; 1864 } 1865 systick_sbd = SYS_BUS_DEVICE(&s->systick); 1866 sysbus_connect_irq(systick_sbd, 0, 1867 qdev_get_gpio_in_named(dev, "systick-trigger", 0)); 1868 1869 /* The NVIC and System Control Space (SCS) starts at 0xe000e000 1870 * and looks like this: 1871 * 0x004 - ICTR 1872 * 0x010 - 0xff - systick 1873 * 0x100..0x7ec - NVIC 1874 * 0x7f0..0xcff - Reserved 1875 * 0xd00..0xd3c - SCS registers 1876 * 0xd40..0xeff - Reserved or Not implemented 1877 * 0xf00 - STIR 1878 * 1879 * Some registers within this space are banked between security states. 1880 * In v8M there is a second range 0xe002e000..0xe002efff which is the 1881 * NonSecure alias SCS; secure accesses to this behave like NS accesses 1882 * to the main SCS range, and non-secure accesses (including when 1883 * the security extension is not implemented) are RAZ/WI. 1884 * Note that both the main SCS range and the alias range are defined 1885 * to be exempt from memory attribution (R_BLJT) and so the memory 1886 * transaction attribute always matches the current CPU security 1887 * state (attrs.secure == env->v7m.secure). In the nvic_sysreg_ns_ops 1888 * wrappers we change attrs.secure to indicate the NS access; so 1889 * generally code determining which banked register to use should 1890 * use attrs.secure; code determining actual behaviour of the system 1891 * should use env->v7m.secure. 1892 */ 1893 regionlen = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? 0x21000 : 0x1000; 1894 memory_region_init(&s->container, OBJECT(s), "nvic", regionlen); 1895 /* The system register region goes at the bottom of the priority 1896 * stack as it covers the whole page. 1897 */ 1898 memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s, 1899 "nvic_sysregs", 0x1000); 1900 memory_region_add_subregion(&s->container, 0, &s->sysregmem); 1901 memory_region_add_subregion_overlap(&s->container, 0x10, 1902 sysbus_mmio_get_region(systick_sbd, 0), 1903 1); 1904 1905 if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) { 1906 memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s), 1907 &nvic_sysreg_ns_ops, s, 1908 "nvic_sysregs_ns", 0x1000); 1909 memory_region_add_subregion(&s->container, 0x20000, &s->sysreg_ns_mem); 1910 } 1911 1912 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container); 1913 } 1914 1915 static void armv7m_nvic_instance_init(Object *obj) 1916 { 1917 /* We have a different default value for the num-irq property 1918 * than our superclass. This function runs after qdev init 1919 * has set the defaults from the Property array and before 1920 * any user-specified property setting, so just modify the 1921 * value in the GICState struct. 1922 */ 1923 DeviceState *dev = DEVICE(obj); 1924 NVICState *nvic = NVIC(obj); 1925 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1926 1927 object_initialize(&nvic->systick, sizeof(nvic->systick), TYPE_SYSTICK); 1928 qdev_set_parent_bus(DEVICE(&nvic->systick), sysbus_get_default()); 1929 1930 sysbus_init_irq(sbd, &nvic->excpout); 1931 qdev_init_gpio_out_named(dev, &nvic->sysresetreq, "SYSRESETREQ", 1); 1932 qdev_init_gpio_in_named(dev, nvic_systick_trigger, "systick-trigger", 1); 1933 } 1934 1935 static void armv7m_nvic_class_init(ObjectClass *klass, void *data) 1936 { 1937 DeviceClass *dc = DEVICE_CLASS(klass); 1938 1939 dc->vmsd = &vmstate_nvic; 1940 dc->props = props_nvic; 1941 dc->reset = armv7m_nvic_reset; 1942 dc->realize = armv7m_nvic_realize; 1943 } 1944 1945 static const TypeInfo armv7m_nvic_info = { 1946 .name = TYPE_NVIC, 1947 .parent = TYPE_SYS_BUS_DEVICE, 1948 .instance_init = armv7m_nvic_instance_init, 1949 .instance_size = sizeof(NVICState), 1950 .class_init = armv7m_nvic_class_init, 1951 .class_size = sizeof(SysBusDeviceClass), 1952 }; 1953 1954 static void armv7m_nvic_register_types(void) 1955 { 1956 type_register_static(&armv7m_nvic_info); 1957 } 1958 1959 type_init(armv7m_nvic_register_types) 1960