1 /* 2 * ARM Generic Interrupt Controller using KVM in-kernel support 3 * 4 * Copyright (c) 2015 Samsung Electronics Co., Ltd. 5 * Written by Pavel Fedin 6 * Based on vGICv2 code by Peter Maydell 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation, either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "hw/intc/arm_gicv3_common.h" 25 #include "hw/arm/virt.h" 26 #include "qemu/error-report.h" 27 #include "qemu/module.h" 28 #include "system/kvm.h" 29 #include "system/runstate.h" 30 #include "kvm_arm.h" 31 #include "gicv3_internal.h" 32 #include "vgic_common.h" 33 #include "migration/blocker.h" 34 #include "migration/misc.h" 35 #include "qom/object.h" 36 #include "target/arm/cpregs.h" 37 38 39 #ifdef DEBUG_GICV3_KVM 40 #define DPRINTF(fmt, ...) \ 41 do { fprintf(stderr, "kvm_gicv3: " fmt, ## __VA_ARGS__); } while (0) 42 #else 43 #define DPRINTF(fmt, ...) \ 44 do { } while (0) 45 #endif 46 47 #define TYPE_KVM_ARM_GICV3 "kvm-arm-gicv3" 48 typedef struct KVMARMGICv3Class KVMARMGICv3Class; 49 /* This is reusing the GICv3State typedef from ARM_GICV3_ITS_COMMON */ 50 DECLARE_OBJ_CHECKERS(GICv3State, KVMARMGICv3Class, 51 KVM_ARM_GICV3, TYPE_KVM_ARM_GICV3) 52 53 #define KVM_DEV_ARM_VGIC_SYSREG(op0, op1, crn, crm, op2) \ 54 (ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \ 55 ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \ 56 ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \ 57 ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \ 58 ARM64_SYS_REG_SHIFT_MASK(op2, OP2)) 59 60 #define ICC_PMR_EL1 \ 61 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 4, 6, 0) 62 #define ICC_BPR0_EL1 \ 63 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 8, 3) 64 #define ICC_AP0R_EL1(n) \ 65 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 8, 4 | n) 66 #define ICC_AP1R_EL1(n) \ 67 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 9, n) 68 #define ICC_BPR1_EL1 \ 69 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 3) 70 #define ICC_CTLR_EL1 \ 71 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 4) 72 #define ICC_SRE_EL1 \ 73 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 5) 74 #define ICC_IGRPEN0_EL1 \ 75 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 6) 76 #define ICC_IGRPEN1_EL1 \ 77 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 7) 78 79 struct KVMARMGICv3Class { 80 ARMGICv3CommonClass parent_class; 81 DeviceRealize parent_realize; 82 ResettablePhases parent_phases; 83 }; 84 85 static void kvm_arm_gicv3_set_irq(void *opaque, int irq, int level) 86 { 87 GICv3State *s = (GICv3State *)opaque; 88 89 kvm_arm_gic_set_irq(s->num_irq, irq, level); 90 } 91 92 #define KVM_VGIC_ATTR(reg, typer) \ 93 ((typer & KVM_DEV_ARM_VGIC_V3_MPIDR_MASK) | (reg)) 94 95 static inline void kvm_gicd_access(GICv3State *s, int offset, 96 uint32_t *val, bool write) 97 { 98 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS, 99 KVM_VGIC_ATTR(offset, 0), 100 val, write, &error_abort); 101 } 102 103 static inline void kvm_gicr_access(GICv3State *s, int offset, int cpu, 104 uint32_t *val, bool write) 105 { 106 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS, 107 KVM_VGIC_ATTR(offset, s->cpu[cpu].gicr_typer), 108 val, write, &error_abort); 109 } 110 111 static inline void kvm_gicc_access(GICv3State *s, uint64_t reg, int cpu, 112 uint64_t *val, bool write) 113 { 114 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, 115 KVM_VGIC_ATTR(reg, s->cpu[cpu].gicr_typer), 116 val, write, &error_abort); 117 } 118 119 static inline void kvm_gic_line_level_access(GICv3State *s, int irq, int cpu, 120 uint32_t *val, bool write) 121 { 122 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO, 123 KVM_VGIC_ATTR(irq, s->cpu[cpu].gicr_typer) | 124 (VGIC_LEVEL_INFO_LINE_LEVEL << 125 KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT), 126 val, write, &error_abort); 127 } 128 129 /* Loop through each distributor IRQ related register; since bits 130 * corresponding to SPIs and PPIs are RAZ/WI when affinity routing 131 * is enabled, we skip those. 132 */ 133 #define for_each_dist_irq_reg(_irq, _max, _field_width) \ 134 for (_irq = GIC_INTERNAL; _irq < _max; _irq += (32 / _field_width)) 135 136 static void kvm_dist_get_priority(GICv3State *s, uint32_t offset, uint8_t *bmp) 137 { 138 uint32_t reg, *field; 139 int irq; 140 141 /* For the KVM GICv3, affinity routing is always enabled, and the first 8 142 * GICD_IPRIORITYR<n> registers are always RAZ/WI. The corresponding 143 * functionality is replaced by GICR_IPRIORITYR<n>. It doesn't need to 144 * sync them. So it needs to skip the field of GIC_INTERNAL irqs in bmp and 145 * offset. 146 */ 147 field = (uint32_t *)(bmp + GIC_INTERNAL); 148 offset += (GIC_INTERNAL * 8) / 8; 149 for_each_dist_irq_reg(irq, s->num_irq, 8) { 150 kvm_gicd_access(s, offset, ®, false); 151 *field = reg; 152 offset += 4; 153 field++; 154 } 155 } 156 157 static void kvm_dist_put_priority(GICv3State *s, uint32_t offset, uint8_t *bmp) 158 { 159 uint32_t reg, *field; 160 int irq; 161 162 /* For the KVM GICv3, affinity routing is always enabled, and the first 8 163 * GICD_IPRIORITYR<n> registers are always RAZ/WI. The corresponding 164 * functionality is replaced by GICR_IPRIORITYR<n>. It doesn't need to 165 * sync them. So it needs to skip the field of GIC_INTERNAL irqs in bmp and 166 * offset. 167 */ 168 field = (uint32_t *)(bmp + GIC_INTERNAL); 169 offset += (GIC_INTERNAL * 8) / 8; 170 for_each_dist_irq_reg(irq, s->num_irq, 8) { 171 reg = *field; 172 kvm_gicd_access(s, offset, ®, true); 173 offset += 4; 174 field++; 175 } 176 } 177 178 static void kvm_dist_get_edge_trigger(GICv3State *s, uint32_t offset, 179 uint32_t *bmp) 180 { 181 uint32_t reg; 182 int irq; 183 184 /* For the KVM GICv3, affinity routing is always enabled, and the first 2 185 * GICD_ICFGR<n> registers are always RAZ/WI. The corresponding 186 * functionality is replaced by GICR_ICFGR<n>. It doesn't need to sync 187 * them. So it should increase the offset to skip GIC_INTERNAL irqs. 188 * This matches the for_each_dist_irq_reg() macro which also skips the 189 * first GIC_INTERNAL irqs. 190 */ 191 offset += (GIC_INTERNAL * 2) / 8; 192 for_each_dist_irq_reg(irq, s->num_irq, 2) { 193 kvm_gicd_access(s, offset, ®, false); 194 reg = half_unshuffle32(reg >> 1); 195 if (irq % 32 != 0) { 196 reg = (reg << 16); 197 } 198 *gic_bmp_ptr32(bmp, irq) |= reg; 199 offset += 4; 200 } 201 } 202 203 static void kvm_dist_put_edge_trigger(GICv3State *s, uint32_t offset, 204 uint32_t *bmp) 205 { 206 uint32_t reg; 207 int irq; 208 209 /* For the KVM GICv3, affinity routing is always enabled, and the first 2 210 * GICD_ICFGR<n> registers are always RAZ/WI. The corresponding 211 * functionality is replaced by GICR_ICFGR<n>. It doesn't need to sync 212 * them. So it should increase the offset to skip GIC_INTERNAL irqs. 213 * This matches the for_each_dist_irq_reg() macro which also skips the 214 * first GIC_INTERNAL irqs. 215 */ 216 offset += (GIC_INTERNAL * 2) / 8; 217 for_each_dist_irq_reg(irq, s->num_irq, 2) { 218 reg = *gic_bmp_ptr32(bmp, irq); 219 if (irq % 32 != 0) { 220 reg = (reg & 0xffff0000) >> 16; 221 } else { 222 reg = reg & 0xffff; 223 } 224 reg = half_shuffle32(reg) << 1; 225 kvm_gicd_access(s, offset, ®, true); 226 offset += 4; 227 } 228 } 229 230 static void kvm_gic_get_line_level_bmp(GICv3State *s, uint32_t *bmp) 231 { 232 uint32_t reg; 233 int irq; 234 235 for_each_dist_irq_reg(irq, s->num_irq, 1) { 236 kvm_gic_line_level_access(s, irq, 0, ®, false); 237 *gic_bmp_ptr32(bmp, irq) = reg; 238 } 239 } 240 241 static void kvm_gic_put_line_level_bmp(GICv3State *s, uint32_t *bmp) 242 { 243 uint32_t reg; 244 int irq; 245 246 for_each_dist_irq_reg(irq, s->num_irq, 1) { 247 reg = *gic_bmp_ptr32(bmp, irq); 248 kvm_gic_line_level_access(s, irq, 0, ®, true); 249 } 250 } 251 252 /* Read a bitmap register group from the kernel VGIC. */ 253 static void kvm_dist_getbmp(GICv3State *s, uint32_t offset, uint32_t *bmp) 254 { 255 uint32_t reg; 256 int irq; 257 258 /* For the KVM GICv3, affinity routing is always enabled, and the 259 * GICD_IGROUPR0/GICD_IGRPMODR0/GICD_ISENABLER0/GICD_ISPENDR0/ 260 * GICD_ISACTIVER0 registers are always RAZ/WI. The corresponding 261 * functionality is replaced by the GICR registers. It doesn't need to sync 262 * them. So it should increase the offset to skip GIC_INTERNAL irqs. 263 * This matches the for_each_dist_irq_reg() macro which also skips the 264 * first GIC_INTERNAL irqs. 265 */ 266 offset += (GIC_INTERNAL * 1) / 8; 267 for_each_dist_irq_reg(irq, s->num_irq, 1) { 268 kvm_gicd_access(s, offset, ®, false); 269 *gic_bmp_ptr32(bmp, irq) = reg; 270 offset += 4; 271 } 272 } 273 274 static void kvm_dist_putbmp(GICv3State *s, uint32_t offset, 275 uint32_t clroffset, uint32_t *bmp) 276 { 277 uint32_t reg; 278 int irq; 279 280 /* For the KVM GICv3, affinity routing is always enabled, and the 281 * GICD_IGROUPR0/GICD_IGRPMODR0/GICD_ISENABLER0/GICD_ISPENDR0/ 282 * GICD_ISACTIVER0 registers are always RAZ/WI. The corresponding 283 * functionality is replaced by the GICR registers. It doesn't need to sync 284 * them. So it should increase the offset and clroffset to skip GIC_INTERNAL 285 * irqs. This matches the for_each_dist_irq_reg() macro which also skips the 286 * first GIC_INTERNAL irqs. 287 */ 288 offset += (GIC_INTERNAL * 1) / 8; 289 if (clroffset != 0) { 290 clroffset += (GIC_INTERNAL * 1) / 8; 291 } 292 293 for_each_dist_irq_reg(irq, s->num_irq, 1) { 294 /* If this bitmap is a set/clear register pair, first write to the 295 * clear-reg to clear all bits before using the set-reg to write 296 * the 1 bits. 297 */ 298 if (clroffset != 0) { 299 reg = ~0; 300 kvm_gicd_access(s, clroffset, ®, true); 301 clroffset += 4; 302 } 303 reg = *gic_bmp_ptr32(bmp, irq); 304 kvm_gicd_access(s, offset, ®, true); 305 offset += 4; 306 } 307 } 308 309 static void kvm_arm_gicv3_check(GICv3State *s) 310 { 311 uint32_t reg; 312 uint32_t num_irq; 313 314 /* Sanity checking s->num_irq */ 315 kvm_gicd_access(s, GICD_TYPER, ®, false); 316 num_irq = ((reg & 0x1f) + 1) * 32; 317 318 if (num_irq < s->num_irq) { 319 error_report("Model requests %u IRQs, but kernel supports max %u", 320 s->num_irq, num_irq); 321 abort(); 322 } 323 } 324 325 static void kvm_arm_gicv3_put(GICv3State *s) 326 { 327 uint32_t regl, regh, reg; 328 uint64_t reg64, redist_typer; 329 int ncpu, i; 330 331 kvm_arm_gicv3_check(s); 332 333 kvm_gicr_access(s, GICR_TYPER, 0, ®l, false); 334 kvm_gicr_access(s, GICR_TYPER + 4, 0, ®h, false); 335 redist_typer = ((uint64_t)regh << 32) | regl; 336 337 reg = s->gicd_ctlr; 338 kvm_gicd_access(s, GICD_CTLR, ®, true); 339 340 if (redist_typer & GICR_TYPER_PLPIS) { 341 /* 342 * Restore base addresses before LPIs are potentially enabled by 343 * GICR_CTLR write 344 */ 345 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 346 GICv3CPUState *c = &s->cpu[ncpu]; 347 348 reg64 = c->gicr_propbaser; 349 regl = (uint32_t)reg64; 350 kvm_gicr_access(s, GICR_PROPBASER, ncpu, ®l, true); 351 regh = (uint32_t)(reg64 >> 32); 352 kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, ®h, true); 353 354 reg64 = c->gicr_pendbaser; 355 regl = (uint32_t)reg64; 356 kvm_gicr_access(s, GICR_PENDBASER, ncpu, ®l, true); 357 regh = (uint32_t)(reg64 >> 32); 358 kvm_gicr_access(s, GICR_PENDBASER + 4, ncpu, ®h, true); 359 } 360 } 361 362 /* Redistributor state (one per CPU) */ 363 364 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 365 GICv3CPUState *c = &s->cpu[ncpu]; 366 367 reg = c->gicr_ctlr; 368 kvm_gicr_access(s, GICR_CTLR, ncpu, ®, true); 369 370 reg = c->gicr_statusr[GICV3_NS]; 371 kvm_gicr_access(s, GICR_STATUSR, ncpu, ®, true); 372 373 reg = c->gicr_waker; 374 kvm_gicr_access(s, GICR_WAKER, ncpu, ®, true); 375 376 reg = c->gicr_igroupr0; 377 kvm_gicr_access(s, GICR_IGROUPR0, ncpu, ®, true); 378 379 reg = ~0; 380 kvm_gicr_access(s, GICR_ICENABLER0, ncpu, ®, true); 381 reg = c->gicr_ienabler0; 382 kvm_gicr_access(s, GICR_ISENABLER0, ncpu, ®, true); 383 384 /* Restore config before pending so we treat level/edge correctly */ 385 reg = half_shuffle32(c->edge_trigger >> 16) << 1; 386 kvm_gicr_access(s, GICR_ICFGR1, ncpu, ®, true); 387 388 reg = c->level; 389 kvm_gic_line_level_access(s, 0, ncpu, ®, true); 390 391 reg = c->gicr_ipendr0; 392 kvm_gicr_access(s, GICR_ISPENDR0, ncpu, ®, true); 393 394 reg = ~0; 395 kvm_gicr_access(s, GICR_ICACTIVER0, ncpu, ®, true); 396 reg = c->gicr_iactiver0; 397 kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, ®, true); 398 399 for (i = 0; i < GIC_INTERNAL; i += 4) { 400 reg = c->gicr_ipriorityr[i] | 401 (c->gicr_ipriorityr[i + 1] << 8) | 402 (c->gicr_ipriorityr[i + 2] << 16) | 403 (c->gicr_ipriorityr[i + 3] << 24); 404 kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, ®, true); 405 } 406 } 407 408 /* Distributor state (shared between all CPUs */ 409 reg = s->gicd_statusr[GICV3_NS]; 410 kvm_gicd_access(s, GICD_STATUSR, ®, true); 411 412 /* s->enable bitmap -> GICD_ISENABLERn */ 413 kvm_dist_putbmp(s, GICD_ISENABLER, GICD_ICENABLER, s->enabled); 414 415 /* s->group bitmap -> GICD_IGROUPRn */ 416 kvm_dist_putbmp(s, GICD_IGROUPR, 0, s->group); 417 418 /* Restore targets before pending to ensure the pending state is set on 419 * the appropriate CPU interfaces in the kernel 420 */ 421 422 /* s->gicd_irouter[irq] -> GICD_IROUTERn 423 * We can't use kvm_dist_put() here because the registers are 64-bit 424 */ 425 for (i = GIC_INTERNAL; i < s->num_irq; i++) { 426 uint32_t offset; 427 428 offset = GICD_IROUTER + (sizeof(uint32_t) * i); 429 reg = (uint32_t)s->gicd_irouter[i]; 430 kvm_gicd_access(s, offset, ®, true); 431 432 offset = GICD_IROUTER + (sizeof(uint32_t) * i) + 4; 433 reg = (uint32_t)(s->gicd_irouter[i] >> 32); 434 kvm_gicd_access(s, offset, ®, true); 435 } 436 437 /* s->trigger bitmap -> GICD_ICFGRn 438 * (restore configuration registers before pending IRQs so we treat 439 * level/edge correctly) 440 */ 441 kvm_dist_put_edge_trigger(s, GICD_ICFGR, s->edge_trigger); 442 443 /* s->level bitmap -> line_level */ 444 kvm_gic_put_line_level_bmp(s, s->level); 445 446 /* s->pending bitmap -> GICD_ISPENDRn */ 447 kvm_dist_putbmp(s, GICD_ISPENDR, 0, s->pending); 448 449 /* s->active bitmap -> GICD_ISACTIVERn */ 450 kvm_dist_putbmp(s, GICD_ISACTIVER, GICD_ICACTIVER, s->active); 451 452 /* s->gicd_ipriority[] -> GICD_IPRIORITYRn */ 453 kvm_dist_put_priority(s, GICD_IPRIORITYR, s->gicd_ipriority); 454 455 /* CPU Interface state (one per CPU) */ 456 457 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 458 GICv3CPUState *c = &s->cpu[ncpu]; 459 int num_pri_bits; 460 461 kvm_gicc_access(s, ICC_SRE_EL1, ncpu, &c->icc_sre_el1, true); 462 kvm_gicc_access(s, ICC_CTLR_EL1, ncpu, 463 &c->icc_ctlr_el1[GICV3_NS], true); 464 kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu, 465 &c->icc_igrpen[GICV3_G0], true); 466 kvm_gicc_access(s, ICC_IGRPEN1_EL1, ncpu, 467 &c->icc_igrpen[GICV3_G1NS], true); 468 kvm_gicc_access(s, ICC_PMR_EL1, ncpu, &c->icc_pmr_el1, true); 469 kvm_gicc_access(s, ICC_BPR0_EL1, ncpu, &c->icc_bpr[GICV3_G0], true); 470 kvm_gicc_access(s, ICC_BPR1_EL1, ncpu, &c->icc_bpr[GICV3_G1NS], true); 471 472 num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] & 473 ICC_CTLR_EL1_PRIBITS_MASK) >> 474 ICC_CTLR_EL1_PRIBITS_SHIFT) + 1; 475 476 switch (num_pri_bits) { 477 case 7: 478 reg64 = c->icc_apr[GICV3_G0][3]; 479 kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, ®64, true); 480 reg64 = c->icc_apr[GICV3_G0][2]; 481 kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, ®64, true); 482 /* fall through */ 483 case 6: 484 reg64 = c->icc_apr[GICV3_G0][1]; 485 kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, ®64, true); 486 /* fall through */ 487 default: 488 reg64 = c->icc_apr[GICV3_G0][0]; 489 kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, ®64, true); 490 } 491 492 switch (num_pri_bits) { 493 case 7: 494 reg64 = c->icc_apr[GICV3_G1NS][3]; 495 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, ®64, true); 496 reg64 = c->icc_apr[GICV3_G1NS][2]; 497 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, ®64, true); 498 /* fall through */ 499 case 6: 500 reg64 = c->icc_apr[GICV3_G1NS][1]; 501 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, ®64, true); 502 /* fall through */ 503 default: 504 reg64 = c->icc_apr[GICV3_G1NS][0]; 505 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, ®64, true); 506 } 507 } 508 } 509 510 static void kvm_arm_gicv3_get(GICv3State *s) 511 { 512 uint32_t regl, regh, reg; 513 uint64_t reg64, redist_typer; 514 int ncpu, i; 515 516 kvm_arm_gicv3_check(s); 517 518 kvm_gicr_access(s, GICR_TYPER, 0, ®l, false); 519 kvm_gicr_access(s, GICR_TYPER + 4, 0, ®h, false); 520 redist_typer = ((uint64_t)regh << 32) | regl; 521 522 kvm_gicd_access(s, GICD_CTLR, ®, false); 523 s->gicd_ctlr = reg; 524 525 /* Redistributor state (one per CPU) */ 526 527 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 528 GICv3CPUState *c = &s->cpu[ncpu]; 529 530 kvm_gicr_access(s, GICR_CTLR, ncpu, ®, false); 531 c->gicr_ctlr = reg; 532 533 kvm_gicr_access(s, GICR_STATUSR, ncpu, ®, false); 534 c->gicr_statusr[GICV3_NS] = reg; 535 536 kvm_gicr_access(s, GICR_WAKER, ncpu, ®, false); 537 c->gicr_waker = reg; 538 539 kvm_gicr_access(s, GICR_IGROUPR0, ncpu, ®, false); 540 c->gicr_igroupr0 = reg; 541 kvm_gicr_access(s, GICR_ISENABLER0, ncpu, ®, false); 542 c->gicr_ienabler0 = reg; 543 kvm_gicr_access(s, GICR_ICFGR1, ncpu, ®, false); 544 c->edge_trigger = half_unshuffle32(reg >> 1) << 16; 545 kvm_gic_line_level_access(s, 0, ncpu, ®, false); 546 c->level = reg; 547 kvm_gicr_access(s, GICR_ISPENDR0, ncpu, ®, false); 548 c->gicr_ipendr0 = reg; 549 kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, ®, false); 550 c->gicr_iactiver0 = reg; 551 552 for (i = 0; i < GIC_INTERNAL; i += 4) { 553 kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, ®, false); 554 c->gicr_ipriorityr[i] = extract32(reg, 0, 8); 555 c->gicr_ipriorityr[i + 1] = extract32(reg, 8, 8); 556 c->gicr_ipriorityr[i + 2] = extract32(reg, 16, 8); 557 c->gicr_ipriorityr[i + 3] = extract32(reg, 24, 8); 558 } 559 } 560 561 if (redist_typer & GICR_TYPER_PLPIS) { 562 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 563 GICv3CPUState *c = &s->cpu[ncpu]; 564 565 kvm_gicr_access(s, GICR_PROPBASER, ncpu, ®l, false); 566 kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, ®h, false); 567 c->gicr_propbaser = ((uint64_t)regh << 32) | regl; 568 569 kvm_gicr_access(s, GICR_PENDBASER, ncpu, ®l, false); 570 kvm_gicr_access(s, GICR_PENDBASER + 4, ncpu, ®h, false); 571 c->gicr_pendbaser = ((uint64_t)regh << 32) | regl; 572 } 573 } 574 575 /* Distributor state (shared between all CPUs */ 576 577 kvm_gicd_access(s, GICD_STATUSR, ®, false); 578 s->gicd_statusr[GICV3_NS] = reg; 579 580 /* GICD_IGROUPRn -> s->group bitmap */ 581 kvm_dist_getbmp(s, GICD_IGROUPR, s->group); 582 583 /* GICD_ISENABLERn -> s->enabled bitmap */ 584 kvm_dist_getbmp(s, GICD_ISENABLER, s->enabled); 585 586 /* Line level of irq */ 587 kvm_gic_get_line_level_bmp(s, s->level); 588 /* GICD_ISPENDRn -> s->pending bitmap */ 589 kvm_dist_getbmp(s, GICD_ISPENDR, s->pending); 590 591 /* GICD_ISACTIVERn -> s->active bitmap */ 592 kvm_dist_getbmp(s, GICD_ISACTIVER, s->active); 593 594 /* GICD_ICFGRn -> s->trigger bitmap */ 595 kvm_dist_get_edge_trigger(s, GICD_ICFGR, s->edge_trigger); 596 597 /* GICD_IPRIORITYRn -> s->gicd_ipriority[] */ 598 kvm_dist_get_priority(s, GICD_IPRIORITYR, s->gicd_ipriority); 599 600 /* GICD_IROUTERn -> s->gicd_irouter[irq] */ 601 for (i = GIC_INTERNAL; i < s->num_irq; i++) { 602 uint32_t offset; 603 604 offset = GICD_IROUTER + (sizeof(uint32_t) * i); 605 kvm_gicd_access(s, offset, ®l, false); 606 offset = GICD_IROUTER + (sizeof(uint32_t) * i) + 4; 607 kvm_gicd_access(s, offset, ®h, false); 608 s->gicd_irouter[i] = ((uint64_t)regh << 32) | regl; 609 } 610 611 /***************************************************************** 612 * CPU Interface(s) State 613 */ 614 615 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 616 GICv3CPUState *c = &s->cpu[ncpu]; 617 int num_pri_bits; 618 619 kvm_gicc_access(s, ICC_SRE_EL1, ncpu, &c->icc_sre_el1, false); 620 kvm_gicc_access(s, ICC_CTLR_EL1, ncpu, 621 &c->icc_ctlr_el1[GICV3_NS], false); 622 kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu, 623 &c->icc_igrpen[GICV3_G0], false); 624 kvm_gicc_access(s, ICC_IGRPEN1_EL1, ncpu, 625 &c->icc_igrpen[GICV3_G1NS], false); 626 kvm_gicc_access(s, ICC_PMR_EL1, ncpu, &c->icc_pmr_el1, false); 627 kvm_gicc_access(s, ICC_BPR0_EL1, ncpu, &c->icc_bpr[GICV3_G0], false); 628 kvm_gicc_access(s, ICC_BPR1_EL1, ncpu, &c->icc_bpr[GICV3_G1NS], false); 629 num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] & 630 ICC_CTLR_EL1_PRIBITS_MASK) >> 631 ICC_CTLR_EL1_PRIBITS_SHIFT) + 1; 632 633 switch (num_pri_bits) { 634 case 7: 635 kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, ®64, false); 636 c->icc_apr[GICV3_G0][3] = reg64; 637 kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, ®64, false); 638 c->icc_apr[GICV3_G0][2] = reg64; 639 /* fall through */ 640 case 6: 641 kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, ®64, false); 642 c->icc_apr[GICV3_G0][1] = reg64; 643 /* fall through */ 644 default: 645 kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, ®64, false); 646 c->icc_apr[GICV3_G0][0] = reg64; 647 } 648 649 switch (num_pri_bits) { 650 case 7: 651 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, ®64, false); 652 c->icc_apr[GICV3_G1NS][3] = reg64; 653 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, ®64, false); 654 c->icc_apr[GICV3_G1NS][2] = reg64; 655 /* fall through */ 656 case 6: 657 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, ®64, false); 658 c->icc_apr[GICV3_G1NS][1] = reg64; 659 /* fall through */ 660 default: 661 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, ®64, false); 662 c->icc_apr[GICV3_G1NS][0] = reg64; 663 } 664 } 665 } 666 667 static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) 668 { 669 GICv3State *s; 670 GICv3CPUState *c; 671 672 c = (GICv3CPUState *)env->gicv3state; 673 s = c->gic; 674 675 c->icc_pmr_el1 = 0; 676 /* 677 * Architecturally the reset value of the ICC_BPR registers 678 * is UNKNOWN. We set them all to 0 here; when the kernel 679 * uses these values to program the ICH_VMCR_EL2 fields that 680 * determine the guest-visible ICC_BPR register values, the 681 * hardware's "writing a value less than the minimum sets 682 * the field to the minimum value" behaviour will result in 683 * them effectively resetting to the correct minimum value 684 * for the host GIC. 685 */ 686 c->icc_bpr[GICV3_G0] = 0; 687 c->icc_bpr[GICV3_G1] = 0; 688 c->icc_bpr[GICV3_G1NS] = 0; 689 690 c->icc_sre_el1 = 0x7; 691 memset(c->icc_apr, 0, sizeof(c->icc_apr)); 692 memset(c->icc_igrpen, 0, sizeof(c->icc_igrpen)); 693 694 if (s->migration_blocker) { 695 return; 696 } 697 698 /* Initialize to actual HW supported configuration */ 699 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, 700 KVM_VGIC_ATTR(ICC_CTLR_EL1, c->gicr_typer), 701 &c->icc_ctlr_el1[GICV3_NS], false, &error_abort); 702 703 c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS]; 704 } 705 706 static void kvm_arm_gicv3_reset_hold(Object *obj, ResetType type) 707 { 708 GICv3State *s = ARM_GICV3_COMMON(obj); 709 KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s); 710 711 DPRINTF("Reset\n"); 712 713 if (kgc->parent_phases.hold) { 714 kgc->parent_phases.hold(obj, type); 715 } 716 717 if (s->migration_blocker) { 718 DPRINTF("Cannot put kernel gic state, no kernel interface\n"); 719 return; 720 } 721 722 kvm_arm_gicv3_put(s); 723 } 724 725 /* 726 * CPU interface registers of GIC needs to be reset on CPU reset. 727 * For the calling arm_gicv3_icc_reset() on CPU reset, we register 728 * below ARMCPRegInfo. As we reset the whole cpu interface under single 729 * register reset, we define only one register of CPU interface instead 730 * of defining all the registers. 731 */ 732 static const ARMCPRegInfo gicv3_cpuif_reginfo[] = { 733 { .name = "ICC_CTLR_EL1", .state = ARM_CP_STATE_BOTH, 734 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 4, 735 /* 736 * If ARM_CP_NOP is used, resetfn is not called, 737 * So ARM_CP_NO_RAW is appropriate type. 738 */ 739 .type = ARM_CP_NO_RAW, 740 .access = PL1_RW, 741 .readfn = arm_cp_read_zero, 742 .writefn = arm_cp_write_ignore, 743 /* 744 * We hang the whole cpu interface reset routine off here 745 * rather than parcelling it out into one little function 746 * per register 747 */ 748 .resetfn = arm_gicv3_icc_reset, 749 }, 750 }; 751 752 /** 753 * vm_change_state_handler - VM change state callback aiming at flushing 754 * RDIST pending tables into guest RAM 755 * 756 * The tables get flushed to guest RAM whenever the VM gets stopped. 757 */ 758 static void vm_change_state_handler(void *opaque, bool running, 759 RunState state) 760 { 761 GICv3State *s = (GICv3State *)opaque; 762 Error *err = NULL; 763 int ret; 764 765 if (running) { 766 return; 767 } 768 769 ret = kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, 770 KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES, 771 NULL, true, &err); 772 if (err) { 773 error_report_err(err); 774 } 775 if (ret < 0 && ret != -EFAULT) { 776 abort(); 777 } 778 } 779 780 static int kvm_arm_gicv3_notifier(NotifierWithReturn *notifier, 781 MigrationEvent *e, Error **errp) 782 { 783 if (e->type == MIG_EVENT_PRECOPY_DONE) { 784 GICv3State *s = container_of(notifier, GICv3State, cpr_notifier); 785 return kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, 786 KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES, 787 NULL, true, errp); 788 } 789 return 0; 790 } 791 792 static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) 793 { 794 GICv3State *s = KVM_ARM_GICV3(dev); 795 KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s); 796 bool multiple_redist_region_allowed; 797 Error *local_err = NULL; 798 int i; 799 800 DPRINTF("kvm_arm_gicv3_realize\n"); 801 802 kgc->parent_realize(dev, &local_err); 803 if (local_err) { 804 error_propagate(errp, local_err); 805 return; 806 } 807 808 if (s->revision != 3) { 809 error_setg(errp, "unsupported GIC revision %d for in-kernel GIC", 810 s->revision); 811 } 812 813 if (s->security_extn) { 814 error_setg(errp, "the in-kernel VGICv3 does not implement the " 815 "security extensions"); 816 return; 817 } 818 819 if (s->nmi_support) { 820 error_setg(errp, "NMI is not supported with the in-kernel GIC"); 821 return; 822 } 823 824 gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL); 825 826 for (i = 0; i < s->num_cpu; i++) { 827 ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i)); 828 829 define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); 830 } 831 832 /* Try to create the device via the device control API */ 833 s->dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V3, false); 834 if (s->dev_fd < 0) { 835 error_setg_errno(errp, -s->dev_fd, "error creating in-kernel VGIC"); 836 return; 837 } 838 839 if (s->maint_irq) { 840 Error *kvm_nv_migration_blocker = NULL; 841 int ret; 842 843 error_setg(&kvm_nv_migration_blocker, 844 "Live migration disabled because KVM nested virt is enabled"); 845 if (migrate_add_blocker(&kvm_nv_migration_blocker, errp)) { 846 error_free(kvm_nv_migration_blocker); 847 return; 848 } 849 850 ret = kvm_device_check_attr(s->dev_fd, 851 KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ, 0); 852 if (!ret) { 853 error_setg_errno(errp, errno, 854 "VGICv3 setting maintenance IRQ is not " 855 "supported by this host kernel"); 856 return; 857 } 858 859 ret = kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ, 0, 860 &s->maint_irq, true, errp); 861 if (ret) { 862 error_setg_errno(errp, errno, "Failed to set VGIC maintenance IRQ"); 863 return; 864 } 865 } 866 867 multiple_redist_region_allowed = 868 kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ADDR, 869 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION); 870 871 if (!multiple_redist_region_allowed && s->nb_redist_regions > 1) { 872 error_setg(errp, "Multiple VGICv3 redistributor regions are not " 873 "supported by this host kernel"); 874 error_append_hint(errp, "A maximum of %d VCPUs can be used", 875 s->redist_region_count[0]); 876 return; 877 } 878 879 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 880 0, &s->num_irq, true, &error_abort); 881 882 /* Tell the kernel to complete VGIC initialization now */ 883 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, 884 KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort); 885 886 kvm_arm_register_device(&s->iomem_dist, -1, KVM_DEV_ARM_VGIC_GRP_ADDR, 887 KVM_VGIC_V3_ADDR_TYPE_DIST, s->dev_fd, 0); 888 889 if (!multiple_redist_region_allowed) { 890 kvm_arm_register_device(&s->redist_regions[0].iomem, -1, 891 KVM_DEV_ARM_VGIC_GRP_ADDR, 892 KVM_VGIC_V3_ADDR_TYPE_REDIST, s->dev_fd, 0); 893 } else { 894 /* we register regions in reverse order as "devices" are inserted at 895 * the head of a QSLIST and the list is then popped from the head 896 * onwards by kvm_arm_machine_init_done() 897 */ 898 for (i = s->nb_redist_regions - 1; i >= 0; i--) { 899 /* Address mask made of the rdist region index and count */ 900 uint64_t addr_ormask = 901 i | ((uint64_t)s->redist_region_count[i] << 52); 902 903 kvm_arm_register_device(&s->redist_regions[i].iomem, -1, 904 KVM_DEV_ARM_VGIC_GRP_ADDR, 905 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION, 906 s->dev_fd, addr_ormask); 907 } 908 } 909 910 if (kvm_has_gsi_routing()) { 911 /* set up irq routing */ 912 for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) { 913 kvm_irqchip_add_irq_route(kvm_state, i, 0, i); 914 } 915 916 kvm_gsi_routing_allowed = true; 917 918 kvm_irqchip_commit_routes(kvm_state); 919 } 920 921 if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS, 922 GICD_CTLR)) { 923 error_setg(&s->migration_blocker, "This operating system kernel does " 924 "not support vGICv3 migration"); 925 if (migrate_add_blocker(&s->migration_blocker, errp) < 0) { 926 return; 927 } 928 } 929 if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, 930 KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES)) { 931 qemu_add_vm_change_state_handler(vm_change_state_handler, s); 932 migration_add_notifier_mode(&s->cpr_notifier, 933 kvm_arm_gicv3_notifier, 934 MIG_MODE_CPR_TRANSFER); 935 } 936 } 937 938 static void kvm_arm_gicv3_class_init(ObjectClass *klass, const void *data) 939 { 940 DeviceClass *dc = DEVICE_CLASS(klass); 941 ResettableClass *rc = RESETTABLE_CLASS(klass); 942 ARMGICv3CommonClass *agcc = ARM_GICV3_COMMON_CLASS(klass); 943 KVMARMGICv3Class *kgc = KVM_ARM_GICV3_CLASS(klass); 944 945 agcc->pre_save = kvm_arm_gicv3_get; 946 agcc->post_load = kvm_arm_gicv3_put; 947 device_class_set_parent_realize(dc, kvm_arm_gicv3_realize, 948 &kgc->parent_realize); 949 resettable_class_set_parent_phases(rc, NULL, kvm_arm_gicv3_reset_hold, NULL, 950 &kgc->parent_phases); 951 } 952 953 static const TypeInfo kvm_arm_gicv3_info = { 954 .name = TYPE_KVM_ARM_GICV3, 955 .parent = TYPE_ARM_GICV3_COMMON, 956 .instance_size = sizeof(GICv3State), 957 .class_init = kvm_arm_gicv3_class_init, 958 .class_size = sizeof(KVMARMGICv3Class), 959 }; 960 961 static void kvm_arm_gicv3_register_types(void) 962 { 963 type_register_static(&kvm_arm_gicv3_info); 964 } 965 966 type_init(kvm_arm_gicv3_register_types) 967