1 /* 2 * ARM Generic Interrupt Controller using KVM in-kernel support 3 * 4 * Copyright (c) 2015 Samsung Electronics Co., Ltd. 5 * Written by Pavel Fedin 6 * Based on vGICv2 code by Peter Maydell 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation, either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "hw/intc/arm_gicv3_common.h" 25 #include "hw/arm/virt.h" 26 #include "qemu/error-report.h" 27 #include "qemu/module.h" 28 #include "system/kvm.h" 29 #include "system/runstate.h" 30 #include "kvm_arm.h" 31 #include "gicv3_internal.h" 32 #include "vgic_common.h" 33 #include "migration/blocker.h" 34 #include "qom/object.h" 35 #include "target/arm/cpregs.h" 36 37 38 #ifdef DEBUG_GICV3_KVM 39 #define DPRINTF(fmt, ...) \ 40 do { fprintf(stderr, "kvm_gicv3: " fmt, ## __VA_ARGS__); } while (0) 41 #else 42 #define DPRINTF(fmt, ...) \ 43 do { } while (0) 44 #endif 45 46 #define TYPE_KVM_ARM_GICV3 "kvm-arm-gicv3" 47 typedef struct KVMARMGICv3Class KVMARMGICv3Class; 48 /* This is reusing the GICv3State typedef from ARM_GICV3_ITS_COMMON */ 49 DECLARE_OBJ_CHECKERS(GICv3State, KVMARMGICv3Class, 50 KVM_ARM_GICV3, TYPE_KVM_ARM_GICV3) 51 52 #define KVM_DEV_ARM_VGIC_SYSREG(op0, op1, crn, crm, op2) \ 53 (ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \ 54 ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \ 55 ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \ 56 ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \ 57 ARM64_SYS_REG_SHIFT_MASK(op2, OP2)) 58 59 #define ICC_PMR_EL1 \ 60 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 4, 6, 0) 61 #define ICC_BPR0_EL1 \ 62 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 8, 3) 63 #define ICC_AP0R_EL1(n) \ 64 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 8, 4 | n) 65 #define ICC_AP1R_EL1(n) \ 66 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 9, n) 67 #define ICC_BPR1_EL1 \ 68 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 3) 69 #define ICC_CTLR_EL1 \ 70 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 4) 71 #define ICC_SRE_EL1 \ 72 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 5) 73 #define ICC_IGRPEN0_EL1 \ 74 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 6) 75 #define ICC_IGRPEN1_EL1 \ 76 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 7) 77 78 struct KVMARMGICv3Class { 79 ARMGICv3CommonClass parent_class; 80 DeviceRealize parent_realize; 81 ResettablePhases parent_phases; 82 }; 83 84 static void kvm_arm_gicv3_set_irq(void *opaque, int irq, int level) 85 { 86 GICv3State *s = (GICv3State *)opaque; 87 88 kvm_arm_gic_set_irq(s->num_irq, irq, level); 89 } 90 91 #define KVM_VGIC_ATTR(reg, typer) \ 92 ((typer & KVM_DEV_ARM_VGIC_V3_MPIDR_MASK) | (reg)) 93 94 static inline void kvm_gicd_access(GICv3State *s, int offset, 95 uint32_t *val, bool write) 96 { 97 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS, 98 KVM_VGIC_ATTR(offset, 0), 99 val, write, &error_abort); 100 } 101 102 static inline void kvm_gicr_access(GICv3State *s, int offset, int cpu, 103 uint32_t *val, bool write) 104 { 105 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS, 106 KVM_VGIC_ATTR(offset, s->cpu[cpu].gicr_typer), 107 val, write, &error_abort); 108 } 109 110 static inline void kvm_gicc_access(GICv3State *s, uint64_t reg, int cpu, 111 uint64_t *val, bool write) 112 { 113 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, 114 KVM_VGIC_ATTR(reg, s->cpu[cpu].gicr_typer), 115 val, write, &error_abort); 116 } 117 118 static inline void kvm_gic_line_level_access(GICv3State *s, int irq, int cpu, 119 uint32_t *val, bool write) 120 { 121 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO, 122 KVM_VGIC_ATTR(irq, s->cpu[cpu].gicr_typer) | 123 (VGIC_LEVEL_INFO_LINE_LEVEL << 124 KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT), 125 val, write, &error_abort); 126 } 127 128 /* Loop through each distributor IRQ related register; since bits 129 * corresponding to SPIs and PPIs are RAZ/WI when affinity routing 130 * is enabled, we skip those. 131 */ 132 #define for_each_dist_irq_reg(_irq, _max, _field_width) \ 133 for (_irq = GIC_INTERNAL; _irq < _max; _irq += (32 / _field_width)) 134 135 static void kvm_dist_get_priority(GICv3State *s, uint32_t offset, uint8_t *bmp) 136 { 137 uint32_t reg, *field; 138 int irq; 139 140 /* For the KVM GICv3, affinity routing is always enabled, and the first 8 141 * GICD_IPRIORITYR<n> registers are always RAZ/WI. The corresponding 142 * functionality is replaced by GICR_IPRIORITYR<n>. It doesn't need to 143 * sync them. So it needs to skip the field of GIC_INTERNAL irqs in bmp and 144 * offset. 145 */ 146 field = (uint32_t *)(bmp + GIC_INTERNAL); 147 offset += (GIC_INTERNAL * 8) / 8; 148 for_each_dist_irq_reg(irq, s->num_irq, 8) { 149 kvm_gicd_access(s, offset, ®, false); 150 *field = reg; 151 offset += 4; 152 field++; 153 } 154 } 155 156 static void kvm_dist_put_priority(GICv3State *s, uint32_t offset, uint8_t *bmp) 157 { 158 uint32_t reg, *field; 159 int irq; 160 161 /* For the KVM GICv3, affinity routing is always enabled, and the first 8 162 * GICD_IPRIORITYR<n> registers are always RAZ/WI. The corresponding 163 * functionality is replaced by GICR_IPRIORITYR<n>. It doesn't need to 164 * sync them. So it needs to skip the field of GIC_INTERNAL irqs in bmp and 165 * offset. 166 */ 167 field = (uint32_t *)(bmp + GIC_INTERNAL); 168 offset += (GIC_INTERNAL * 8) / 8; 169 for_each_dist_irq_reg(irq, s->num_irq, 8) { 170 reg = *field; 171 kvm_gicd_access(s, offset, ®, true); 172 offset += 4; 173 field++; 174 } 175 } 176 177 static void kvm_dist_get_edge_trigger(GICv3State *s, uint32_t offset, 178 uint32_t *bmp) 179 { 180 uint32_t reg; 181 int irq; 182 183 /* For the KVM GICv3, affinity routing is always enabled, and the first 2 184 * GICD_ICFGR<n> registers are always RAZ/WI. The corresponding 185 * functionality is replaced by GICR_ICFGR<n>. It doesn't need to sync 186 * them. So it should increase the offset to skip GIC_INTERNAL irqs. 187 * This matches the for_each_dist_irq_reg() macro which also skips the 188 * first GIC_INTERNAL irqs. 189 */ 190 offset += (GIC_INTERNAL * 2) / 8; 191 for_each_dist_irq_reg(irq, s->num_irq, 2) { 192 kvm_gicd_access(s, offset, ®, false); 193 reg = half_unshuffle32(reg >> 1); 194 if (irq % 32 != 0) { 195 reg = (reg << 16); 196 } 197 *gic_bmp_ptr32(bmp, irq) |= reg; 198 offset += 4; 199 } 200 } 201 202 static void kvm_dist_put_edge_trigger(GICv3State *s, uint32_t offset, 203 uint32_t *bmp) 204 { 205 uint32_t reg; 206 int irq; 207 208 /* For the KVM GICv3, affinity routing is always enabled, and the first 2 209 * GICD_ICFGR<n> registers are always RAZ/WI. The corresponding 210 * functionality is replaced by GICR_ICFGR<n>. It doesn't need to sync 211 * them. So it should increase the offset to skip GIC_INTERNAL irqs. 212 * This matches the for_each_dist_irq_reg() macro which also skips the 213 * first GIC_INTERNAL irqs. 214 */ 215 offset += (GIC_INTERNAL * 2) / 8; 216 for_each_dist_irq_reg(irq, s->num_irq, 2) { 217 reg = *gic_bmp_ptr32(bmp, irq); 218 if (irq % 32 != 0) { 219 reg = (reg & 0xffff0000) >> 16; 220 } else { 221 reg = reg & 0xffff; 222 } 223 reg = half_shuffle32(reg) << 1; 224 kvm_gicd_access(s, offset, ®, true); 225 offset += 4; 226 } 227 } 228 229 static void kvm_gic_get_line_level_bmp(GICv3State *s, uint32_t *bmp) 230 { 231 uint32_t reg; 232 int irq; 233 234 for_each_dist_irq_reg(irq, s->num_irq, 1) { 235 kvm_gic_line_level_access(s, irq, 0, ®, false); 236 *gic_bmp_ptr32(bmp, irq) = reg; 237 } 238 } 239 240 static void kvm_gic_put_line_level_bmp(GICv3State *s, uint32_t *bmp) 241 { 242 uint32_t reg; 243 int irq; 244 245 for_each_dist_irq_reg(irq, s->num_irq, 1) { 246 reg = *gic_bmp_ptr32(bmp, irq); 247 kvm_gic_line_level_access(s, irq, 0, ®, true); 248 } 249 } 250 251 /* Read a bitmap register group from the kernel VGIC. */ 252 static void kvm_dist_getbmp(GICv3State *s, uint32_t offset, uint32_t *bmp) 253 { 254 uint32_t reg; 255 int irq; 256 257 /* For the KVM GICv3, affinity routing is always enabled, and the 258 * GICD_IGROUPR0/GICD_IGRPMODR0/GICD_ISENABLER0/GICD_ISPENDR0/ 259 * GICD_ISACTIVER0 registers are always RAZ/WI. The corresponding 260 * functionality is replaced by the GICR registers. It doesn't need to sync 261 * them. So it should increase the offset to skip GIC_INTERNAL irqs. 262 * This matches the for_each_dist_irq_reg() macro which also skips the 263 * first GIC_INTERNAL irqs. 264 */ 265 offset += (GIC_INTERNAL * 1) / 8; 266 for_each_dist_irq_reg(irq, s->num_irq, 1) { 267 kvm_gicd_access(s, offset, ®, false); 268 *gic_bmp_ptr32(bmp, irq) = reg; 269 offset += 4; 270 } 271 } 272 273 static void kvm_dist_putbmp(GICv3State *s, uint32_t offset, 274 uint32_t clroffset, uint32_t *bmp) 275 { 276 uint32_t reg; 277 int irq; 278 279 /* For the KVM GICv3, affinity routing is always enabled, and the 280 * GICD_IGROUPR0/GICD_IGRPMODR0/GICD_ISENABLER0/GICD_ISPENDR0/ 281 * GICD_ISACTIVER0 registers are always RAZ/WI. The corresponding 282 * functionality is replaced by the GICR registers. It doesn't need to sync 283 * them. So it should increase the offset and clroffset to skip GIC_INTERNAL 284 * irqs. This matches the for_each_dist_irq_reg() macro which also skips the 285 * first GIC_INTERNAL irqs. 286 */ 287 offset += (GIC_INTERNAL * 1) / 8; 288 if (clroffset != 0) { 289 clroffset += (GIC_INTERNAL * 1) / 8; 290 } 291 292 for_each_dist_irq_reg(irq, s->num_irq, 1) { 293 /* If this bitmap is a set/clear register pair, first write to the 294 * clear-reg to clear all bits before using the set-reg to write 295 * the 1 bits. 296 */ 297 if (clroffset != 0) { 298 reg = ~0; 299 kvm_gicd_access(s, clroffset, ®, true); 300 clroffset += 4; 301 } 302 reg = *gic_bmp_ptr32(bmp, irq); 303 kvm_gicd_access(s, offset, ®, true); 304 offset += 4; 305 } 306 } 307 308 static void kvm_arm_gicv3_check(GICv3State *s) 309 { 310 uint32_t reg; 311 uint32_t num_irq; 312 313 /* Sanity checking s->num_irq */ 314 kvm_gicd_access(s, GICD_TYPER, ®, false); 315 num_irq = ((reg & 0x1f) + 1) * 32; 316 317 if (num_irq < s->num_irq) { 318 error_report("Model requests %u IRQs, but kernel supports max %u", 319 s->num_irq, num_irq); 320 abort(); 321 } 322 } 323 324 static void kvm_arm_gicv3_put(GICv3State *s) 325 { 326 uint32_t regl, regh, reg; 327 uint64_t reg64, redist_typer; 328 int ncpu, i; 329 330 kvm_arm_gicv3_check(s); 331 332 kvm_gicr_access(s, GICR_TYPER, 0, ®l, false); 333 kvm_gicr_access(s, GICR_TYPER + 4, 0, ®h, false); 334 redist_typer = ((uint64_t)regh << 32) | regl; 335 336 reg = s->gicd_ctlr; 337 kvm_gicd_access(s, GICD_CTLR, ®, true); 338 339 if (redist_typer & GICR_TYPER_PLPIS) { 340 /* 341 * Restore base addresses before LPIs are potentially enabled by 342 * GICR_CTLR write 343 */ 344 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 345 GICv3CPUState *c = &s->cpu[ncpu]; 346 347 reg64 = c->gicr_propbaser; 348 regl = (uint32_t)reg64; 349 kvm_gicr_access(s, GICR_PROPBASER, ncpu, ®l, true); 350 regh = (uint32_t)(reg64 >> 32); 351 kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, ®h, true); 352 353 reg64 = c->gicr_pendbaser; 354 regl = (uint32_t)reg64; 355 kvm_gicr_access(s, GICR_PENDBASER, ncpu, ®l, true); 356 regh = (uint32_t)(reg64 >> 32); 357 kvm_gicr_access(s, GICR_PENDBASER + 4, ncpu, ®h, true); 358 } 359 } 360 361 /* Redistributor state (one per CPU) */ 362 363 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 364 GICv3CPUState *c = &s->cpu[ncpu]; 365 366 reg = c->gicr_ctlr; 367 kvm_gicr_access(s, GICR_CTLR, ncpu, ®, true); 368 369 reg = c->gicr_statusr[GICV3_NS]; 370 kvm_gicr_access(s, GICR_STATUSR, ncpu, ®, true); 371 372 reg = c->gicr_waker; 373 kvm_gicr_access(s, GICR_WAKER, ncpu, ®, true); 374 375 reg = c->gicr_igroupr0; 376 kvm_gicr_access(s, GICR_IGROUPR0, ncpu, ®, true); 377 378 reg = ~0; 379 kvm_gicr_access(s, GICR_ICENABLER0, ncpu, ®, true); 380 reg = c->gicr_ienabler0; 381 kvm_gicr_access(s, GICR_ISENABLER0, ncpu, ®, true); 382 383 /* Restore config before pending so we treat level/edge correctly */ 384 reg = half_shuffle32(c->edge_trigger >> 16) << 1; 385 kvm_gicr_access(s, GICR_ICFGR1, ncpu, ®, true); 386 387 reg = c->level; 388 kvm_gic_line_level_access(s, 0, ncpu, ®, true); 389 390 reg = c->gicr_ipendr0; 391 kvm_gicr_access(s, GICR_ISPENDR0, ncpu, ®, true); 392 393 reg = ~0; 394 kvm_gicr_access(s, GICR_ICACTIVER0, ncpu, ®, true); 395 reg = c->gicr_iactiver0; 396 kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, ®, true); 397 398 for (i = 0; i < GIC_INTERNAL; i += 4) { 399 reg = c->gicr_ipriorityr[i] | 400 (c->gicr_ipriorityr[i + 1] << 8) | 401 (c->gicr_ipriorityr[i + 2] << 16) | 402 (c->gicr_ipriorityr[i + 3] << 24); 403 kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, ®, true); 404 } 405 } 406 407 /* Distributor state (shared between all CPUs */ 408 reg = s->gicd_statusr[GICV3_NS]; 409 kvm_gicd_access(s, GICD_STATUSR, ®, true); 410 411 /* s->enable bitmap -> GICD_ISENABLERn */ 412 kvm_dist_putbmp(s, GICD_ISENABLER, GICD_ICENABLER, s->enabled); 413 414 /* s->group bitmap -> GICD_IGROUPRn */ 415 kvm_dist_putbmp(s, GICD_IGROUPR, 0, s->group); 416 417 /* Restore targets before pending to ensure the pending state is set on 418 * the appropriate CPU interfaces in the kernel 419 */ 420 421 /* s->gicd_irouter[irq] -> GICD_IROUTERn 422 * We can't use kvm_dist_put() here because the registers are 64-bit 423 */ 424 for (i = GIC_INTERNAL; i < s->num_irq; i++) { 425 uint32_t offset; 426 427 offset = GICD_IROUTER + (sizeof(uint32_t) * i); 428 reg = (uint32_t)s->gicd_irouter[i]; 429 kvm_gicd_access(s, offset, ®, true); 430 431 offset = GICD_IROUTER + (sizeof(uint32_t) * i) + 4; 432 reg = (uint32_t)(s->gicd_irouter[i] >> 32); 433 kvm_gicd_access(s, offset, ®, true); 434 } 435 436 /* s->trigger bitmap -> GICD_ICFGRn 437 * (restore configuration registers before pending IRQs so we treat 438 * level/edge correctly) 439 */ 440 kvm_dist_put_edge_trigger(s, GICD_ICFGR, s->edge_trigger); 441 442 /* s->level bitmap -> line_level */ 443 kvm_gic_put_line_level_bmp(s, s->level); 444 445 /* s->pending bitmap -> GICD_ISPENDRn */ 446 kvm_dist_putbmp(s, GICD_ISPENDR, 0, s->pending); 447 448 /* s->active bitmap -> GICD_ISACTIVERn */ 449 kvm_dist_putbmp(s, GICD_ISACTIVER, GICD_ICACTIVER, s->active); 450 451 /* s->gicd_ipriority[] -> GICD_IPRIORITYRn */ 452 kvm_dist_put_priority(s, GICD_IPRIORITYR, s->gicd_ipriority); 453 454 /* CPU Interface state (one per CPU) */ 455 456 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 457 GICv3CPUState *c = &s->cpu[ncpu]; 458 int num_pri_bits; 459 460 kvm_gicc_access(s, ICC_SRE_EL1, ncpu, &c->icc_sre_el1, true); 461 kvm_gicc_access(s, ICC_CTLR_EL1, ncpu, 462 &c->icc_ctlr_el1[GICV3_NS], true); 463 kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu, 464 &c->icc_igrpen[GICV3_G0], true); 465 kvm_gicc_access(s, ICC_IGRPEN1_EL1, ncpu, 466 &c->icc_igrpen[GICV3_G1NS], true); 467 kvm_gicc_access(s, ICC_PMR_EL1, ncpu, &c->icc_pmr_el1, true); 468 kvm_gicc_access(s, ICC_BPR0_EL1, ncpu, &c->icc_bpr[GICV3_G0], true); 469 kvm_gicc_access(s, ICC_BPR1_EL1, ncpu, &c->icc_bpr[GICV3_G1NS], true); 470 471 num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] & 472 ICC_CTLR_EL1_PRIBITS_MASK) >> 473 ICC_CTLR_EL1_PRIBITS_SHIFT) + 1; 474 475 switch (num_pri_bits) { 476 case 7: 477 reg64 = c->icc_apr[GICV3_G0][3]; 478 kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, ®64, true); 479 reg64 = c->icc_apr[GICV3_G0][2]; 480 kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, ®64, true); 481 /* fall through */ 482 case 6: 483 reg64 = c->icc_apr[GICV3_G0][1]; 484 kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, ®64, true); 485 /* fall through */ 486 default: 487 reg64 = c->icc_apr[GICV3_G0][0]; 488 kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, ®64, true); 489 } 490 491 switch (num_pri_bits) { 492 case 7: 493 reg64 = c->icc_apr[GICV3_G1NS][3]; 494 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, ®64, true); 495 reg64 = c->icc_apr[GICV3_G1NS][2]; 496 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, ®64, true); 497 /* fall through */ 498 case 6: 499 reg64 = c->icc_apr[GICV3_G1NS][1]; 500 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, ®64, true); 501 /* fall through */ 502 default: 503 reg64 = c->icc_apr[GICV3_G1NS][0]; 504 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, ®64, true); 505 } 506 } 507 } 508 509 static void kvm_arm_gicv3_get(GICv3State *s) 510 { 511 uint32_t regl, regh, reg; 512 uint64_t reg64, redist_typer; 513 int ncpu, i; 514 515 kvm_arm_gicv3_check(s); 516 517 kvm_gicr_access(s, GICR_TYPER, 0, ®l, false); 518 kvm_gicr_access(s, GICR_TYPER + 4, 0, ®h, false); 519 redist_typer = ((uint64_t)regh << 32) | regl; 520 521 kvm_gicd_access(s, GICD_CTLR, ®, false); 522 s->gicd_ctlr = reg; 523 524 /* Redistributor state (one per CPU) */ 525 526 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 527 GICv3CPUState *c = &s->cpu[ncpu]; 528 529 kvm_gicr_access(s, GICR_CTLR, ncpu, ®, false); 530 c->gicr_ctlr = reg; 531 532 kvm_gicr_access(s, GICR_STATUSR, ncpu, ®, false); 533 c->gicr_statusr[GICV3_NS] = reg; 534 535 kvm_gicr_access(s, GICR_WAKER, ncpu, ®, false); 536 c->gicr_waker = reg; 537 538 kvm_gicr_access(s, GICR_IGROUPR0, ncpu, ®, false); 539 c->gicr_igroupr0 = reg; 540 kvm_gicr_access(s, GICR_ISENABLER0, ncpu, ®, false); 541 c->gicr_ienabler0 = reg; 542 kvm_gicr_access(s, GICR_ICFGR1, ncpu, ®, false); 543 c->edge_trigger = half_unshuffle32(reg >> 1) << 16; 544 kvm_gic_line_level_access(s, 0, ncpu, ®, false); 545 c->level = reg; 546 kvm_gicr_access(s, GICR_ISPENDR0, ncpu, ®, false); 547 c->gicr_ipendr0 = reg; 548 kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, ®, false); 549 c->gicr_iactiver0 = reg; 550 551 for (i = 0; i < GIC_INTERNAL; i += 4) { 552 kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, ®, false); 553 c->gicr_ipriorityr[i] = extract32(reg, 0, 8); 554 c->gicr_ipriorityr[i + 1] = extract32(reg, 8, 8); 555 c->gicr_ipriorityr[i + 2] = extract32(reg, 16, 8); 556 c->gicr_ipriorityr[i + 3] = extract32(reg, 24, 8); 557 } 558 } 559 560 if (redist_typer & GICR_TYPER_PLPIS) { 561 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 562 GICv3CPUState *c = &s->cpu[ncpu]; 563 564 kvm_gicr_access(s, GICR_PROPBASER, ncpu, ®l, false); 565 kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, ®h, false); 566 c->gicr_propbaser = ((uint64_t)regh << 32) | regl; 567 568 kvm_gicr_access(s, GICR_PENDBASER, ncpu, ®l, false); 569 kvm_gicr_access(s, GICR_PENDBASER + 4, ncpu, ®h, false); 570 c->gicr_pendbaser = ((uint64_t)regh << 32) | regl; 571 } 572 } 573 574 /* Distributor state (shared between all CPUs */ 575 576 kvm_gicd_access(s, GICD_STATUSR, ®, false); 577 s->gicd_statusr[GICV3_NS] = reg; 578 579 /* GICD_IGROUPRn -> s->group bitmap */ 580 kvm_dist_getbmp(s, GICD_IGROUPR, s->group); 581 582 /* GICD_ISENABLERn -> s->enabled bitmap */ 583 kvm_dist_getbmp(s, GICD_ISENABLER, s->enabled); 584 585 /* Line level of irq */ 586 kvm_gic_get_line_level_bmp(s, s->level); 587 /* GICD_ISPENDRn -> s->pending bitmap */ 588 kvm_dist_getbmp(s, GICD_ISPENDR, s->pending); 589 590 /* GICD_ISACTIVERn -> s->active bitmap */ 591 kvm_dist_getbmp(s, GICD_ISACTIVER, s->active); 592 593 /* GICD_ICFGRn -> s->trigger bitmap */ 594 kvm_dist_get_edge_trigger(s, GICD_ICFGR, s->edge_trigger); 595 596 /* GICD_IPRIORITYRn -> s->gicd_ipriority[] */ 597 kvm_dist_get_priority(s, GICD_IPRIORITYR, s->gicd_ipriority); 598 599 /* GICD_IROUTERn -> s->gicd_irouter[irq] */ 600 for (i = GIC_INTERNAL; i < s->num_irq; i++) { 601 uint32_t offset; 602 603 offset = GICD_IROUTER + (sizeof(uint32_t) * i); 604 kvm_gicd_access(s, offset, ®l, false); 605 offset = GICD_IROUTER + (sizeof(uint32_t) * i) + 4; 606 kvm_gicd_access(s, offset, ®h, false); 607 s->gicd_irouter[i] = ((uint64_t)regh << 32) | regl; 608 } 609 610 /***************************************************************** 611 * CPU Interface(s) State 612 */ 613 614 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 615 GICv3CPUState *c = &s->cpu[ncpu]; 616 int num_pri_bits; 617 618 kvm_gicc_access(s, ICC_SRE_EL1, ncpu, &c->icc_sre_el1, false); 619 kvm_gicc_access(s, ICC_CTLR_EL1, ncpu, 620 &c->icc_ctlr_el1[GICV3_NS], false); 621 kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu, 622 &c->icc_igrpen[GICV3_G0], false); 623 kvm_gicc_access(s, ICC_IGRPEN1_EL1, ncpu, 624 &c->icc_igrpen[GICV3_G1NS], false); 625 kvm_gicc_access(s, ICC_PMR_EL1, ncpu, &c->icc_pmr_el1, false); 626 kvm_gicc_access(s, ICC_BPR0_EL1, ncpu, &c->icc_bpr[GICV3_G0], false); 627 kvm_gicc_access(s, ICC_BPR1_EL1, ncpu, &c->icc_bpr[GICV3_G1NS], false); 628 num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] & 629 ICC_CTLR_EL1_PRIBITS_MASK) >> 630 ICC_CTLR_EL1_PRIBITS_SHIFT) + 1; 631 632 switch (num_pri_bits) { 633 case 7: 634 kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, ®64, false); 635 c->icc_apr[GICV3_G0][3] = reg64; 636 kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, ®64, false); 637 c->icc_apr[GICV3_G0][2] = reg64; 638 /* fall through */ 639 case 6: 640 kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, ®64, false); 641 c->icc_apr[GICV3_G0][1] = reg64; 642 /* fall through */ 643 default: 644 kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, ®64, false); 645 c->icc_apr[GICV3_G0][0] = reg64; 646 } 647 648 switch (num_pri_bits) { 649 case 7: 650 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, ®64, false); 651 c->icc_apr[GICV3_G1NS][3] = reg64; 652 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, ®64, false); 653 c->icc_apr[GICV3_G1NS][2] = reg64; 654 /* fall through */ 655 case 6: 656 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, ®64, false); 657 c->icc_apr[GICV3_G1NS][1] = reg64; 658 /* fall through */ 659 default: 660 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, ®64, false); 661 c->icc_apr[GICV3_G1NS][0] = reg64; 662 } 663 } 664 } 665 666 static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) 667 { 668 GICv3State *s; 669 GICv3CPUState *c; 670 671 c = (GICv3CPUState *)env->gicv3state; 672 s = c->gic; 673 674 c->icc_pmr_el1 = 0; 675 /* 676 * Architecturally the reset value of the ICC_BPR registers 677 * is UNKNOWN. We set them all to 0 here; when the kernel 678 * uses these values to program the ICH_VMCR_EL2 fields that 679 * determine the guest-visible ICC_BPR register values, the 680 * hardware's "writing a value less than the minimum sets 681 * the field to the minimum value" behaviour will result in 682 * them effectively resetting to the correct minimum value 683 * for the host GIC. 684 */ 685 c->icc_bpr[GICV3_G0] = 0; 686 c->icc_bpr[GICV3_G1] = 0; 687 c->icc_bpr[GICV3_G1NS] = 0; 688 689 c->icc_sre_el1 = 0x7; 690 memset(c->icc_apr, 0, sizeof(c->icc_apr)); 691 memset(c->icc_igrpen, 0, sizeof(c->icc_igrpen)); 692 693 if (s->migration_blocker) { 694 return; 695 } 696 697 /* Initialize to actual HW supported configuration */ 698 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, 699 KVM_VGIC_ATTR(ICC_CTLR_EL1, c->gicr_typer), 700 &c->icc_ctlr_el1[GICV3_NS], false, &error_abort); 701 702 c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS]; 703 } 704 705 static void kvm_arm_gicv3_reset_hold(Object *obj, ResetType type) 706 { 707 GICv3State *s = ARM_GICV3_COMMON(obj); 708 KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s); 709 710 DPRINTF("Reset\n"); 711 712 if (kgc->parent_phases.hold) { 713 kgc->parent_phases.hold(obj, type); 714 } 715 716 if (s->migration_blocker) { 717 DPRINTF("Cannot put kernel gic state, no kernel interface\n"); 718 return; 719 } 720 721 kvm_arm_gicv3_put(s); 722 } 723 724 /* 725 * CPU interface registers of GIC needs to be reset on CPU reset. 726 * For the calling arm_gicv3_icc_reset() on CPU reset, we register 727 * below ARMCPRegInfo. As we reset the whole cpu interface under single 728 * register reset, we define only one register of CPU interface instead 729 * of defining all the registers. 730 */ 731 static const ARMCPRegInfo gicv3_cpuif_reginfo[] = { 732 { .name = "ICC_CTLR_EL1", .state = ARM_CP_STATE_BOTH, 733 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 4, 734 /* 735 * If ARM_CP_NOP is used, resetfn is not called, 736 * So ARM_CP_NO_RAW is appropriate type. 737 */ 738 .type = ARM_CP_NO_RAW, 739 .access = PL1_RW, 740 .readfn = arm_cp_read_zero, 741 .writefn = arm_cp_write_ignore, 742 /* 743 * We hang the whole cpu interface reset routine off here 744 * rather than parcelling it out into one little function 745 * per register 746 */ 747 .resetfn = arm_gicv3_icc_reset, 748 }, 749 }; 750 751 /** 752 * vm_change_state_handler - VM change state callback aiming at flushing 753 * RDIST pending tables into guest RAM 754 * 755 * The tables get flushed to guest RAM whenever the VM gets stopped. 756 */ 757 static void vm_change_state_handler(void *opaque, bool running, 758 RunState state) 759 { 760 GICv3State *s = (GICv3State *)opaque; 761 Error *err = NULL; 762 int ret; 763 764 if (running) { 765 return; 766 } 767 768 ret = kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, 769 KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES, 770 NULL, true, &err); 771 if (err) { 772 error_report_err(err); 773 } 774 if (ret < 0 && ret != -EFAULT) { 775 abort(); 776 } 777 } 778 779 780 static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) 781 { 782 GICv3State *s = KVM_ARM_GICV3(dev); 783 KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s); 784 bool multiple_redist_region_allowed; 785 Error *local_err = NULL; 786 int i; 787 788 DPRINTF("kvm_arm_gicv3_realize\n"); 789 790 kgc->parent_realize(dev, &local_err); 791 if (local_err) { 792 error_propagate(errp, local_err); 793 return; 794 } 795 796 if (s->revision != 3) { 797 error_setg(errp, "unsupported GIC revision %d for in-kernel GIC", 798 s->revision); 799 } 800 801 if (s->security_extn) { 802 error_setg(errp, "the in-kernel VGICv3 does not implement the " 803 "security extensions"); 804 return; 805 } 806 807 if (s->nmi_support) { 808 error_setg(errp, "NMI is not supported with the in-kernel GIC"); 809 return; 810 } 811 812 gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL); 813 814 for (i = 0; i < s->num_cpu; i++) { 815 ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i)); 816 817 define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); 818 } 819 820 /* Try to create the device via the device control API */ 821 s->dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V3, false); 822 if (s->dev_fd < 0) { 823 error_setg_errno(errp, -s->dev_fd, "error creating in-kernel VGIC"); 824 return; 825 } 826 827 if (s->maint_irq) { 828 Error *kvm_nv_migration_blocker = NULL; 829 int ret; 830 831 error_setg(&kvm_nv_migration_blocker, 832 "Live migration disabled because KVM nested virt is enabled"); 833 if (migrate_add_blocker(&kvm_nv_migration_blocker, errp)) { 834 error_free(kvm_nv_migration_blocker); 835 return; 836 } 837 838 ret = kvm_device_check_attr(s->dev_fd, 839 KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ, 0); 840 if (!ret) { 841 error_setg_errno(errp, errno, 842 "VGICv3 setting maintenance IRQ is not " 843 "supported by this host kernel"); 844 return; 845 } 846 847 ret = kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ, 0, 848 &s->maint_irq, true, errp); 849 if (ret) { 850 error_setg_errno(errp, errno, "Failed to set VGIC maintenance IRQ"); 851 return; 852 } 853 } 854 855 multiple_redist_region_allowed = 856 kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ADDR, 857 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION); 858 859 if (!multiple_redist_region_allowed && s->nb_redist_regions > 1) { 860 error_setg(errp, "Multiple VGICv3 redistributor regions are not " 861 "supported by this host kernel"); 862 error_append_hint(errp, "A maximum of %d VCPUs can be used", 863 s->redist_region_count[0]); 864 return; 865 } 866 867 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 868 0, &s->num_irq, true, &error_abort); 869 870 /* Tell the kernel to complete VGIC initialization now */ 871 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, 872 KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort); 873 874 kvm_arm_register_device(&s->iomem_dist, -1, KVM_DEV_ARM_VGIC_GRP_ADDR, 875 KVM_VGIC_V3_ADDR_TYPE_DIST, s->dev_fd, 0); 876 877 if (!multiple_redist_region_allowed) { 878 kvm_arm_register_device(&s->redist_regions[0].iomem, -1, 879 KVM_DEV_ARM_VGIC_GRP_ADDR, 880 KVM_VGIC_V3_ADDR_TYPE_REDIST, s->dev_fd, 0); 881 } else { 882 /* we register regions in reverse order as "devices" are inserted at 883 * the head of a QSLIST and the list is then popped from the head 884 * onwards by kvm_arm_machine_init_done() 885 */ 886 for (i = s->nb_redist_regions - 1; i >= 0; i--) { 887 /* Address mask made of the rdist region index and count */ 888 uint64_t addr_ormask = 889 i | ((uint64_t)s->redist_region_count[i] << 52); 890 891 kvm_arm_register_device(&s->redist_regions[i].iomem, -1, 892 KVM_DEV_ARM_VGIC_GRP_ADDR, 893 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION, 894 s->dev_fd, addr_ormask); 895 } 896 } 897 898 if (kvm_has_gsi_routing()) { 899 /* set up irq routing */ 900 for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) { 901 kvm_irqchip_add_irq_route(kvm_state, i, 0, i); 902 } 903 904 kvm_gsi_routing_allowed = true; 905 906 kvm_irqchip_commit_routes(kvm_state); 907 } 908 909 if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS, 910 GICD_CTLR)) { 911 error_setg(&s->migration_blocker, "This operating system kernel does " 912 "not support vGICv3 migration"); 913 if (migrate_add_blocker(&s->migration_blocker, errp) < 0) { 914 return; 915 } 916 } 917 if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, 918 KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES)) { 919 qemu_add_vm_change_state_handler(vm_change_state_handler, s); 920 } 921 } 922 923 static void kvm_arm_gicv3_class_init(ObjectClass *klass, const void *data) 924 { 925 DeviceClass *dc = DEVICE_CLASS(klass); 926 ResettableClass *rc = RESETTABLE_CLASS(klass); 927 ARMGICv3CommonClass *agcc = ARM_GICV3_COMMON_CLASS(klass); 928 KVMARMGICv3Class *kgc = KVM_ARM_GICV3_CLASS(klass); 929 930 agcc->pre_save = kvm_arm_gicv3_get; 931 agcc->post_load = kvm_arm_gicv3_put; 932 device_class_set_parent_realize(dc, kvm_arm_gicv3_realize, 933 &kgc->parent_realize); 934 resettable_class_set_parent_phases(rc, NULL, kvm_arm_gicv3_reset_hold, NULL, 935 &kgc->parent_phases); 936 } 937 938 static const TypeInfo kvm_arm_gicv3_info = { 939 .name = TYPE_KVM_ARM_GICV3, 940 .parent = TYPE_ARM_GICV3_COMMON, 941 .instance_size = sizeof(GICv3State), 942 .class_init = kvm_arm_gicv3_class_init, 943 .class_size = sizeof(KVMARMGICv3Class), 944 }; 945 946 static void kvm_arm_gicv3_register_types(void) 947 { 948 type_register_static(&kvm_arm_gicv3_info); 949 } 950 951 type_init(kvm_arm_gicv3_register_types) 952