1 /* 2 * ARM Generic Interrupt Controller using KVM in-kernel support 3 * 4 * Copyright (c) 2015 Samsung Electronics Co., Ltd. 5 * Written by Pavel Fedin 6 * Based on vGICv2 code by Peter Maydell 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation, either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "hw/intc/arm_gicv3_common.h" 25 #include "qemu/error-report.h" 26 #include "qemu/module.h" 27 #include "sysemu/kvm.h" 28 #include "sysemu/runstate.h" 29 #include "kvm_arm.h" 30 #include "gicv3_internal.h" 31 #include "vgic_common.h" 32 #include "migration/blocker.h" 33 #include "qom/object.h" 34 35 #ifdef DEBUG_GICV3_KVM 36 #define DPRINTF(fmt, ...) \ 37 do { fprintf(stderr, "kvm_gicv3: " fmt, ## __VA_ARGS__); } while (0) 38 #else 39 #define DPRINTF(fmt, ...) \ 40 do { } while (0) 41 #endif 42 43 #define TYPE_KVM_ARM_GICV3 "kvm-arm-gicv3" 44 typedef struct KVMARMGICv3Class KVMARMGICv3Class; 45 /* This is reusing the GICv3State typedef from ARM_GICV3_ITS_COMMON */ 46 DECLARE_OBJ_CHECKERS(GICv3State, KVMARMGICv3Class, 47 KVM_ARM_GICV3, TYPE_KVM_ARM_GICV3) 48 49 #define KVM_DEV_ARM_VGIC_SYSREG(op0, op1, crn, crm, op2) \ 50 (ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \ 51 ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \ 52 ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \ 53 ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \ 54 ARM64_SYS_REG_SHIFT_MASK(op2, OP2)) 55 56 #define ICC_PMR_EL1 \ 57 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 4, 6, 0) 58 #define ICC_BPR0_EL1 \ 59 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 8, 3) 60 #define ICC_AP0R_EL1(n) \ 61 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 8, 4 | n) 62 #define ICC_AP1R_EL1(n) \ 63 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 9, n) 64 #define ICC_BPR1_EL1 \ 65 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 3) 66 #define ICC_CTLR_EL1 \ 67 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 4) 68 #define ICC_SRE_EL1 \ 69 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 5) 70 #define ICC_IGRPEN0_EL1 \ 71 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 6) 72 #define ICC_IGRPEN1_EL1 \ 73 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 7) 74 75 struct KVMARMGICv3Class { 76 ARMGICv3CommonClass parent_class; 77 DeviceRealize parent_realize; 78 void (*parent_reset)(DeviceState *dev); 79 }; 80 81 static void kvm_arm_gicv3_set_irq(void *opaque, int irq, int level) 82 { 83 GICv3State *s = (GICv3State *)opaque; 84 85 kvm_arm_gic_set_irq(s->num_irq, irq, level); 86 } 87 88 #define KVM_VGIC_ATTR(reg, typer) \ 89 ((typer & KVM_DEV_ARM_VGIC_V3_MPIDR_MASK) | (reg)) 90 91 static inline void kvm_gicd_access(GICv3State *s, int offset, 92 uint32_t *val, bool write) 93 { 94 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS, 95 KVM_VGIC_ATTR(offset, 0), 96 val, write, &error_abort); 97 } 98 99 static inline void kvm_gicr_access(GICv3State *s, int offset, int cpu, 100 uint32_t *val, bool write) 101 { 102 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS, 103 KVM_VGIC_ATTR(offset, s->cpu[cpu].gicr_typer), 104 val, write, &error_abort); 105 } 106 107 static inline void kvm_gicc_access(GICv3State *s, uint64_t reg, int cpu, 108 uint64_t *val, bool write) 109 { 110 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, 111 KVM_VGIC_ATTR(reg, s->cpu[cpu].gicr_typer), 112 val, write, &error_abort); 113 } 114 115 static inline void kvm_gic_line_level_access(GICv3State *s, int irq, int cpu, 116 uint32_t *val, bool write) 117 { 118 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO, 119 KVM_VGIC_ATTR(irq, s->cpu[cpu].gicr_typer) | 120 (VGIC_LEVEL_INFO_LINE_LEVEL << 121 KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT), 122 val, write, &error_abort); 123 } 124 125 /* Loop through each distributor IRQ related register; since bits 126 * corresponding to SPIs and PPIs are RAZ/WI when affinity routing 127 * is enabled, we skip those. 128 */ 129 #define for_each_dist_irq_reg(_irq, _max, _field_width) \ 130 for (_irq = GIC_INTERNAL; _irq < _max; _irq += (32 / _field_width)) 131 132 static void kvm_dist_get_priority(GICv3State *s, uint32_t offset, uint8_t *bmp) 133 { 134 uint32_t reg, *field; 135 int irq; 136 137 /* For the KVM GICv3, affinity routing is always enabled, and the first 8 138 * GICD_IPRIORITYR<n> registers are always RAZ/WI. The corresponding 139 * functionality is replaced by GICR_IPRIORITYR<n>. It doesn't need to 140 * sync them. So it needs to skip the field of GIC_INTERNAL irqs in bmp and 141 * offset. 142 */ 143 field = (uint32_t *)(bmp + GIC_INTERNAL); 144 offset += (GIC_INTERNAL * 8) / 8; 145 for_each_dist_irq_reg(irq, s->num_irq, 8) { 146 kvm_gicd_access(s, offset, ®, false); 147 *field = reg; 148 offset += 4; 149 field++; 150 } 151 } 152 153 static void kvm_dist_put_priority(GICv3State *s, uint32_t offset, uint8_t *bmp) 154 { 155 uint32_t reg, *field; 156 int irq; 157 158 /* For the KVM GICv3, affinity routing is always enabled, and the first 8 159 * GICD_IPRIORITYR<n> registers are always RAZ/WI. The corresponding 160 * functionality is replaced by GICR_IPRIORITYR<n>. It doesn't need to 161 * sync them. So it needs to skip the field of GIC_INTERNAL irqs in bmp and 162 * offset. 163 */ 164 field = (uint32_t *)(bmp + GIC_INTERNAL); 165 offset += (GIC_INTERNAL * 8) / 8; 166 for_each_dist_irq_reg(irq, s->num_irq, 8) { 167 reg = *field; 168 kvm_gicd_access(s, offset, ®, true); 169 offset += 4; 170 field++; 171 } 172 } 173 174 static void kvm_dist_get_edge_trigger(GICv3State *s, uint32_t offset, 175 uint32_t *bmp) 176 { 177 uint32_t reg; 178 int irq; 179 180 /* For the KVM GICv3, affinity routing is always enabled, and the first 2 181 * GICD_ICFGR<n> registers are always RAZ/WI. The corresponding 182 * functionality is replaced by GICR_ICFGR<n>. It doesn't need to sync 183 * them. So it should increase the offset to skip GIC_INTERNAL irqs. 184 * This matches the for_each_dist_irq_reg() macro which also skips the 185 * first GIC_INTERNAL irqs. 186 */ 187 offset += (GIC_INTERNAL * 2) / 8; 188 for_each_dist_irq_reg(irq, s->num_irq, 2) { 189 kvm_gicd_access(s, offset, ®, false); 190 reg = half_unshuffle32(reg >> 1); 191 if (irq % 32 != 0) { 192 reg = (reg << 16); 193 } 194 *gic_bmp_ptr32(bmp, irq) |= reg; 195 offset += 4; 196 } 197 } 198 199 static void kvm_dist_put_edge_trigger(GICv3State *s, uint32_t offset, 200 uint32_t *bmp) 201 { 202 uint32_t reg; 203 int irq; 204 205 /* For the KVM GICv3, affinity routing is always enabled, and the first 2 206 * GICD_ICFGR<n> registers are always RAZ/WI. The corresponding 207 * functionality is replaced by GICR_ICFGR<n>. It doesn't need to sync 208 * them. So it should increase the offset to skip GIC_INTERNAL irqs. 209 * This matches the for_each_dist_irq_reg() macro which also skips the 210 * first GIC_INTERNAL irqs. 211 */ 212 offset += (GIC_INTERNAL * 2) / 8; 213 for_each_dist_irq_reg(irq, s->num_irq, 2) { 214 reg = *gic_bmp_ptr32(bmp, irq); 215 if (irq % 32 != 0) { 216 reg = (reg & 0xffff0000) >> 16; 217 } else { 218 reg = reg & 0xffff; 219 } 220 reg = half_shuffle32(reg) << 1; 221 kvm_gicd_access(s, offset, ®, true); 222 offset += 4; 223 } 224 } 225 226 static void kvm_gic_get_line_level_bmp(GICv3State *s, uint32_t *bmp) 227 { 228 uint32_t reg; 229 int irq; 230 231 for_each_dist_irq_reg(irq, s->num_irq, 1) { 232 kvm_gic_line_level_access(s, irq, 0, ®, false); 233 *gic_bmp_ptr32(bmp, irq) = reg; 234 } 235 } 236 237 static void kvm_gic_put_line_level_bmp(GICv3State *s, uint32_t *bmp) 238 { 239 uint32_t reg; 240 int irq; 241 242 for_each_dist_irq_reg(irq, s->num_irq, 1) { 243 reg = *gic_bmp_ptr32(bmp, irq); 244 kvm_gic_line_level_access(s, irq, 0, ®, true); 245 } 246 } 247 248 /* Read a bitmap register group from the kernel VGIC. */ 249 static void kvm_dist_getbmp(GICv3State *s, uint32_t offset, uint32_t *bmp) 250 { 251 uint32_t reg; 252 int irq; 253 254 /* For the KVM GICv3, affinity routing is always enabled, and the 255 * GICD_IGROUPR0/GICD_IGRPMODR0/GICD_ISENABLER0/GICD_ISPENDR0/ 256 * GICD_ISACTIVER0 registers are always RAZ/WI. The corresponding 257 * functionality is replaced by the GICR registers. It doesn't need to sync 258 * them. So it should increase the offset to skip GIC_INTERNAL irqs. 259 * This matches the for_each_dist_irq_reg() macro which also skips the 260 * first GIC_INTERNAL irqs. 261 */ 262 offset += (GIC_INTERNAL * 1) / 8; 263 for_each_dist_irq_reg(irq, s->num_irq, 1) { 264 kvm_gicd_access(s, offset, ®, false); 265 *gic_bmp_ptr32(bmp, irq) = reg; 266 offset += 4; 267 } 268 } 269 270 static void kvm_dist_putbmp(GICv3State *s, uint32_t offset, 271 uint32_t clroffset, uint32_t *bmp) 272 { 273 uint32_t reg; 274 int irq; 275 276 /* For the KVM GICv3, affinity routing is always enabled, and the 277 * GICD_IGROUPR0/GICD_IGRPMODR0/GICD_ISENABLER0/GICD_ISPENDR0/ 278 * GICD_ISACTIVER0 registers are always RAZ/WI. The corresponding 279 * functionality is replaced by the GICR registers. It doesn't need to sync 280 * them. So it should increase the offset and clroffset to skip GIC_INTERNAL 281 * irqs. This matches the for_each_dist_irq_reg() macro which also skips the 282 * first GIC_INTERNAL irqs. 283 */ 284 offset += (GIC_INTERNAL * 1) / 8; 285 if (clroffset != 0) { 286 clroffset += (GIC_INTERNAL * 1) / 8; 287 } 288 289 for_each_dist_irq_reg(irq, s->num_irq, 1) { 290 /* If this bitmap is a set/clear register pair, first write to the 291 * clear-reg to clear all bits before using the set-reg to write 292 * the 1 bits. 293 */ 294 if (clroffset != 0) { 295 reg = 0; 296 kvm_gicd_access(s, clroffset, ®, true); 297 clroffset += 4; 298 } 299 reg = *gic_bmp_ptr32(bmp, irq); 300 kvm_gicd_access(s, offset, ®, true); 301 offset += 4; 302 } 303 } 304 305 static void kvm_arm_gicv3_check(GICv3State *s) 306 { 307 uint32_t reg; 308 uint32_t num_irq; 309 310 /* Sanity checking s->num_irq */ 311 kvm_gicd_access(s, GICD_TYPER, ®, false); 312 num_irq = ((reg & 0x1f) + 1) * 32; 313 314 if (num_irq < s->num_irq) { 315 error_report("Model requests %u IRQs, but kernel supports max %u", 316 s->num_irq, num_irq); 317 abort(); 318 } 319 } 320 321 static void kvm_arm_gicv3_put(GICv3State *s) 322 { 323 uint32_t regl, regh, reg; 324 uint64_t reg64, redist_typer; 325 int ncpu, i; 326 327 kvm_arm_gicv3_check(s); 328 329 kvm_gicr_access(s, GICR_TYPER, 0, ®l, false); 330 kvm_gicr_access(s, GICR_TYPER + 4, 0, ®h, false); 331 redist_typer = ((uint64_t)regh << 32) | regl; 332 333 reg = s->gicd_ctlr; 334 kvm_gicd_access(s, GICD_CTLR, ®, true); 335 336 if (redist_typer & GICR_TYPER_PLPIS) { 337 /* 338 * Restore base addresses before LPIs are potentially enabled by 339 * GICR_CTLR write 340 */ 341 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 342 GICv3CPUState *c = &s->cpu[ncpu]; 343 344 reg64 = c->gicr_propbaser; 345 regl = (uint32_t)reg64; 346 kvm_gicr_access(s, GICR_PROPBASER, ncpu, ®l, true); 347 regh = (uint32_t)(reg64 >> 32); 348 kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, ®h, true); 349 350 reg64 = c->gicr_pendbaser; 351 regl = (uint32_t)reg64; 352 kvm_gicr_access(s, GICR_PENDBASER, ncpu, ®l, true); 353 regh = (uint32_t)(reg64 >> 32); 354 kvm_gicr_access(s, GICR_PENDBASER + 4, ncpu, ®h, true); 355 } 356 } 357 358 /* Redistributor state (one per CPU) */ 359 360 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 361 GICv3CPUState *c = &s->cpu[ncpu]; 362 363 reg = c->gicr_ctlr; 364 kvm_gicr_access(s, GICR_CTLR, ncpu, ®, true); 365 366 reg = c->gicr_statusr[GICV3_NS]; 367 kvm_gicr_access(s, GICR_STATUSR, ncpu, ®, true); 368 369 reg = c->gicr_waker; 370 kvm_gicr_access(s, GICR_WAKER, ncpu, ®, true); 371 372 reg = c->gicr_igroupr0; 373 kvm_gicr_access(s, GICR_IGROUPR0, ncpu, ®, true); 374 375 reg = ~0; 376 kvm_gicr_access(s, GICR_ICENABLER0, ncpu, ®, true); 377 reg = c->gicr_ienabler0; 378 kvm_gicr_access(s, GICR_ISENABLER0, ncpu, ®, true); 379 380 /* Restore config before pending so we treat level/edge correctly */ 381 reg = half_shuffle32(c->edge_trigger >> 16) << 1; 382 kvm_gicr_access(s, GICR_ICFGR1, ncpu, ®, true); 383 384 reg = c->level; 385 kvm_gic_line_level_access(s, 0, ncpu, ®, true); 386 387 reg = ~0; 388 kvm_gicr_access(s, GICR_ICPENDR0, ncpu, ®, true); 389 reg = c->gicr_ipendr0; 390 kvm_gicr_access(s, GICR_ISPENDR0, ncpu, ®, true); 391 392 reg = ~0; 393 kvm_gicr_access(s, GICR_ICACTIVER0, ncpu, ®, true); 394 reg = c->gicr_iactiver0; 395 kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, ®, true); 396 397 for (i = 0; i < GIC_INTERNAL; i += 4) { 398 reg = c->gicr_ipriorityr[i] | 399 (c->gicr_ipriorityr[i + 1] << 8) | 400 (c->gicr_ipriorityr[i + 2] << 16) | 401 (c->gicr_ipriorityr[i + 3] << 24); 402 kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, ®, true); 403 } 404 } 405 406 /* Distributor state (shared between all CPUs */ 407 reg = s->gicd_statusr[GICV3_NS]; 408 kvm_gicd_access(s, GICD_STATUSR, ®, true); 409 410 /* s->enable bitmap -> GICD_ISENABLERn */ 411 kvm_dist_putbmp(s, GICD_ISENABLER, GICD_ICENABLER, s->enabled); 412 413 /* s->group bitmap -> GICD_IGROUPRn */ 414 kvm_dist_putbmp(s, GICD_IGROUPR, 0, s->group); 415 416 /* Restore targets before pending to ensure the pending state is set on 417 * the appropriate CPU interfaces in the kernel 418 */ 419 420 /* s->gicd_irouter[irq] -> GICD_IROUTERn 421 * We can't use kvm_dist_put() here because the registers are 64-bit 422 */ 423 for (i = GIC_INTERNAL; i < s->num_irq; i++) { 424 uint32_t offset; 425 426 offset = GICD_IROUTER + (sizeof(uint32_t) * i); 427 reg = (uint32_t)s->gicd_irouter[i]; 428 kvm_gicd_access(s, offset, ®, true); 429 430 offset = GICD_IROUTER + (sizeof(uint32_t) * i) + 4; 431 reg = (uint32_t)(s->gicd_irouter[i] >> 32); 432 kvm_gicd_access(s, offset, ®, true); 433 } 434 435 /* s->trigger bitmap -> GICD_ICFGRn 436 * (restore configuration registers before pending IRQs so we treat 437 * level/edge correctly) 438 */ 439 kvm_dist_put_edge_trigger(s, GICD_ICFGR, s->edge_trigger); 440 441 /* s->level bitmap -> line_level */ 442 kvm_gic_put_line_level_bmp(s, s->level); 443 444 /* s->pending bitmap -> GICD_ISPENDRn */ 445 kvm_dist_putbmp(s, GICD_ISPENDR, GICD_ICPENDR, s->pending); 446 447 /* s->active bitmap -> GICD_ISACTIVERn */ 448 kvm_dist_putbmp(s, GICD_ISACTIVER, GICD_ICACTIVER, s->active); 449 450 /* s->gicd_ipriority[] -> GICD_IPRIORITYRn */ 451 kvm_dist_put_priority(s, GICD_IPRIORITYR, s->gicd_ipriority); 452 453 /* CPU Interface state (one per CPU) */ 454 455 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 456 GICv3CPUState *c = &s->cpu[ncpu]; 457 int num_pri_bits; 458 459 kvm_gicc_access(s, ICC_SRE_EL1, ncpu, &c->icc_sre_el1, true); 460 kvm_gicc_access(s, ICC_CTLR_EL1, ncpu, 461 &c->icc_ctlr_el1[GICV3_NS], true); 462 kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu, 463 &c->icc_igrpen[GICV3_G0], true); 464 kvm_gicc_access(s, ICC_IGRPEN1_EL1, ncpu, 465 &c->icc_igrpen[GICV3_G1NS], true); 466 kvm_gicc_access(s, ICC_PMR_EL1, ncpu, &c->icc_pmr_el1, true); 467 kvm_gicc_access(s, ICC_BPR0_EL1, ncpu, &c->icc_bpr[GICV3_G0], true); 468 kvm_gicc_access(s, ICC_BPR1_EL1, ncpu, &c->icc_bpr[GICV3_G1NS], true); 469 470 num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] & 471 ICC_CTLR_EL1_PRIBITS_MASK) >> 472 ICC_CTLR_EL1_PRIBITS_SHIFT) + 1; 473 474 switch (num_pri_bits) { 475 case 7: 476 reg64 = c->icc_apr[GICV3_G0][3]; 477 kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, ®64, true); 478 reg64 = c->icc_apr[GICV3_G0][2]; 479 kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, ®64, true); 480 /* fall through */ 481 case 6: 482 reg64 = c->icc_apr[GICV3_G0][1]; 483 kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, ®64, true); 484 /* fall through */ 485 default: 486 reg64 = c->icc_apr[GICV3_G0][0]; 487 kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, ®64, true); 488 } 489 490 switch (num_pri_bits) { 491 case 7: 492 reg64 = c->icc_apr[GICV3_G1NS][3]; 493 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, ®64, true); 494 reg64 = c->icc_apr[GICV3_G1NS][2]; 495 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, ®64, true); 496 /* fall through */ 497 case 6: 498 reg64 = c->icc_apr[GICV3_G1NS][1]; 499 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, ®64, true); 500 /* fall through */ 501 default: 502 reg64 = c->icc_apr[GICV3_G1NS][0]; 503 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, ®64, true); 504 } 505 } 506 } 507 508 static void kvm_arm_gicv3_get(GICv3State *s) 509 { 510 uint32_t regl, regh, reg; 511 uint64_t reg64, redist_typer; 512 int ncpu, i; 513 514 kvm_arm_gicv3_check(s); 515 516 kvm_gicr_access(s, GICR_TYPER, 0, ®l, false); 517 kvm_gicr_access(s, GICR_TYPER + 4, 0, ®h, false); 518 redist_typer = ((uint64_t)regh << 32) | regl; 519 520 kvm_gicd_access(s, GICD_CTLR, ®, false); 521 s->gicd_ctlr = reg; 522 523 /* Redistributor state (one per CPU) */ 524 525 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 526 GICv3CPUState *c = &s->cpu[ncpu]; 527 528 kvm_gicr_access(s, GICR_CTLR, ncpu, ®, false); 529 c->gicr_ctlr = reg; 530 531 kvm_gicr_access(s, GICR_STATUSR, ncpu, ®, false); 532 c->gicr_statusr[GICV3_NS] = reg; 533 534 kvm_gicr_access(s, GICR_WAKER, ncpu, ®, false); 535 c->gicr_waker = reg; 536 537 kvm_gicr_access(s, GICR_IGROUPR0, ncpu, ®, false); 538 c->gicr_igroupr0 = reg; 539 kvm_gicr_access(s, GICR_ISENABLER0, ncpu, ®, false); 540 c->gicr_ienabler0 = reg; 541 kvm_gicr_access(s, GICR_ICFGR1, ncpu, ®, false); 542 c->edge_trigger = half_unshuffle32(reg >> 1) << 16; 543 kvm_gic_line_level_access(s, 0, ncpu, ®, false); 544 c->level = reg; 545 kvm_gicr_access(s, GICR_ISPENDR0, ncpu, ®, false); 546 c->gicr_ipendr0 = reg; 547 kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, ®, false); 548 c->gicr_iactiver0 = reg; 549 550 for (i = 0; i < GIC_INTERNAL; i += 4) { 551 kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, ®, false); 552 c->gicr_ipriorityr[i] = extract32(reg, 0, 8); 553 c->gicr_ipriorityr[i + 1] = extract32(reg, 8, 8); 554 c->gicr_ipriorityr[i + 2] = extract32(reg, 16, 8); 555 c->gicr_ipriorityr[i + 3] = extract32(reg, 24, 8); 556 } 557 } 558 559 if (redist_typer & GICR_TYPER_PLPIS) { 560 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 561 GICv3CPUState *c = &s->cpu[ncpu]; 562 563 kvm_gicr_access(s, GICR_PROPBASER, ncpu, ®l, false); 564 kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, ®h, false); 565 c->gicr_propbaser = ((uint64_t)regh << 32) | regl; 566 567 kvm_gicr_access(s, GICR_PENDBASER, ncpu, ®l, false); 568 kvm_gicr_access(s, GICR_PENDBASER + 4, ncpu, ®h, false); 569 c->gicr_pendbaser = ((uint64_t)regh << 32) | regl; 570 } 571 } 572 573 /* Distributor state (shared between all CPUs */ 574 575 kvm_gicd_access(s, GICD_STATUSR, ®, false); 576 s->gicd_statusr[GICV3_NS] = reg; 577 578 /* GICD_IGROUPRn -> s->group bitmap */ 579 kvm_dist_getbmp(s, GICD_IGROUPR, s->group); 580 581 /* GICD_ISENABLERn -> s->enabled bitmap */ 582 kvm_dist_getbmp(s, GICD_ISENABLER, s->enabled); 583 584 /* Line level of irq */ 585 kvm_gic_get_line_level_bmp(s, s->level); 586 /* GICD_ISPENDRn -> s->pending bitmap */ 587 kvm_dist_getbmp(s, GICD_ISPENDR, s->pending); 588 589 /* GICD_ISACTIVERn -> s->active bitmap */ 590 kvm_dist_getbmp(s, GICD_ISACTIVER, s->active); 591 592 /* GICD_ICFGRn -> s->trigger bitmap */ 593 kvm_dist_get_edge_trigger(s, GICD_ICFGR, s->edge_trigger); 594 595 /* GICD_IPRIORITYRn -> s->gicd_ipriority[] */ 596 kvm_dist_get_priority(s, GICD_IPRIORITYR, s->gicd_ipriority); 597 598 /* GICD_IROUTERn -> s->gicd_irouter[irq] */ 599 for (i = GIC_INTERNAL; i < s->num_irq; i++) { 600 uint32_t offset; 601 602 offset = GICD_IROUTER + (sizeof(uint32_t) * i); 603 kvm_gicd_access(s, offset, ®l, false); 604 offset = GICD_IROUTER + (sizeof(uint32_t) * i) + 4; 605 kvm_gicd_access(s, offset, ®h, false); 606 s->gicd_irouter[i] = ((uint64_t)regh << 32) | regl; 607 } 608 609 /***************************************************************** 610 * CPU Interface(s) State 611 */ 612 613 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 614 GICv3CPUState *c = &s->cpu[ncpu]; 615 int num_pri_bits; 616 617 kvm_gicc_access(s, ICC_SRE_EL1, ncpu, &c->icc_sre_el1, false); 618 kvm_gicc_access(s, ICC_CTLR_EL1, ncpu, 619 &c->icc_ctlr_el1[GICV3_NS], false); 620 kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu, 621 &c->icc_igrpen[GICV3_G0], false); 622 kvm_gicc_access(s, ICC_IGRPEN1_EL1, ncpu, 623 &c->icc_igrpen[GICV3_G1NS], false); 624 kvm_gicc_access(s, ICC_PMR_EL1, ncpu, &c->icc_pmr_el1, false); 625 kvm_gicc_access(s, ICC_BPR0_EL1, ncpu, &c->icc_bpr[GICV3_G0], false); 626 kvm_gicc_access(s, ICC_BPR1_EL1, ncpu, &c->icc_bpr[GICV3_G1NS], false); 627 num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] & 628 ICC_CTLR_EL1_PRIBITS_MASK) >> 629 ICC_CTLR_EL1_PRIBITS_SHIFT) + 1; 630 631 switch (num_pri_bits) { 632 case 7: 633 kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, ®64, false); 634 c->icc_apr[GICV3_G0][3] = reg64; 635 kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, ®64, false); 636 c->icc_apr[GICV3_G0][2] = reg64; 637 /* fall through */ 638 case 6: 639 kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, ®64, false); 640 c->icc_apr[GICV3_G0][1] = reg64; 641 /* fall through */ 642 default: 643 kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, ®64, false); 644 c->icc_apr[GICV3_G0][0] = reg64; 645 } 646 647 switch (num_pri_bits) { 648 case 7: 649 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, ®64, false); 650 c->icc_apr[GICV3_G1NS][3] = reg64; 651 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, ®64, false); 652 c->icc_apr[GICV3_G1NS][2] = reg64; 653 /* fall through */ 654 case 6: 655 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, ®64, false); 656 c->icc_apr[GICV3_G1NS][1] = reg64; 657 /* fall through */ 658 default: 659 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, ®64, false); 660 c->icc_apr[GICV3_G1NS][0] = reg64; 661 } 662 } 663 } 664 665 static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) 666 { 667 GICv3State *s; 668 GICv3CPUState *c; 669 670 c = (GICv3CPUState *)env->gicv3state; 671 s = c->gic; 672 673 c->icc_pmr_el1 = 0; 674 c->icc_bpr[GICV3_G0] = GIC_MIN_BPR; 675 c->icc_bpr[GICV3_G1] = GIC_MIN_BPR; 676 c->icc_bpr[GICV3_G1NS] = GIC_MIN_BPR; 677 678 c->icc_sre_el1 = 0x7; 679 memset(c->icc_apr, 0, sizeof(c->icc_apr)); 680 memset(c->icc_igrpen, 0, sizeof(c->icc_igrpen)); 681 682 if (s->migration_blocker) { 683 return; 684 } 685 686 /* Initialize to actual HW supported configuration */ 687 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, 688 KVM_VGIC_ATTR(ICC_CTLR_EL1, c->gicr_typer), 689 &c->icc_ctlr_el1[GICV3_NS], false, &error_abort); 690 691 c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS]; 692 } 693 694 static void kvm_arm_gicv3_reset(DeviceState *dev) 695 { 696 GICv3State *s = ARM_GICV3_COMMON(dev); 697 KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s); 698 699 DPRINTF("Reset\n"); 700 701 kgc->parent_reset(dev); 702 703 if (s->migration_blocker) { 704 DPRINTF("Cannot put kernel gic state, no kernel interface\n"); 705 return; 706 } 707 708 kvm_arm_gicv3_put(s); 709 } 710 711 /* 712 * CPU interface registers of GIC needs to be reset on CPU reset. 713 * For the calling arm_gicv3_icc_reset() on CPU reset, we register 714 * below ARMCPRegInfo. As we reset the whole cpu interface under single 715 * register reset, we define only one register of CPU interface instead 716 * of defining all the registers. 717 */ 718 static const ARMCPRegInfo gicv3_cpuif_reginfo[] = { 719 { .name = "ICC_CTLR_EL1", .state = ARM_CP_STATE_BOTH, 720 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 4, 721 /* 722 * If ARM_CP_NOP is used, resetfn is not called, 723 * So ARM_CP_NO_RAW is appropriate type. 724 */ 725 .type = ARM_CP_NO_RAW, 726 .access = PL1_RW, 727 .readfn = arm_cp_read_zero, 728 .writefn = arm_cp_write_ignore, 729 /* 730 * We hang the whole cpu interface reset routine off here 731 * rather than parcelling it out into one little function 732 * per register 733 */ 734 .resetfn = arm_gicv3_icc_reset, 735 }, 736 REGINFO_SENTINEL 737 }; 738 739 /** 740 * vm_change_state_handler - VM change state callback aiming at flushing 741 * RDIST pending tables into guest RAM 742 * 743 * The tables get flushed to guest RAM whenever the VM gets stopped. 744 */ 745 static void vm_change_state_handler(void *opaque, bool running, 746 RunState state) 747 { 748 GICv3State *s = (GICv3State *)opaque; 749 Error *err = NULL; 750 int ret; 751 752 if (running) { 753 return; 754 } 755 756 ret = kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, 757 KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES, 758 NULL, true, &err); 759 if (err) { 760 error_report_err(err); 761 } 762 if (ret < 0 && ret != -EFAULT) { 763 abort(); 764 } 765 } 766 767 768 static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) 769 { 770 GICv3State *s = KVM_ARM_GICV3(dev); 771 KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s); 772 bool multiple_redist_region_allowed; 773 Error *local_err = NULL; 774 int i; 775 776 DPRINTF("kvm_arm_gicv3_realize\n"); 777 778 kgc->parent_realize(dev, &local_err); 779 if (local_err) { 780 error_propagate(errp, local_err); 781 return; 782 } 783 784 if (s->revision != 3) { 785 error_setg(errp, "unsupported GIC revision %d for in-kernel GIC", 786 s->revision); 787 } 788 789 if (s->security_extn) { 790 error_setg(errp, "the in-kernel VGICv3 does not implement the " 791 "security extensions"); 792 return; 793 } 794 795 gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL); 796 797 for (i = 0; i < s->num_cpu; i++) { 798 ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i)); 799 800 define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); 801 } 802 803 /* Try to create the device via the device control API */ 804 s->dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V3, false); 805 if (s->dev_fd < 0) { 806 error_setg_errno(errp, -s->dev_fd, "error creating in-kernel VGIC"); 807 return; 808 } 809 810 multiple_redist_region_allowed = 811 kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ADDR, 812 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION); 813 814 if (!multiple_redist_region_allowed && s->nb_redist_regions > 1) { 815 error_setg(errp, "Multiple VGICv3 redistributor regions are not " 816 "supported by this host kernel"); 817 error_append_hint(errp, "A maximum of %d VCPUs can be used", 818 s->redist_region_count[0]); 819 return; 820 } 821 822 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 823 0, &s->num_irq, true, &error_abort); 824 825 /* Tell the kernel to complete VGIC initialization now */ 826 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, 827 KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort); 828 829 kvm_arm_register_device(&s->iomem_dist, -1, KVM_DEV_ARM_VGIC_GRP_ADDR, 830 KVM_VGIC_V3_ADDR_TYPE_DIST, s->dev_fd, 0); 831 832 if (!multiple_redist_region_allowed) { 833 kvm_arm_register_device(&s->redist_regions[0].iomem, -1, 834 KVM_DEV_ARM_VGIC_GRP_ADDR, 835 KVM_VGIC_V3_ADDR_TYPE_REDIST, s->dev_fd, 0); 836 } else { 837 /* we register regions in reverse order as "devices" are inserted at 838 * the head of a QSLIST and the list is then popped from the head 839 * onwards by kvm_arm_machine_init_done() 840 */ 841 for (i = s->nb_redist_regions - 1; i >= 0; i--) { 842 /* Address mask made of the rdist region index and count */ 843 uint64_t addr_ormask = 844 i | ((uint64_t)s->redist_region_count[i] << 52); 845 846 kvm_arm_register_device(&s->redist_regions[i].iomem, -1, 847 KVM_DEV_ARM_VGIC_GRP_ADDR, 848 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION, 849 s->dev_fd, addr_ormask); 850 } 851 } 852 853 if (kvm_has_gsi_routing()) { 854 /* set up irq routing */ 855 for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) { 856 kvm_irqchip_add_irq_route(kvm_state, i, 0, i); 857 } 858 859 kvm_gsi_routing_allowed = true; 860 861 kvm_irqchip_commit_routes(kvm_state); 862 } 863 864 if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS, 865 GICD_CTLR)) { 866 error_setg(&s->migration_blocker, "This operating system kernel does " 867 "not support vGICv3 migration"); 868 if (migrate_add_blocker(s->migration_blocker, errp) < 0) { 869 error_free(s->migration_blocker); 870 return; 871 } 872 } 873 if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, 874 KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES)) { 875 qemu_add_vm_change_state_handler(vm_change_state_handler, s); 876 } 877 } 878 879 static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data) 880 { 881 DeviceClass *dc = DEVICE_CLASS(klass); 882 ARMGICv3CommonClass *agcc = ARM_GICV3_COMMON_CLASS(klass); 883 KVMARMGICv3Class *kgc = KVM_ARM_GICV3_CLASS(klass); 884 885 agcc->pre_save = kvm_arm_gicv3_get; 886 agcc->post_load = kvm_arm_gicv3_put; 887 device_class_set_parent_realize(dc, kvm_arm_gicv3_realize, 888 &kgc->parent_realize); 889 device_class_set_parent_reset(dc, kvm_arm_gicv3_reset, &kgc->parent_reset); 890 } 891 892 static const TypeInfo kvm_arm_gicv3_info = { 893 .name = TYPE_KVM_ARM_GICV3, 894 .parent = TYPE_ARM_GICV3_COMMON, 895 .instance_size = sizeof(GICv3State), 896 .class_init = kvm_arm_gicv3_class_init, 897 .class_size = sizeof(KVMARMGICv3Class), 898 }; 899 900 static void kvm_arm_gicv3_register_types(void) 901 { 902 type_register_static(&kvm_arm_gicv3_info); 903 } 904 905 type_init(kvm_arm_gicv3_register_types) 906