1 /* 2 * ARM Generic Interrupt Controller using KVM in-kernel support 3 * 4 * Copyright (c) 2015 Samsung Electronics Co., Ltd. 5 * Written by Pavel Fedin 6 * Based on vGICv2 code by Peter Maydell 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation, either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "hw/intc/arm_gicv3_common.h" 25 #include "hw/arm/virt.h" 26 #include "qemu/error-report.h" 27 #include "qemu/module.h" 28 #include "system/kvm.h" 29 #include "system/runstate.h" 30 #include "kvm_arm.h" 31 #include "gicv3_internal.h" 32 #include "vgic_common.h" 33 #include "migration/blocker.h" 34 #include "qom/object.h" 35 #include "target/arm/cpregs.h" 36 37 38 #ifdef DEBUG_GICV3_KVM 39 #define DPRINTF(fmt, ...) \ 40 do { fprintf(stderr, "kvm_gicv3: " fmt, ## __VA_ARGS__); } while (0) 41 #else 42 #define DPRINTF(fmt, ...) \ 43 do { } while (0) 44 #endif 45 46 #define TYPE_KVM_ARM_GICV3 "kvm-arm-gicv3" 47 typedef struct KVMARMGICv3Class KVMARMGICv3Class; 48 /* This is reusing the GICv3State typedef from ARM_GICV3_ITS_COMMON */ 49 DECLARE_OBJ_CHECKERS(GICv3State, KVMARMGICv3Class, 50 KVM_ARM_GICV3, TYPE_KVM_ARM_GICV3) 51 52 #define KVM_DEV_ARM_VGIC_SYSREG(op0, op1, crn, crm, op2) \ 53 (ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \ 54 ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \ 55 ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \ 56 ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \ 57 ARM64_SYS_REG_SHIFT_MASK(op2, OP2)) 58 59 #define ICC_PMR_EL1 \ 60 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 4, 6, 0) 61 #define ICC_BPR0_EL1 \ 62 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 8, 3) 63 #define ICC_AP0R_EL1(n) \ 64 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 8, 4 | n) 65 #define ICC_AP1R_EL1(n) \ 66 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 9, n) 67 #define ICC_BPR1_EL1 \ 68 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 3) 69 #define ICC_CTLR_EL1 \ 70 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 4) 71 #define ICC_SRE_EL1 \ 72 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 5) 73 #define ICC_IGRPEN0_EL1 \ 74 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 6) 75 #define ICC_IGRPEN1_EL1 \ 76 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 7) 77 78 struct KVMARMGICv3Class { 79 ARMGICv3CommonClass parent_class; 80 DeviceRealize parent_realize; 81 ResettablePhases parent_phases; 82 }; 83 84 static void kvm_arm_gicv3_set_irq(void *opaque, int irq, int level) 85 { 86 GICv3State *s = (GICv3State *)opaque; 87 88 kvm_arm_gic_set_irq(s->num_irq, irq, level); 89 } 90 91 #define KVM_VGIC_ATTR(reg, typer) \ 92 ((typer & KVM_DEV_ARM_VGIC_V3_MPIDR_MASK) | (reg)) 93 94 static inline void kvm_gicd_access(GICv3State *s, int offset, 95 uint32_t *val, bool write) 96 { 97 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS, 98 KVM_VGIC_ATTR(offset, 0), 99 val, write, &error_abort); 100 } 101 102 static inline void kvm_gicr_access(GICv3State *s, int offset, int cpu, 103 uint32_t *val, bool write) 104 { 105 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS, 106 KVM_VGIC_ATTR(offset, s->cpu[cpu].gicr_typer), 107 val, write, &error_abort); 108 } 109 110 static inline void kvm_gicc_access(GICv3State *s, uint64_t reg, int cpu, 111 uint64_t *val, bool write) 112 { 113 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, 114 KVM_VGIC_ATTR(reg, s->cpu[cpu].gicr_typer), 115 val, write, &error_abort); 116 } 117 118 static inline void kvm_gic_line_level_access(GICv3State *s, int irq, int cpu, 119 uint32_t *val, bool write) 120 { 121 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO, 122 KVM_VGIC_ATTR(irq, s->cpu[cpu].gicr_typer) | 123 (VGIC_LEVEL_INFO_LINE_LEVEL << 124 KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT), 125 val, write, &error_abort); 126 } 127 128 /* Loop through each distributor IRQ related register; since bits 129 * corresponding to SPIs and PPIs are RAZ/WI when affinity routing 130 * is enabled, we skip those. 131 */ 132 #define for_each_dist_irq_reg(_irq, _max, _field_width) \ 133 for (_irq = GIC_INTERNAL; _irq < _max; _irq += (32 / _field_width)) 134 135 static void kvm_dist_get_priority(GICv3State *s, uint32_t offset, uint8_t *bmp) 136 { 137 uint32_t reg, *field; 138 int irq; 139 140 /* For the KVM GICv3, affinity routing is always enabled, and the first 8 141 * GICD_IPRIORITYR<n> registers are always RAZ/WI. The corresponding 142 * functionality is replaced by GICR_IPRIORITYR<n>. It doesn't need to 143 * sync them. So it needs to skip the field of GIC_INTERNAL irqs in bmp and 144 * offset. 145 */ 146 field = (uint32_t *)(bmp + GIC_INTERNAL); 147 offset += (GIC_INTERNAL * 8) / 8; 148 for_each_dist_irq_reg(irq, s->num_irq, 8) { 149 kvm_gicd_access(s, offset, ®, false); 150 *field = reg; 151 offset += 4; 152 field++; 153 } 154 } 155 156 static void kvm_dist_put_priority(GICv3State *s, uint32_t offset, uint8_t *bmp) 157 { 158 uint32_t reg, *field; 159 int irq; 160 161 /* For the KVM GICv3, affinity routing is always enabled, and the first 8 162 * GICD_IPRIORITYR<n> registers are always RAZ/WI. The corresponding 163 * functionality is replaced by GICR_IPRIORITYR<n>. It doesn't need to 164 * sync them. So it needs to skip the field of GIC_INTERNAL irqs in bmp and 165 * offset. 166 */ 167 field = (uint32_t *)(bmp + GIC_INTERNAL); 168 offset += (GIC_INTERNAL * 8) / 8; 169 for_each_dist_irq_reg(irq, s->num_irq, 8) { 170 reg = *field; 171 kvm_gicd_access(s, offset, ®, true); 172 offset += 4; 173 field++; 174 } 175 } 176 177 static void kvm_dist_get_edge_trigger(GICv3State *s, uint32_t offset, 178 uint32_t *bmp) 179 { 180 uint32_t reg; 181 int irq; 182 183 /* For the KVM GICv3, affinity routing is always enabled, and the first 2 184 * GICD_ICFGR<n> registers are always RAZ/WI. The corresponding 185 * functionality is replaced by GICR_ICFGR<n>. It doesn't need to sync 186 * them. So it should increase the offset to skip GIC_INTERNAL irqs. 187 * This matches the for_each_dist_irq_reg() macro which also skips the 188 * first GIC_INTERNAL irqs. 189 */ 190 offset += (GIC_INTERNAL * 2) / 8; 191 for_each_dist_irq_reg(irq, s->num_irq, 2) { 192 kvm_gicd_access(s, offset, ®, false); 193 reg = half_unshuffle32(reg >> 1); 194 if (irq % 32 != 0) { 195 reg = (reg << 16); 196 } 197 *gic_bmp_ptr32(bmp, irq) |= reg; 198 offset += 4; 199 } 200 } 201 202 static void kvm_dist_put_edge_trigger(GICv3State *s, uint32_t offset, 203 uint32_t *bmp) 204 { 205 uint32_t reg; 206 int irq; 207 208 /* For the KVM GICv3, affinity routing is always enabled, and the first 2 209 * GICD_ICFGR<n> registers are always RAZ/WI. The corresponding 210 * functionality is replaced by GICR_ICFGR<n>. It doesn't need to sync 211 * them. So it should increase the offset to skip GIC_INTERNAL irqs. 212 * This matches the for_each_dist_irq_reg() macro which also skips the 213 * first GIC_INTERNAL irqs. 214 */ 215 offset += (GIC_INTERNAL * 2) / 8; 216 for_each_dist_irq_reg(irq, s->num_irq, 2) { 217 reg = *gic_bmp_ptr32(bmp, irq); 218 if (irq % 32 != 0) { 219 reg = (reg & 0xffff0000) >> 16; 220 } else { 221 reg = reg & 0xffff; 222 } 223 reg = half_shuffle32(reg) << 1; 224 kvm_gicd_access(s, offset, ®, true); 225 offset += 4; 226 } 227 } 228 229 static void kvm_gic_get_line_level_bmp(GICv3State *s, uint32_t *bmp) 230 { 231 uint32_t reg; 232 int irq; 233 234 for_each_dist_irq_reg(irq, s->num_irq, 1) { 235 kvm_gic_line_level_access(s, irq, 0, ®, false); 236 *gic_bmp_ptr32(bmp, irq) = reg; 237 } 238 } 239 240 static void kvm_gic_put_line_level_bmp(GICv3State *s, uint32_t *bmp) 241 { 242 uint32_t reg; 243 int irq; 244 245 for_each_dist_irq_reg(irq, s->num_irq, 1) { 246 reg = *gic_bmp_ptr32(bmp, irq); 247 kvm_gic_line_level_access(s, irq, 0, ®, true); 248 } 249 } 250 251 /* Read a bitmap register group from the kernel VGIC. */ 252 static void kvm_dist_getbmp(GICv3State *s, uint32_t offset, uint32_t *bmp) 253 { 254 uint32_t reg; 255 int irq; 256 257 /* For the KVM GICv3, affinity routing is always enabled, and the 258 * GICD_IGROUPR0/GICD_IGRPMODR0/GICD_ISENABLER0/GICD_ISPENDR0/ 259 * GICD_ISACTIVER0 registers are always RAZ/WI. The corresponding 260 * functionality is replaced by the GICR registers. It doesn't need to sync 261 * them. So it should increase the offset to skip GIC_INTERNAL irqs. 262 * This matches the for_each_dist_irq_reg() macro which also skips the 263 * first GIC_INTERNAL irqs. 264 */ 265 offset += (GIC_INTERNAL * 1) / 8; 266 for_each_dist_irq_reg(irq, s->num_irq, 1) { 267 kvm_gicd_access(s, offset, ®, false); 268 *gic_bmp_ptr32(bmp, irq) = reg; 269 offset += 4; 270 } 271 } 272 273 static void kvm_dist_putbmp(GICv3State *s, uint32_t offset, 274 uint32_t clroffset, uint32_t *bmp) 275 { 276 uint32_t reg; 277 int irq; 278 279 /* For the KVM GICv3, affinity routing is always enabled, and the 280 * GICD_IGROUPR0/GICD_IGRPMODR0/GICD_ISENABLER0/GICD_ISPENDR0/ 281 * GICD_ISACTIVER0 registers are always RAZ/WI. The corresponding 282 * functionality is replaced by the GICR registers. It doesn't need to sync 283 * them. So it should increase the offset and clroffset to skip GIC_INTERNAL 284 * irqs. This matches the for_each_dist_irq_reg() macro which also skips the 285 * first GIC_INTERNAL irqs. 286 */ 287 offset += (GIC_INTERNAL * 1) / 8; 288 if (clroffset != 0) { 289 clroffset += (GIC_INTERNAL * 1) / 8; 290 } 291 292 for_each_dist_irq_reg(irq, s->num_irq, 1) { 293 /* If this bitmap is a set/clear register pair, first write to the 294 * clear-reg to clear all bits before using the set-reg to write 295 * the 1 bits. 296 */ 297 if (clroffset != 0) { 298 reg = 0; 299 kvm_gicd_access(s, clroffset, ®, true); 300 clroffset += 4; 301 } 302 reg = *gic_bmp_ptr32(bmp, irq); 303 kvm_gicd_access(s, offset, ®, true); 304 offset += 4; 305 } 306 } 307 308 static void kvm_arm_gicv3_check(GICv3State *s) 309 { 310 uint32_t reg; 311 uint32_t num_irq; 312 313 /* Sanity checking s->num_irq */ 314 kvm_gicd_access(s, GICD_TYPER, ®, false); 315 num_irq = ((reg & 0x1f) + 1) * 32; 316 317 if (num_irq < s->num_irq) { 318 error_report("Model requests %u IRQs, but kernel supports max %u", 319 s->num_irq, num_irq); 320 abort(); 321 } 322 } 323 324 static void kvm_arm_gicv3_put(GICv3State *s) 325 { 326 uint32_t regl, regh, reg; 327 uint64_t reg64, redist_typer; 328 int ncpu, i; 329 330 kvm_arm_gicv3_check(s); 331 332 kvm_gicr_access(s, GICR_TYPER, 0, ®l, false); 333 kvm_gicr_access(s, GICR_TYPER + 4, 0, ®h, false); 334 redist_typer = ((uint64_t)regh << 32) | regl; 335 336 reg = s->gicd_ctlr; 337 kvm_gicd_access(s, GICD_CTLR, ®, true); 338 339 if (redist_typer & GICR_TYPER_PLPIS) { 340 /* 341 * Restore base addresses before LPIs are potentially enabled by 342 * GICR_CTLR write 343 */ 344 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 345 GICv3CPUState *c = &s->cpu[ncpu]; 346 347 reg64 = c->gicr_propbaser; 348 regl = (uint32_t)reg64; 349 kvm_gicr_access(s, GICR_PROPBASER, ncpu, ®l, true); 350 regh = (uint32_t)(reg64 >> 32); 351 kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, ®h, true); 352 353 reg64 = c->gicr_pendbaser; 354 regl = (uint32_t)reg64; 355 kvm_gicr_access(s, GICR_PENDBASER, ncpu, ®l, true); 356 regh = (uint32_t)(reg64 >> 32); 357 kvm_gicr_access(s, GICR_PENDBASER + 4, ncpu, ®h, true); 358 } 359 } 360 361 /* Redistributor state (one per CPU) */ 362 363 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 364 GICv3CPUState *c = &s->cpu[ncpu]; 365 366 reg = c->gicr_ctlr; 367 kvm_gicr_access(s, GICR_CTLR, ncpu, ®, true); 368 369 reg = c->gicr_statusr[GICV3_NS]; 370 kvm_gicr_access(s, GICR_STATUSR, ncpu, ®, true); 371 372 reg = c->gicr_waker; 373 kvm_gicr_access(s, GICR_WAKER, ncpu, ®, true); 374 375 reg = c->gicr_igroupr0; 376 kvm_gicr_access(s, GICR_IGROUPR0, ncpu, ®, true); 377 378 reg = ~0; 379 kvm_gicr_access(s, GICR_ICENABLER0, ncpu, ®, true); 380 reg = c->gicr_ienabler0; 381 kvm_gicr_access(s, GICR_ISENABLER0, ncpu, ®, true); 382 383 /* Restore config before pending so we treat level/edge correctly */ 384 reg = half_shuffle32(c->edge_trigger >> 16) << 1; 385 kvm_gicr_access(s, GICR_ICFGR1, ncpu, ®, true); 386 387 reg = c->level; 388 kvm_gic_line_level_access(s, 0, ncpu, ®, true); 389 390 reg = ~0; 391 kvm_gicr_access(s, GICR_ICPENDR0, ncpu, ®, true); 392 reg = c->gicr_ipendr0; 393 kvm_gicr_access(s, GICR_ISPENDR0, ncpu, ®, true); 394 395 reg = ~0; 396 kvm_gicr_access(s, GICR_ICACTIVER0, ncpu, ®, true); 397 reg = c->gicr_iactiver0; 398 kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, ®, true); 399 400 for (i = 0; i < GIC_INTERNAL; i += 4) { 401 reg = c->gicr_ipriorityr[i] | 402 (c->gicr_ipriorityr[i + 1] << 8) | 403 (c->gicr_ipriorityr[i + 2] << 16) | 404 (c->gicr_ipriorityr[i + 3] << 24); 405 kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, ®, true); 406 } 407 } 408 409 /* Distributor state (shared between all CPUs */ 410 reg = s->gicd_statusr[GICV3_NS]; 411 kvm_gicd_access(s, GICD_STATUSR, ®, true); 412 413 /* s->enable bitmap -> GICD_ISENABLERn */ 414 kvm_dist_putbmp(s, GICD_ISENABLER, GICD_ICENABLER, s->enabled); 415 416 /* s->group bitmap -> GICD_IGROUPRn */ 417 kvm_dist_putbmp(s, GICD_IGROUPR, 0, s->group); 418 419 /* Restore targets before pending to ensure the pending state is set on 420 * the appropriate CPU interfaces in the kernel 421 */ 422 423 /* s->gicd_irouter[irq] -> GICD_IROUTERn 424 * We can't use kvm_dist_put() here because the registers are 64-bit 425 */ 426 for (i = GIC_INTERNAL; i < s->num_irq; i++) { 427 uint32_t offset; 428 429 offset = GICD_IROUTER + (sizeof(uint32_t) * i); 430 reg = (uint32_t)s->gicd_irouter[i]; 431 kvm_gicd_access(s, offset, ®, true); 432 433 offset = GICD_IROUTER + (sizeof(uint32_t) * i) + 4; 434 reg = (uint32_t)(s->gicd_irouter[i] >> 32); 435 kvm_gicd_access(s, offset, ®, true); 436 } 437 438 /* s->trigger bitmap -> GICD_ICFGRn 439 * (restore configuration registers before pending IRQs so we treat 440 * level/edge correctly) 441 */ 442 kvm_dist_put_edge_trigger(s, GICD_ICFGR, s->edge_trigger); 443 444 /* s->level bitmap -> line_level */ 445 kvm_gic_put_line_level_bmp(s, s->level); 446 447 /* s->pending bitmap -> GICD_ISPENDRn */ 448 kvm_dist_putbmp(s, GICD_ISPENDR, GICD_ICPENDR, s->pending); 449 450 /* s->active bitmap -> GICD_ISACTIVERn */ 451 kvm_dist_putbmp(s, GICD_ISACTIVER, GICD_ICACTIVER, s->active); 452 453 /* s->gicd_ipriority[] -> GICD_IPRIORITYRn */ 454 kvm_dist_put_priority(s, GICD_IPRIORITYR, s->gicd_ipriority); 455 456 /* CPU Interface state (one per CPU) */ 457 458 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 459 GICv3CPUState *c = &s->cpu[ncpu]; 460 int num_pri_bits; 461 462 kvm_gicc_access(s, ICC_SRE_EL1, ncpu, &c->icc_sre_el1, true); 463 kvm_gicc_access(s, ICC_CTLR_EL1, ncpu, 464 &c->icc_ctlr_el1[GICV3_NS], true); 465 kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu, 466 &c->icc_igrpen[GICV3_G0], true); 467 kvm_gicc_access(s, ICC_IGRPEN1_EL1, ncpu, 468 &c->icc_igrpen[GICV3_G1NS], true); 469 kvm_gicc_access(s, ICC_PMR_EL1, ncpu, &c->icc_pmr_el1, true); 470 kvm_gicc_access(s, ICC_BPR0_EL1, ncpu, &c->icc_bpr[GICV3_G0], true); 471 kvm_gicc_access(s, ICC_BPR1_EL1, ncpu, &c->icc_bpr[GICV3_G1NS], true); 472 473 num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] & 474 ICC_CTLR_EL1_PRIBITS_MASK) >> 475 ICC_CTLR_EL1_PRIBITS_SHIFT) + 1; 476 477 switch (num_pri_bits) { 478 case 7: 479 reg64 = c->icc_apr[GICV3_G0][3]; 480 kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, ®64, true); 481 reg64 = c->icc_apr[GICV3_G0][2]; 482 kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, ®64, true); 483 /* fall through */ 484 case 6: 485 reg64 = c->icc_apr[GICV3_G0][1]; 486 kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, ®64, true); 487 /* fall through */ 488 default: 489 reg64 = c->icc_apr[GICV3_G0][0]; 490 kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, ®64, true); 491 } 492 493 switch (num_pri_bits) { 494 case 7: 495 reg64 = c->icc_apr[GICV3_G1NS][3]; 496 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, ®64, true); 497 reg64 = c->icc_apr[GICV3_G1NS][2]; 498 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, ®64, true); 499 /* fall through */ 500 case 6: 501 reg64 = c->icc_apr[GICV3_G1NS][1]; 502 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, ®64, true); 503 /* fall through */ 504 default: 505 reg64 = c->icc_apr[GICV3_G1NS][0]; 506 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, ®64, true); 507 } 508 } 509 } 510 511 static void kvm_arm_gicv3_get(GICv3State *s) 512 { 513 uint32_t regl, regh, reg; 514 uint64_t reg64, redist_typer; 515 int ncpu, i; 516 517 kvm_arm_gicv3_check(s); 518 519 kvm_gicr_access(s, GICR_TYPER, 0, ®l, false); 520 kvm_gicr_access(s, GICR_TYPER + 4, 0, ®h, false); 521 redist_typer = ((uint64_t)regh << 32) | regl; 522 523 kvm_gicd_access(s, GICD_CTLR, ®, false); 524 s->gicd_ctlr = reg; 525 526 /* Redistributor state (one per CPU) */ 527 528 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 529 GICv3CPUState *c = &s->cpu[ncpu]; 530 531 kvm_gicr_access(s, GICR_CTLR, ncpu, ®, false); 532 c->gicr_ctlr = reg; 533 534 kvm_gicr_access(s, GICR_STATUSR, ncpu, ®, false); 535 c->gicr_statusr[GICV3_NS] = reg; 536 537 kvm_gicr_access(s, GICR_WAKER, ncpu, ®, false); 538 c->gicr_waker = reg; 539 540 kvm_gicr_access(s, GICR_IGROUPR0, ncpu, ®, false); 541 c->gicr_igroupr0 = reg; 542 kvm_gicr_access(s, GICR_ISENABLER0, ncpu, ®, false); 543 c->gicr_ienabler0 = reg; 544 kvm_gicr_access(s, GICR_ICFGR1, ncpu, ®, false); 545 c->edge_trigger = half_unshuffle32(reg >> 1) << 16; 546 kvm_gic_line_level_access(s, 0, ncpu, ®, false); 547 c->level = reg; 548 kvm_gicr_access(s, GICR_ISPENDR0, ncpu, ®, false); 549 c->gicr_ipendr0 = reg; 550 kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, ®, false); 551 c->gicr_iactiver0 = reg; 552 553 for (i = 0; i < GIC_INTERNAL; i += 4) { 554 kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, ®, false); 555 c->gicr_ipriorityr[i] = extract32(reg, 0, 8); 556 c->gicr_ipriorityr[i + 1] = extract32(reg, 8, 8); 557 c->gicr_ipriorityr[i + 2] = extract32(reg, 16, 8); 558 c->gicr_ipriorityr[i + 3] = extract32(reg, 24, 8); 559 } 560 } 561 562 if (redist_typer & GICR_TYPER_PLPIS) { 563 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 564 GICv3CPUState *c = &s->cpu[ncpu]; 565 566 kvm_gicr_access(s, GICR_PROPBASER, ncpu, ®l, false); 567 kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, ®h, false); 568 c->gicr_propbaser = ((uint64_t)regh << 32) | regl; 569 570 kvm_gicr_access(s, GICR_PENDBASER, ncpu, ®l, false); 571 kvm_gicr_access(s, GICR_PENDBASER + 4, ncpu, ®h, false); 572 c->gicr_pendbaser = ((uint64_t)regh << 32) | regl; 573 } 574 } 575 576 /* Distributor state (shared between all CPUs */ 577 578 kvm_gicd_access(s, GICD_STATUSR, ®, false); 579 s->gicd_statusr[GICV3_NS] = reg; 580 581 /* GICD_IGROUPRn -> s->group bitmap */ 582 kvm_dist_getbmp(s, GICD_IGROUPR, s->group); 583 584 /* GICD_ISENABLERn -> s->enabled bitmap */ 585 kvm_dist_getbmp(s, GICD_ISENABLER, s->enabled); 586 587 /* Line level of irq */ 588 kvm_gic_get_line_level_bmp(s, s->level); 589 /* GICD_ISPENDRn -> s->pending bitmap */ 590 kvm_dist_getbmp(s, GICD_ISPENDR, s->pending); 591 592 /* GICD_ISACTIVERn -> s->active bitmap */ 593 kvm_dist_getbmp(s, GICD_ISACTIVER, s->active); 594 595 /* GICD_ICFGRn -> s->trigger bitmap */ 596 kvm_dist_get_edge_trigger(s, GICD_ICFGR, s->edge_trigger); 597 598 /* GICD_IPRIORITYRn -> s->gicd_ipriority[] */ 599 kvm_dist_get_priority(s, GICD_IPRIORITYR, s->gicd_ipriority); 600 601 /* GICD_IROUTERn -> s->gicd_irouter[irq] */ 602 for (i = GIC_INTERNAL; i < s->num_irq; i++) { 603 uint32_t offset; 604 605 offset = GICD_IROUTER + (sizeof(uint32_t) * i); 606 kvm_gicd_access(s, offset, ®l, false); 607 offset = GICD_IROUTER + (sizeof(uint32_t) * i) + 4; 608 kvm_gicd_access(s, offset, ®h, false); 609 s->gicd_irouter[i] = ((uint64_t)regh << 32) | regl; 610 } 611 612 /***************************************************************** 613 * CPU Interface(s) State 614 */ 615 616 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 617 GICv3CPUState *c = &s->cpu[ncpu]; 618 int num_pri_bits; 619 620 kvm_gicc_access(s, ICC_SRE_EL1, ncpu, &c->icc_sre_el1, false); 621 kvm_gicc_access(s, ICC_CTLR_EL1, ncpu, 622 &c->icc_ctlr_el1[GICV3_NS], false); 623 kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu, 624 &c->icc_igrpen[GICV3_G0], false); 625 kvm_gicc_access(s, ICC_IGRPEN1_EL1, ncpu, 626 &c->icc_igrpen[GICV3_G1NS], false); 627 kvm_gicc_access(s, ICC_PMR_EL1, ncpu, &c->icc_pmr_el1, false); 628 kvm_gicc_access(s, ICC_BPR0_EL1, ncpu, &c->icc_bpr[GICV3_G0], false); 629 kvm_gicc_access(s, ICC_BPR1_EL1, ncpu, &c->icc_bpr[GICV3_G1NS], false); 630 num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] & 631 ICC_CTLR_EL1_PRIBITS_MASK) >> 632 ICC_CTLR_EL1_PRIBITS_SHIFT) + 1; 633 634 switch (num_pri_bits) { 635 case 7: 636 kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, ®64, false); 637 c->icc_apr[GICV3_G0][3] = reg64; 638 kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, ®64, false); 639 c->icc_apr[GICV3_G0][2] = reg64; 640 /* fall through */ 641 case 6: 642 kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, ®64, false); 643 c->icc_apr[GICV3_G0][1] = reg64; 644 /* fall through */ 645 default: 646 kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, ®64, false); 647 c->icc_apr[GICV3_G0][0] = reg64; 648 } 649 650 switch (num_pri_bits) { 651 case 7: 652 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, ®64, false); 653 c->icc_apr[GICV3_G1NS][3] = reg64; 654 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, ®64, false); 655 c->icc_apr[GICV3_G1NS][2] = reg64; 656 /* fall through */ 657 case 6: 658 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, ®64, false); 659 c->icc_apr[GICV3_G1NS][1] = reg64; 660 /* fall through */ 661 default: 662 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, ®64, false); 663 c->icc_apr[GICV3_G1NS][0] = reg64; 664 } 665 } 666 } 667 668 static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) 669 { 670 GICv3State *s; 671 GICv3CPUState *c; 672 673 c = (GICv3CPUState *)env->gicv3state; 674 s = c->gic; 675 676 c->icc_pmr_el1 = 0; 677 /* 678 * Architecturally the reset value of the ICC_BPR registers 679 * is UNKNOWN. We set them all to 0 here; when the kernel 680 * uses these values to program the ICH_VMCR_EL2 fields that 681 * determine the guest-visible ICC_BPR register values, the 682 * hardware's "writing a value less than the minimum sets 683 * the field to the minimum value" behaviour will result in 684 * them effectively resetting to the correct minimum value 685 * for the host GIC. 686 */ 687 c->icc_bpr[GICV3_G0] = 0; 688 c->icc_bpr[GICV3_G1] = 0; 689 c->icc_bpr[GICV3_G1NS] = 0; 690 691 c->icc_sre_el1 = 0x7; 692 memset(c->icc_apr, 0, sizeof(c->icc_apr)); 693 memset(c->icc_igrpen, 0, sizeof(c->icc_igrpen)); 694 695 if (s->migration_blocker) { 696 return; 697 } 698 699 /* Initialize to actual HW supported configuration */ 700 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, 701 KVM_VGIC_ATTR(ICC_CTLR_EL1, c->gicr_typer), 702 &c->icc_ctlr_el1[GICV3_NS], false, &error_abort); 703 704 c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS]; 705 } 706 707 static void kvm_arm_gicv3_reset_hold(Object *obj, ResetType type) 708 { 709 GICv3State *s = ARM_GICV3_COMMON(obj); 710 KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s); 711 712 DPRINTF("Reset\n"); 713 714 if (kgc->parent_phases.hold) { 715 kgc->parent_phases.hold(obj, type); 716 } 717 718 if (s->migration_blocker) { 719 DPRINTF("Cannot put kernel gic state, no kernel interface\n"); 720 return; 721 } 722 723 kvm_arm_gicv3_put(s); 724 } 725 726 /* 727 * CPU interface registers of GIC needs to be reset on CPU reset. 728 * For the calling arm_gicv3_icc_reset() on CPU reset, we register 729 * below ARMCPRegInfo. As we reset the whole cpu interface under single 730 * register reset, we define only one register of CPU interface instead 731 * of defining all the registers. 732 */ 733 static const ARMCPRegInfo gicv3_cpuif_reginfo[] = { 734 { .name = "ICC_CTLR_EL1", .state = ARM_CP_STATE_BOTH, 735 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 4, 736 /* 737 * If ARM_CP_NOP is used, resetfn is not called, 738 * So ARM_CP_NO_RAW is appropriate type. 739 */ 740 .type = ARM_CP_NO_RAW, 741 .access = PL1_RW, 742 .readfn = arm_cp_read_zero, 743 .writefn = arm_cp_write_ignore, 744 /* 745 * We hang the whole cpu interface reset routine off here 746 * rather than parcelling it out into one little function 747 * per register 748 */ 749 .resetfn = arm_gicv3_icc_reset, 750 }, 751 }; 752 753 /** 754 * vm_change_state_handler - VM change state callback aiming at flushing 755 * RDIST pending tables into guest RAM 756 * 757 * The tables get flushed to guest RAM whenever the VM gets stopped. 758 */ 759 static void vm_change_state_handler(void *opaque, bool running, 760 RunState state) 761 { 762 GICv3State *s = (GICv3State *)opaque; 763 Error *err = NULL; 764 int ret; 765 766 if (running) { 767 return; 768 } 769 770 ret = kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, 771 KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES, 772 NULL, true, &err); 773 if (err) { 774 error_report_err(err); 775 } 776 if (ret < 0 && ret != -EFAULT) { 777 abort(); 778 } 779 } 780 781 782 static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) 783 { 784 GICv3State *s = KVM_ARM_GICV3(dev); 785 KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s); 786 bool multiple_redist_region_allowed; 787 Error *local_err = NULL; 788 int i; 789 790 DPRINTF("kvm_arm_gicv3_realize\n"); 791 792 kgc->parent_realize(dev, &local_err); 793 if (local_err) { 794 error_propagate(errp, local_err); 795 return; 796 } 797 798 if (s->revision != 3) { 799 error_setg(errp, "unsupported GIC revision %d for in-kernel GIC", 800 s->revision); 801 } 802 803 if (s->security_extn) { 804 error_setg(errp, "the in-kernel VGICv3 does not implement the " 805 "security extensions"); 806 return; 807 } 808 809 if (s->nmi_support) { 810 error_setg(errp, "NMI is not supported with the in-kernel GIC"); 811 return; 812 } 813 814 gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL); 815 816 for (i = 0; i < s->num_cpu; i++) { 817 ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i)); 818 819 define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); 820 } 821 822 /* Try to create the device via the device control API */ 823 s->dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V3, false); 824 if (s->dev_fd < 0) { 825 error_setg_errno(errp, -s->dev_fd, "error creating in-kernel VGIC"); 826 return; 827 } 828 829 if (s->maint_irq) { 830 Error *kvm_nv_migration_blocker = NULL; 831 int ret; 832 833 error_setg(&kvm_nv_migration_blocker, 834 "Live migration disabled because KVM nested virt is enabled"); 835 if (migrate_add_blocker(&kvm_nv_migration_blocker, errp)) { 836 error_free(kvm_nv_migration_blocker); 837 return; 838 } 839 840 ret = kvm_device_check_attr(s->dev_fd, 841 KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ, 0); 842 if (!ret) { 843 error_setg_errno(errp, errno, 844 "VGICv3 setting maintenance IRQ is not " 845 "supported by this host kernel"); 846 return; 847 } 848 849 ret = kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ, 0, 850 &s->maint_irq, true, errp); 851 if (ret) { 852 error_setg_errno(errp, errno, "Failed to set VGIC maintenance IRQ"); 853 return; 854 } 855 } 856 857 multiple_redist_region_allowed = 858 kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ADDR, 859 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION); 860 861 if (!multiple_redist_region_allowed && s->nb_redist_regions > 1) { 862 error_setg(errp, "Multiple VGICv3 redistributor regions are not " 863 "supported by this host kernel"); 864 error_append_hint(errp, "A maximum of %d VCPUs can be used", 865 s->redist_region_count[0]); 866 return; 867 } 868 869 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 870 0, &s->num_irq, true, &error_abort); 871 872 /* Tell the kernel to complete VGIC initialization now */ 873 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, 874 KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort); 875 876 kvm_arm_register_device(&s->iomem_dist, -1, KVM_DEV_ARM_VGIC_GRP_ADDR, 877 KVM_VGIC_V3_ADDR_TYPE_DIST, s->dev_fd, 0); 878 879 if (!multiple_redist_region_allowed) { 880 kvm_arm_register_device(&s->redist_regions[0].iomem, -1, 881 KVM_DEV_ARM_VGIC_GRP_ADDR, 882 KVM_VGIC_V3_ADDR_TYPE_REDIST, s->dev_fd, 0); 883 } else { 884 /* we register regions in reverse order as "devices" are inserted at 885 * the head of a QSLIST and the list is then popped from the head 886 * onwards by kvm_arm_machine_init_done() 887 */ 888 for (i = s->nb_redist_regions - 1; i >= 0; i--) { 889 /* Address mask made of the rdist region index and count */ 890 uint64_t addr_ormask = 891 i | ((uint64_t)s->redist_region_count[i] << 52); 892 893 kvm_arm_register_device(&s->redist_regions[i].iomem, -1, 894 KVM_DEV_ARM_VGIC_GRP_ADDR, 895 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION, 896 s->dev_fd, addr_ormask); 897 } 898 } 899 900 if (kvm_has_gsi_routing()) { 901 /* set up irq routing */ 902 for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) { 903 kvm_irqchip_add_irq_route(kvm_state, i, 0, i); 904 } 905 906 kvm_gsi_routing_allowed = true; 907 908 kvm_irqchip_commit_routes(kvm_state); 909 } 910 911 if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS, 912 GICD_CTLR)) { 913 error_setg(&s->migration_blocker, "This operating system kernel does " 914 "not support vGICv3 migration"); 915 if (migrate_add_blocker(&s->migration_blocker, errp) < 0) { 916 return; 917 } 918 } 919 if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, 920 KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES)) { 921 qemu_add_vm_change_state_handler(vm_change_state_handler, s); 922 } 923 } 924 925 static void kvm_arm_gicv3_class_init(ObjectClass *klass, const void *data) 926 { 927 DeviceClass *dc = DEVICE_CLASS(klass); 928 ResettableClass *rc = RESETTABLE_CLASS(klass); 929 ARMGICv3CommonClass *agcc = ARM_GICV3_COMMON_CLASS(klass); 930 KVMARMGICv3Class *kgc = KVM_ARM_GICV3_CLASS(klass); 931 932 agcc->pre_save = kvm_arm_gicv3_get; 933 agcc->post_load = kvm_arm_gicv3_put; 934 device_class_set_parent_realize(dc, kvm_arm_gicv3_realize, 935 &kgc->parent_realize); 936 resettable_class_set_parent_phases(rc, NULL, kvm_arm_gicv3_reset_hold, NULL, 937 &kgc->parent_phases); 938 } 939 940 static const TypeInfo kvm_arm_gicv3_info = { 941 .name = TYPE_KVM_ARM_GICV3, 942 .parent = TYPE_ARM_GICV3_COMMON, 943 .instance_size = sizeof(GICv3State), 944 .class_init = kvm_arm_gicv3_class_init, 945 .class_size = sizeof(KVMARMGICv3Class), 946 }; 947 948 static void kvm_arm_gicv3_register_types(void) 949 { 950 type_register_static(&kvm_arm_gicv3_info); 951 } 952 953 type_init(kvm_arm_gicv3_register_types) 954