1 /* 2 * ARM Generic Interrupt Controller using KVM in-kernel support 3 * 4 * Copyright (c) 2015 Samsung Electronics Co., Ltd. 5 * Written by Pavel Fedin 6 * Based on vGICv2 code by Peter Maydell 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation, either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "hw/intc/arm_gicv3_common.h" 25 #include "hw/sysbus.h" 26 #include "qemu/error-report.h" 27 #include "qemu/module.h" 28 #include "sysemu/kvm.h" 29 #include "sysemu/sysemu.h" 30 #include "kvm_arm.h" 31 #include "gicv3_internal.h" 32 #include "vgic_common.h" 33 #include "migration/blocker.h" 34 35 #ifdef DEBUG_GICV3_KVM 36 #define DPRINTF(fmt, ...) \ 37 do { fprintf(stderr, "kvm_gicv3: " fmt, ## __VA_ARGS__); } while (0) 38 #else 39 #define DPRINTF(fmt, ...) \ 40 do { } while (0) 41 #endif 42 43 #define TYPE_KVM_ARM_GICV3 "kvm-arm-gicv3" 44 #define KVM_ARM_GICV3(obj) \ 45 OBJECT_CHECK(GICv3State, (obj), TYPE_KVM_ARM_GICV3) 46 #define KVM_ARM_GICV3_CLASS(klass) \ 47 OBJECT_CLASS_CHECK(KVMARMGICv3Class, (klass), TYPE_KVM_ARM_GICV3) 48 #define KVM_ARM_GICV3_GET_CLASS(obj) \ 49 OBJECT_GET_CLASS(KVMARMGICv3Class, (obj), TYPE_KVM_ARM_GICV3) 50 51 #define KVM_DEV_ARM_VGIC_SYSREG(op0, op1, crn, crm, op2) \ 52 (ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \ 53 ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \ 54 ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \ 55 ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \ 56 ARM64_SYS_REG_SHIFT_MASK(op2, OP2)) 57 58 #define ICC_PMR_EL1 \ 59 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 4, 6, 0) 60 #define ICC_BPR0_EL1 \ 61 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 8, 3) 62 #define ICC_AP0R_EL1(n) \ 63 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 8, 4 | n) 64 #define ICC_AP1R_EL1(n) \ 65 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 9, n) 66 #define ICC_BPR1_EL1 \ 67 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 3) 68 #define ICC_CTLR_EL1 \ 69 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 4) 70 #define ICC_SRE_EL1 \ 71 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 5) 72 #define ICC_IGRPEN0_EL1 \ 73 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 6) 74 #define ICC_IGRPEN1_EL1 \ 75 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 7) 76 77 typedef struct KVMARMGICv3Class { 78 ARMGICv3CommonClass parent_class; 79 DeviceRealize parent_realize; 80 void (*parent_reset)(DeviceState *dev); 81 } KVMARMGICv3Class; 82 83 static void kvm_arm_gicv3_set_irq(void *opaque, int irq, int level) 84 { 85 GICv3State *s = (GICv3State *)opaque; 86 87 kvm_arm_gic_set_irq(s->num_irq, irq, level); 88 } 89 90 #define KVM_VGIC_ATTR(reg, typer) \ 91 ((typer & KVM_DEV_ARM_VGIC_V3_MPIDR_MASK) | (reg)) 92 93 static inline void kvm_gicd_access(GICv3State *s, int offset, 94 uint32_t *val, bool write) 95 { 96 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS, 97 KVM_VGIC_ATTR(offset, 0), 98 val, write, &error_abort); 99 } 100 101 static inline void kvm_gicr_access(GICv3State *s, int offset, int cpu, 102 uint32_t *val, bool write) 103 { 104 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS, 105 KVM_VGIC_ATTR(offset, s->cpu[cpu].gicr_typer), 106 val, write, &error_abort); 107 } 108 109 static inline void kvm_gicc_access(GICv3State *s, uint64_t reg, int cpu, 110 uint64_t *val, bool write) 111 { 112 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, 113 KVM_VGIC_ATTR(reg, s->cpu[cpu].gicr_typer), 114 val, write, &error_abort); 115 } 116 117 static inline void kvm_gic_line_level_access(GICv3State *s, int irq, int cpu, 118 uint32_t *val, bool write) 119 { 120 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO, 121 KVM_VGIC_ATTR(irq, s->cpu[cpu].gicr_typer) | 122 (VGIC_LEVEL_INFO_LINE_LEVEL << 123 KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT), 124 val, write, &error_abort); 125 } 126 127 /* Loop through each distributor IRQ related register; since bits 128 * corresponding to SPIs and PPIs are RAZ/WI when affinity routing 129 * is enabled, we skip those. 130 */ 131 #define for_each_dist_irq_reg(_irq, _max, _field_width) \ 132 for (_irq = GIC_INTERNAL; _irq < _max; _irq += (32 / _field_width)) 133 134 static void kvm_dist_get_priority(GICv3State *s, uint32_t offset, uint8_t *bmp) 135 { 136 uint32_t reg, *field; 137 int irq; 138 139 /* For the KVM GICv3, affinity routing is always enabled, and the first 8 140 * GICD_IPRIORITYR<n> registers are always RAZ/WI. The corresponding 141 * functionality is replaced by GICR_IPRIORITYR<n>. It doesn't need to 142 * sync them. So it needs to skip the field of GIC_INTERNAL irqs in bmp and 143 * offset. 144 */ 145 field = (uint32_t *)(bmp + GIC_INTERNAL); 146 offset += (GIC_INTERNAL * 8) / 8; 147 for_each_dist_irq_reg(irq, s->num_irq, 8) { 148 kvm_gicd_access(s, offset, ®, false); 149 *field = reg; 150 offset += 4; 151 field++; 152 } 153 } 154 155 static void kvm_dist_put_priority(GICv3State *s, uint32_t offset, uint8_t *bmp) 156 { 157 uint32_t reg, *field; 158 int irq; 159 160 /* For the KVM GICv3, affinity routing is always enabled, and the first 8 161 * GICD_IPRIORITYR<n> registers are always RAZ/WI. The corresponding 162 * functionality is replaced by GICR_IPRIORITYR<n>. It doesn't need to 163 * sync them. So it needs to skip the field of GIC_INTERNAL irqs in bmp and 164 * offset. 165 */ 166 field = (uint32_t *)(bmp + GIC_INTERNAL); 167 offset += (GIC_INTERNAL * 8) / 8; 168 for_each_dist_irq_reg(irq, s->num_irq, 8) { 169 reg = *field; 170 kvm_gicd_access(s, offset, ®, true); 171 offset += 4; 172 field++; 173 } 174 } 175 176 static void kvm_dist_get_edge_trigger(GICv3State *s, uint32_t offset, 177 uint32_t *bmp) 178 { 179 uint32_t reg; 180 int irq; 181 182 /* For the KVM GICv3, affinity routing is always enabled, and the first 2 183 * GICD_ICFGR<n> registers are always RAZ/WI. The corresponding 184 * functionality is replaced by GICR_ICFGR<n>. It doesn't need to sync 185 * them. So it should increase the offset to skip GIC_INTERNAL irqs. 186 * This matches the for_each_dist_irq_reg() macro which also skips the 187 * first GIC_INTERNAL irqs. 188 */ 189 offset += (GIC_INTERNAL * 2) / 8; 190 for_each_dist_irq_reg(irq, s->num_irq, 2) { 191 kvm_gicd_access(s, offset, ®, false); 192 reg = half_unshuffle32(reg >> 1); 193 if (irq % 32 != 0) { 194 reg = (reg << 16); 195 } 196 *gic_bmp_ptr32(bmp, irq) |= reg; 197 offset += 4; 198 } 199 } 200 201 static void kvm_dist_put_edge_trigger(GICv3State *s, uint32_t offset, 202 uint32_t *bmp) 203 { 204 uint32_t reg; 205 int irq; 206 207 /* For the KVM GICv3, affinity routing is always enabled, and the first 2 208 * GICD_ICFGR<n> registers are always RAZ/WI. The corresponding 209 * functionality is replaced by GICR_ICFGR<n>. It doesn't need to sync 210 * them. So it should increase the offset to skip GIC_INTERNAL irqs. 211 * This matches the for_each_dist_irq_reg() macro which also skips the 212 * first GIC_INTERNAL irqs. 213 */ 214 offset += (GIC_INTERNAL * 2) / 8; 215 for_each_dist_irq_reg(irq, s->num_irq, 2) { 216 reg = *gic_bmp_ptr32(bmp, irq); 217 if (irq % 32 != 0) { 218 reg = (reg & 0xffff0000) >> 16; 219 } else { 220 reg = reg & 0xffff; 221 } 222 reg = half_shuffle32(reg) << 1; 223 kvm_gicd_access(s, offset, ®, true); 224 offset += 4; 225 } 226 } 227 228 static void kvm_gic_get_line_level_bmp(GICv3State *s, uint32_t *bmp) 229 { 230 uint32_t reg; 231 int irq; 232 233 for_each_dist_irq_reg(irq, s->num_irq, 1) { 234 kvm_gic_line_level_access(s, irq, 0, ®, false); 235 *gic_bmp_ptr32(bmp, irq) = reg; 236 } 237 } 238 239 static void kvm_gic_put_line_level_bmp(GICv3State *s, uint32_t *bmp) 240 { 241 uint32_t reg; 242 int irq; 243 244 for_each_dist_irq_reg(irq, s->num_irq, 1) { 245 reg = *gic_bmp_ptr32(bmp, irq); 246 kvm_gic_line_level_access(s, irq, 0, ®, true); 247 } 248 } 249 250 /* Read a bitmap register group from the kernel VGIC. */ 251 static void kvm_dist_getbmp(GICv3State *s, uint32_t offset, uint32_t *bmp) 252 { 253 uint32_t reg; 254 int irq; 255 256 /* For the KVM GICv3, affinity routing is always enabled, and the 257 * GICD_IGROUPR0/GICD_IGRPMODR0/GICD_ISENABLER0/GICD_ISPENDR0/ 258 * GICD_ISACTIVER0 registers are always RAZ/WI. The corresponding 259 * functionality is replaced by the GICR registers. It doesn't need to sync 260 * them. So it should increase the offset to skip GIC_INTERNAL irqs. 261 * This matches the for_each_dist_irq_reg() macro which also skips the 262 * first GIC_INTERNAL irqs. 263 */ 264 offset += (GIC_INTERNAL * 1) / 8; 265 for_each_dist_irq_reg(irq, s->num_irq, 1) { 266 kvm_gicd_access(s, offset, ®, false); 267 *gic_bmp_ptr32(bmp, irq) = reg; 268 offset += 4; 269 } 270 } 271 272 static void kvm_dist_putbmp(GICv3State *s, uint32_t offset, 273 uint32_t clroffset, uint32_t *bmp) 274 { 275 uint32_t reg; 276 int irq; 277 278 /* For the KVM GICv3, affinity routing is always enabled, and the 279 * GICD_IGROUPR0/GICD_IGRPMODR0/GICD_ISENABLER0/GICD_ISPENDR0/ 280 * GICD_ISACTIVER0 registers are always RAZ/WI. The corresponding 281 * functionality is replaced by the GICR registers. It doesn't need to sync 282 * them. So it should increase the offset and clroffset to skip GIC_INTERNAL 283 * irqs. This matches the for_each_dist_irq_reg() macro which also skips the 284 * first GIC_INTERNAL irqs. 285 */ 286 offset += (GIC_INTERNAL * 1) / 8; 287 if (clroffset != 0) { 288 clroffset += (GIC_INTERNAL * 1) / 8; 289 } 290 291 for_each_dist_irq_reg(irq, s->num_irq, 1) { 292 /* If this bitmap is a set/clear register pair, first write to the 293 * clear-reg to clear all bits before using the set-reg to write 294 * the 1 bits. 295 */ 296 if (clroffset != 0) { 297 reg = 0; 298 kvm_gicd_access(s, clroffset, ®, true); 299 clroffset += 4; 300 } 301 reg = *gic_bmp_ptr32(bmp, irq); 302 kvm_gicd_access(s, offset, ®, true); 303 offset += 4; 304 } 305 } 306 307 static void kvm_arm_gicv3_check(GICv3State *s) 308 { 309 uint32_t reg; 310 uint32_t num_irq; 311 312 /* Sanity checking s->num_irq */ 313 kvm_gicd_access(s, GICD_TYPER, ®, false); 314 num_irq = ((reg & 0x1f) + 1) * 32; 315 316 if (num_irq < s->num_irq) { 317 error_report("Model requests %u IRQs, but kernel supports max %u", 318 s->num_irq, num_irq); 319 abort(); 320 } 321 } 322 323 static void kvm_arm_gicv3_put(GICv3State *s) 324 { 325 uint32_t regl, regh, reg; 326 uint64_t reg64, redist_typer; 327 int ncpu, i; 328 329 kvm_arm_gicv3_check(s); 330 331 kvm_gicr_access(s, GICR_TYPER, 0, ®l, false); 332 kvm_gicr_access(s, GICR_TYPER + 4, 0, ®h, false); 333 redist_typer = ((uint64_t)regh << 32) | regl; 334 335 reg = s->gicd_ctlr; 336 kvm_gicd_access(s, GICD_CTLR, ®, true); 337 338 if (redist_typer & GICR_TYPER_PLPIS) { 339 /* Set base addresses before LPIs are enabled by GICR_CTLR write */ 340 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 341 GICv3CPUState *c = &s->cpu[ncpu]; 342 343 reg64 = c->gicr_propbaser; 344 regl = (uint32_t)reg64; 345 kvm_gicr_access(s, GICR_PROPBASER, ncpu, ®l, true); 346 regh = (uint32_t)(reg64 >> 32); 347 kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, ®h, true); 348 349 reg64 = c->gicr_pendbaser; 350 if (!(c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS)) { 351 /* Setting PTZ is advised if LPIs are disabled, to reduce 352 * GIC initialization time. 353 */ 354 reg64 |= GICR_PENDBASER_PTZ; 355 } 356 regl = (uint32_t)reg64; 357 kvm_gicr_access(s, GICR_PENDBASER, ncpu, ®l, true); 358 regh = (uint32_t)(reg64 >> 32); 359 kvm_gicr_access(s, GICR_PENDBASER + 4, ncpu, ®h, true); 360 } 361 } 362 363 /* Redistributor state (one per CPU) */ 364 365 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 366 GICv3CPUState *c = &s->cpu[ncpu]; 367 368 reg = c->gicr_ctlr; 369 kvm_gicr_access(s, GICR_CTLR, ncpu, ®, true); 370 371 reg = c->gicr_statusr[GICV3_NS]; 372 kvm_gicr_access(s, GICR_STATUSR, ncpu, ®, true); 373 374 reg = c->gicr_waker; 375 kvm_gicr_access(s, GICR_WAKER, ncpu, ®, true); 376 377 reg = c->gicr_igroupr0; 378 kvm_gicr_access(s, GICR_IGROUPR0, ncpu, ®, true); 379 380 reg = ~0; 381 kvm_gicr_access(s, GICR_ICENABLER0, ncpu, ®, true); 382 reg = c->gicr_ienabler0; 383 kvm_gicr_access(s, GICR_ISENABLER0, ncpu, ®, true); 384 385 /* Restore config before pending so we treat level/edge correctly */ 386 reg = half_shuffle32(c->edge_trigger >> 16) << 1; 387 kvm_gicr_access(s, GICR_ICFGR1, ncpu, ®, true); 388 389 reg = c->level; 390 kvm_gic_line_level_access(s, 0, ncpu, ®, true); 391 392 reg = ~0; 393 kvm_gicr_access(s, GICR_ICPENDR0, ncpu, ®, true); 394 reg = c->gicr_ipendr0; 395 kvm_gicr_access(s, GICR_ISPENDR0, ncpu, ®, true); 396 397 reg = ~0; 398 kvm_gicr_access(s, GICR_ICACTIVER0, ncpu, ®, true); 399 reg = c->gicr_iactiver0; 400 kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, ®, true); 401 402 for (i = 0; i < GIC_INTERNAL; i += 4) { 403 reg = c->gicr_ipriorityr[i] | 404 (c->gicr_ipriorityr[i + 1] << 8) | 405 (c->gicr_ipriorityr[i + 2] << 16) | 406 (c->gicr_ipriorityr[i + 3] << 24); 407 kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, ®, true); 408 } 409 } 410 411 /* Distributor state (shared between all CPUs */ 412 reg = s->gicd_statusr[GICV3_NS]; 413 kvm_gicd_access(s, GICD_STATUSR, ®, true); 414 415 /* s->enable bitmap -> GICD_ISENABLERn */ 416 kvm_dist_putbmp(s, GICD_ISENABLER, GICD_ICENABLER, s->enabled); 417 418 /* s->group bitmap -> GICD_IGROUPRn */ 419 kvm_dist_putbmp(s, GICD_IGROUPR, 0, s->group); 420 421 /* Restore targets before pending to ensure the pending state is set on 422 * the appropriate CPU interfaces in the kernel 423 */ 424 425 /* s->gicd_irouter[irq] -> GICD_IROUTERn 426 * We can't use kvm_dist_put() here because the registers are 64-bit 427 */ 428 for (i = GIC_INTERNAL; i < s->num_irq; i++) { 429 uint32_t offset; 430 431 offset = GICD_IROUTER + (sizeof(uint32_t) * i); 432 reg = (uint32_t)s->gicd_irouter[i]; 433 kvm_gicd_access(s, offset, ®, true); 434 435 offset = GICD_IROUTER + (sizeof(uint32_t) * i) + 4; 436 reg = (uint32_t)(s->gicd_irouter[i] >> 32); 437 kvm_gicd_access(s, offset, ®, true); 438 } 439 440 /* s->trigger bitmap -> GICD_ICFGRn 441 * (restore configuration registers before pending IRQs so we treat 442 * level/edge correctly) 443 */ 444 kvm_dist_put_edge_trigger(s, GICD_ICFGR, s->edge_trigger); 445 446 /* s->level bitmap -> line_level */ 447 kvm_gic_put_line_level_bmp(s, s->level); 448 449 /* s->pending bitmap -> GICD_ISPENDRn */ 450 kvm_dist_putbmp(s, GICD_ISPENDR, GICD_ICPENDR, s->pending); 451 452 /* s->active bitmap -> GICD_ISACTIVERn */ 453 kvm_dist_putbmp(s, GICD_ISACTIVER, GICD_ICACTIVER, s->active); 454 455 /* s->gicd_ipriority[] -> GICD_IPRIORITYRn */ 456 kvm_dist_put_priority(s, GICD_IPRIORITYR, s->gicd_ipriority); 457 458 /* CPU Interface state (one per CPU) */ 459 460 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 461 GICv3CPUState *c = &s->cpu[ncpu]; 462 int num_pri_bits; 463 464 kvm_gicc_access(s, ICC_SRE_EL1, ncpu, &c->icc_sre_el1, true); 465 kvm_gicc_access(s, ICC_CTLR_EL1, ncpu, 466 &c->icc_ctlr_el1[GICV3_NS], true); 467 kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu, 468 &c->icc_igrpen[GICV3_G0], true); 469 kvm_gicc_access(s, ICC_IGRPEN1_EL1, ncpu, 470 &c->icc_igrpen[GICV3_G1NS], true); 471 kvm_gicc_access(s, ICC_PMR_EL1, ncpu, &c->icc_pmr_el1, true); 472 kvm_gicc_access(s, ICC_BPR0_EL1, ncpu, &c->icc_bpr[GICV3_G0], true); 473 kvm_gicc_access(s, ICC_BPR1_EL1, ncpu, &c->icc_bpr[GICV3_G1NS], true); 474 475 num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] & 476 ICC_CTLR_EL1_PRIBITS_MASK) >> 477 ICC_CTLR_EL1_PRIBITS_SHIFT) + 1; 478 479 switch (num_pri_bits) { 480 case 7: 481 reg64 = c->icc_apr[GICV3_G0][3]; 482 kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, ®64, true); 483 reg64 = c->icc_apr[GICV3_G0][2]; 484 kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, ®64, true); 485 case 6: 486 reg64 = c->icc_apr[GICV3_G0][1]; 487 kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, ®64, true); 488 default: 489 reg64 = c->icc_apr[GICV3_G0][0]; 490 kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, ®64, true); 491 } 492 493 switch (num_pri_bits) { 494 case 7: 495 reg64 = c->icc_apr[GICV3_G1NS][3]; 496 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, ®64, true); 497 reg64 = c->icc_apr[GICV3_G1NS][2]; 498 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, ®64, true); 499 case 6: 500 reg64 = c->icc_apr[GICV3_G1NS][1]; 501 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, ®64, true); 502 default: 503 reg64 = c->icc_apr[GICV3_G1NS][0]; 504 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, ®64, true); 505 } 506 } 507 } 508 509 static void kvm_arm_gicv3_get(GICv3State *s) 510 { 511 uint32_t regl, regh, reg; 512 uint64_t reg64, redist_typer; 513 int ncpu, i; 514 515 kvm_arm_gicv3_check(s); 516 517 kvm_gicr_access(s, GICR_TYPER, 0, ®l, false); 518 kvm_gicr_access(s, GICR_TYPER + 4, 0, ®h, false); 519 redist_typer = ((uint64_t)regh << 32) | regl; 520 521 kvm_gicd_access(s, GICD_CTLR, ®, false); 522 s->gicd_ctlr = reg; 523 524 /* Redistributor state (one per CPU) */ 525 526 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 527 GICv3CPUState *c = &s->cpu[ncpu]; 528 529 kvm_gicr_access(s, GICR_CTLR, ncpu, ®, false); 530 c->gicr_ctlr = reg; 531 532 kvm_gicr_access(s, GICR_STATUSR, ncpu, ®, false); 533 c->gicr_statusr[GICV3_NS] = reg; 534 535 kvm_gicr_access(s, GICR_WAKER, ncpu, ®, false); 536 c->gicr_waker = reg; 537 538 kvm_gicr_access(s, GICR_IGROUPR0, ncpu, ®, false); 539 c->gicr_igroupr0 = reg; 540 kvm_gicr_access(s, GICR_ISENABLER0, ncpu, ®, false); 541 c->gicr_ienabler0 = reg; 542 kvm_gicr_access(s, GICR_ICFGR1, ncpu, ®, false); 543 c->edge_trigger = half_unshuffle32(reg >> 1) << 16; 544 kvm_gic_line_level_access(s, 0, ncpu, ®, false); 545 c->level = reg; 546 kvm_gicr_access(s, GICR_ISPENDR0, ncpu, ®, false); 547 c->gicr_ipendr0 = reg; 548 kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, ®, false); 549 c->gicr_iactiver0 = reg; 550 551 for (i = 0; i < GIC_INTERNAL; i += 4) { 552 kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, ®, false); 553 c->gicr_ipriorityr[i] = extract32(reg, 0, 8); 554 c->gicr_ipriorityr[i + 1] = extract32(reg, 8, 8); 555 c->gicr_ipriorityr[i + 2] = extract32(reg, 16, 8); 556 c->gicr_ipriorityr[i + 3] = extract32(reg, 24, 8); 557 } 558 } 559 560 if (redist_typer & GICR_TYPER_PLPIS) { 561 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 562 GICv3CPUState *c = &s->cpu[ncpu]; 563 564 kvm_gicr_access(s, GICR_PROPBASER, ncpu, ®l, false); 565 kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, ®h, false); 566 c->gicr_propbaser = ((uint64_t)regh << 32) | regl; 567 568 kvm_gicr_access(s, GICR_PENDBASER, ncpu, ®l, false); 569 kvm_gicr_access(s, GICR_PENDBASER + 4, ncpu, ®h, false); 570 c->gicr_pendbaser = ((uint64_t)regh << 32) | regl; 571 } 572 } 573 574 /* Distributor state (shared between all CPUs */ 575 576 kvm_gicd_access(s, GICD_STATUSR, ®, false); 577 s->gicd_statusr[GICV3_NS] = reg; 578 579 /* GICD_IGROUPRn -> s->group bitmap */ 580 kvm_dist_getbmp(s, GICD_IGROUPR, s->group); 581 582 /* GICD_ISENABLERn -> s->enabled bitmap */ 583 kvm_dist_getbmp(s, GICD_ISENABLER, s->enabled); 584 585 /* Line level of irq */ 586 kvm_gic_get_line_level_bmp(s, s->level); 587 /* GICD_ISPENDRn -> s->pending bitmap */ 588 kvm_dist_getbmp(s, GICD_ISPENDR, s->pending); 589 590 /* GICD_ISACTIVERn -> s->active bitmap */ 591 kvm_dist_getbmp(s, GICD_ISACTIVER, s->active); 592 593 /* GICD_ICFGRn -> s->trigger bitmap */ 594 kvm_dist_get_edge_trigger(s, GICD_ICFGR, s->edge_trigger); 595 596 /* GICD_IPRIORITYRn -> s->gicd_ipriority[] */ 597 kvm_dist_get_priority(s, GICD_IPRIORITYR, s->gicd_ipriority); 598 599 /* GICD_IROUTERn -> s->gicd_irouter[irq] */ 600 for (i = GIC_INTERNAL; i < s->num_irq; i++) { 601 uint32_t offset; 602 603 offset = GICD_IROUTER + (sizeof(uint32_t) * i); 604 kvm_gicd_access(s, offset, ®l, false); 605 offset = GICD_IROUTER + (sizeof(uint32_t) * i) + 4; 606 kvm_gicd_access(s, offset, ®h, false); 607 s->gicd_irouter[i] = ((uint64_t)regh << 32) | regl; 608 } 609 610 /***************************************************************** 611 * CPU Interface(s) State 612 */ 613 614 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 615 GICv3CPUState *c = &s->cpu[ncpu]; 616 int num_pri_bits; 617 618 kvm_gicc_access(s, ICC_SRE_EL1, ncpu, &c->icc_sre_el1, false); 619 kvm_gicc_access(s, ICC_CTLR_EL1, ncpu, 620 &c->icc_ctlr_el1[GICV3_NS], false); 621 kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu, 622 &c->icc_igrpen[GICV3_G0], false); 623 kvm_gicc_access(s, ICC_IGRPEN1_EL1, ncpu, 624 &c->icc_igrpen[GICV3_G1NS], false); 625 kvm_gicc_access(s, ICC_PMR_EL1, ncpu, &c->icc_pmr_el1, false); 626 kvm_gicc_access(s, ICC_BPR0_EL1, ncpu, &c->icc_bpr[GICV3_G0], false); 627 kvm_gicc_access(s, ICC_BPR1_EL1, ncpu, &c->icc_bpr[GICV3_G1NS], false); 628 num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] & 629 ICC_CTLR_EL1_PRIBITS_MASK) >> 630 ICC_CTLR_EL1_PRIBITS_SHIFT) + 1; 631 632 switch (num_pri_bits) { 633 case 7: 634 kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, ®64, false); 635 c->icc_apr[GICV3_G0][3] = reg64; 636 kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, ®64, false); 637 c->icc_apr[GICV3_G0][2] = reg64; 638 case 6: 639 kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, ®64, false); 640 c->icc_apr[GICV3_G0][1] = reg64; 641 default: 642 kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, ®64, false); 643 c->icc_apr[GICV3_G0][0] = reg64; 644 } 645 646 switch (num_pri_bits) { 647 case 7: 648 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, ®64, false); 649 c->icc_apr[GICV3_G1NS][3] = reg64; 650 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, ®64, false); 651 c->icc_apr[GICV3_G1NS][2] = reg64; 652 case 6: 653 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, ®64, false); 654 c->icc_apr[GICV3_G1NS][1] = reg64; 655 default: 656 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, ®64, false); 657 c->icc_apr[GICV3_G1NS][0] = reg64; 658 } 659 } 660 } 661 662 static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) 663 { 664 ARMCPU *cpu; 665 GICv3State *s; 666 GICv3CPUState *c; 667 668 c = (GICv3CPUState *)env->gicv3state; 669 s = c->gic; 670 cpu = ARM_CPU(c->cpu); 671 672 c->icc_pmr_el1 = 0; 673 c->icc_bpr[GICV3_G0] = GIC_MIN_BPR; 674 c->icc_bpr[GICV3_G1] = GIC_MIN_BPR; 675 c->icc_bpr[GICV3_G1NS] = GIC_MIN_BPR; 676 677 c->icc_sre_el1 = 0x7; 678 memset(c->icc_apr, 0, sizeof(c->icc_apr)); 679 memset(c->icc_igrpen, 0, sizeof(c->icc_igrpen)); 680 681 if (s->migration_blocker) { 682 return; 683 } 684 685 /* Initialize to actual HW supported configuration */ 686 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, 687 KVM_VGIC_ATTR(ICC_CTLR_EL1, cpu->mp_affinity), 688 &c->icc_ctlr_el1[GICV3_NS], false, &error_abort); 689 690 c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS]; 691 } 692 693 static void kvm_arm_gicv3_reset(DeviceState *dev) 694 { 695 GICv3State *s = ARM_GICV3_COMMON(dev); 696 KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s); 697 698 DPRINTF("Reset\n"); 699 700 kgc->parent_reset(dev); 701 702 if (s->migration_blocker) { 703 DPRINTF("Cannot put kernel gic state, no kernel interface\n"); 704 return; 705 } 706 707 kvm_arm_gicv3_put(s); 708 } 709 710 /* 711 * CPU interface registers of GIC needs to be reset on CPU reset. 712 * For the calling arm_gicv3_icc_reset() on CPU reset, we register 713 * below ARMCPRegInfo. As we reset the whole cpu interface under single 714 * register reset, we define only one register of CPU interface instead 715 * of defining all the registers. 716 */ 717 static const ARMCPRegInfo gicv3_cpuif_reginfo[] = { 718 { .name = "ICC_CTLR_EL1", .state = ARM_CP_STATE_BOTH, 719 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 4, 720 /* 721 * If ARM_CP_NOP is used, resetfn is not called, 722 * So ARM_CP_NO_RAW is appropriate type. 723 */ 724 .type = ARM_CP_NO_RAW, 725 .access = PL1_RW, 726 .readfn = arm_cp_read_zero, 727 .writefn = arm_cp_write_ignore, 728 /* 729 * We hang the whole cpu interface reset routine off here 730 * rather than parcelling it out into one little function 731 * per register 732 */ 733 .resetfn = arm_gicv3_icc_reset, 734 }, 735 REGINFO_SENTINEL 736 }; 737 738 /** 739 * vm_change_state_handler - VM change state callback aiming at flushing 740 * RDIST pending tables into guest RAM 741 * 742 * The tables get flushed to guest RAM whenever the VM gets stopped. 743 */ 744 static void vm_change_state_handler(void *opaque, int running, 745 RunState state) 746 { 747 GICv3State *s = (GICv3State *)opaque; 748 Error *err = NULL; 749 int ret; 750 751 if (running) { 752 return; 753 } 754 755 ret = kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, 756 KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES, 757 NULL, true, &err); 758 if (err) { 759 error_report_err(err); 760 } 761 if (ret < 0 && ret != -EFAULT) { 762 abort(); 763 } 764 } 765 766 767 static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) 768 { 769 GICv3State *s = KVM_ARM_GICV3(dev); 770 KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s); 771 bool multiple_redist_region_allowed; 772 Error *local_err = NULL; 773 int i; 774 775 DPRINTF("kvm_arm_gicv3_realize\n"); 776 777 kgc->parent_realize(dev, &local_err); 778 if (local_err) { 779 error_propagate(errp, local_err); 780 return; 781 } 782 783 if (s->security_extn) { 784 error_setg(errp, "the in-kernel VGICv3 does not implement the " 785 "security extensions"); 786 return; 787 } 788 789 gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL, &local_err); 790 if (local_err) { 791 error_propagate(errp, local_err); 792 return; 793 } 794 795 for (i = 0; i < s->num_cpu; i++) { 796 ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i)); 797 798 define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); 799 } 800 801 /* Try to create the device via the device control API */ 802 s->dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V3, false); 803 if (s->dev_fd < 0) { 804 error_setg_errno(errp, -s->dev_fd, "error creating in-kernel VGIC"); 805 return; 806 } 807 808 multiple_redist_region_allowed = 809 kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ADDR, 810 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION); 811 812 if (!multiple_redist_region_allowed && s->nb_redist_regions > 1) { 813 error_setg(errp, "Multiple VGICv3 redistributor regions are not " 814 "supported by this host kernel"); 815 error_append_hint(errp, "A maximum of %d VCPUs can be used", 816 s->redist_region_count[0]); 817 return; 818 } 819 820 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 821 0, &s->num_irq, true, &error_abort); 822 823 /* Tell the kernel to complete VGIC initialization now */ 824 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, 825 KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort); 826 827 kvm_arm_register_device(&s->iomem_dist, -1, KVM_DEV_ARM_VGIC_GRP_ADDR, 828 KVM_VGIC_V3_ADDR_TYPE_DIST, s->dev_fd, 0); 829 830 if (!multiple_redist_region_allowed) { 831 kvm_arm_register_device(&s->iomem_redist[0], -1, 832 KVM_DEV_ARM_VGIC_GRP_ADDR, 833 KVM_VGIC_V3_ADDR_TYPE_REDIST, s->dev_fd, 0); 834 } else { 835 /* we register regions in reverse order as "devices" are inserted at 836 * the head of a QSLIST and the list is then popped from the head 837 * onwards by kvm_arm_machine_init_done() 838 */ 839 for (i = s->nb_redist_regions - 1; i >= 0; i--) { 840 /* Address mask made of the rdist region index and count */ 841 uint64_t addr_ormask = 842 i | ((uint64_t)s->redist_region_count[i] << 52); 843 844 kvm_arm_register_device(&s->iomem_redist[i], -1, 845 KVM_DEV_ARM_VGIC_GRP_ADDR, 846 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION, 847 s->dev_fd, addr_ormask); 848 } 849 } 850 851 if (kvm_has_gsi_routing()) { 852 /* set up irq routing */ 853 for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) { 854 kvm_irqchip_add_irq_route(kvm_state, i, 0, i); 855 } 856 857 kvm_gsi_routing_allowed = true; 858 859 kvm_irqchip_commit_routes(kvm_state); 860 } 861 862 if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS, 863 GICD_CTLR)) { 864 error_setg(&s->migration_blocker, "This operating system kernel does " 865 "not support vGICv3 migration"); 866 migrate_add_blocker(s->migration_blocker, &local_err); 867 if (local_err) { 868 error_propagate(errp, local_err); 869 error_free(s->migration_blocker); 870 return; 871 } 872 } 873 if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, 874 KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES)) { 875 qemu_add_vm_change_state_handler(vm_change_state_handler, s); 876 } 877 } 878 879 static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data) 880 { 881 DeviceClass *dc = DEVICE_CLASS(klass); 882 ARMGICv3CommonClass *agcc = ARM_GICV3_COMMON_CLASS(klass); 883 KVMARMGICv3Class *kgc = KVM_ARM_GICV3_CLASS(klass); 884 885 agcc->pre_save = kvm_arm_gicv3_get; 886 agcc->post_load = kvm_arm_gicv3_put; 887 device_class_set_parent_realize(dc, kvm_arm_gicv3_realize, 888 &kgc->parent_realize); 889 device_class_set_parent_reset(dc, kvm_arm_gicv3_reset, &kgc->parent_reset); 890 } 891 892 static const TypeInfo kvm_arm_gicv3_info = { 893 .name = TYPE_KVM_ARM_GICV3, 894 .parent = TYPE_ARM_GICV3_COMMON, 895 .instance_size = sizeof(GICv3State), 896 .class_init = kvm_arm_gicv3_class_init, 897 .class_size = sizeof(KVMARMGICv3Class), 898 }; 899 900 static void kvm_arm_gicv3_register_types(void) 901 { 902 type_register_static(&kvm_arm_gicv3_info); 903 } 904 905 type_init(kvm_arm_gicv3_register_types) 906