1 /* 2 * ARM Generic Interrupt Controller using KVM in-kernel support 3 * 4 * Copyright (c) 2015 Samsung Electronics Co., Ltd. 5 * Written by Pavel Fedin 6 * Based on vGICv2 code by Peter Maydell 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation, either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "hw/intc/arm_gicv3_common.h" 25 #include "hw/sysbus.h" 26 #include "qemu/error-report.h" 27 #include "qemu/module.h" 28 #include "sysemu/kvm.h" 29 #include "sysemu/runstate.h" 30 #include "kvm_arm.h" 31 #include "gicv3_internal.h" 32 #include "vgic_common.h" 33 #include "migration/blocker.h" 34 35 #ifdef DEBUG_GICV3_KVM 36 #define DPRINTF(fmt, ...) \ 37 do { fprintf(stderr, "kvm_gicv3: " fmt, ## __VA_ARGS__); } while (0) 38 #else 39 #define DPRINTF(fmt, ...) \ 40 do { } while (0) 41 #endif 42 43 #define TYPE_KVM_ARM_GICV3 "kvm-arm-gicv3" 44 #define KVM_ARM_GICV3(obj) \ 45 OBJECT_CHECK(GICv3State, (obj), TYPE_KVM_ARM_GICV3) 46 #define KVM_ARM_GICV3_CLASS(klass) \ 47 OBJECT_CLASS_CHECK(KVMARMGICv3Class, (klass), TYPE_KVM_ARM_GICV3) 48 #define KVM_ARM_GICV3_GET_CLASS(obj) \ 49 OBJECT_GET_CLASS(KVMARMGICv3Class, (obj), TYPE_KVM_ARM_GICV3) 50 51 #define KVM_DEV_ARM_VGIC_SYSREG(op0, op1, crn, crm, op2) \ 52 (ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \ 53 ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \ 54 ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \ 55 ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \ 56 ARM64_SYS_REG_SHIFT_MASK(op2, OP2)) 57 58 #define ICC_PMR_EL1 \ 59 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 4, 6, 0) 60 #define ICC_BPR0_EL1 \ 61 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 8, 3) 62 #define ICC_AP0R_EL1(n) \ 63 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 8, 4 | n) 64 #define ICC_AP1R_EL1(n) \ 65 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 9, n) 66 #define ICC_BPR1_EL1 \ 67 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 3) 68 #define ICC_CTLR_EL1 \ 69 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 4) 70 #define ICC_SRE_EL1 \ 71 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 5) 72 #define ICC_IGRPEN0_EL1 \ 73 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 6) 74 #define ICC_IGRPEN1_EL1 \ 75 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 7) 76 77 typedef struct KVMARMGICv3Class { 78 ARMGICv3CommonClass parent_class; 79 DeviceRealize parent_realize; 80 void (*parent_reset)(DeviceState *dev); 81 } KVMARMGICv3Class; 82 83 static void kvm_arm_gicv3_set_irq(void *opaque, int irq, int level) 84 { 85 GICv3State *s = (GICv3State *)opaque; 86 87 kvm_arm_gic_set_irq(s->num_irq, irq, level); 88 } 89 90 #define KVM_VGIC_ATTR(reg, typer) \ 91 ((typer & KVM_DEV_ARM_VGIC_V3_MPIDR_MASK) | (reg)) 92 93 static inline void kvm_gicd_access(GICv3State *s, int offset, 94 uint32_t *val, bool write) 95 { 96 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS, 97 KVM_VGIC_ATTR(offset, 0), 98 val, write, &error_abort); 99 } 100 101 static inline void kvm_gicr_access(GICv3State *s, int offset, int cpu, 102 uint32_t *val, bool write) 103 { 104 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS, 105 KVM_VGIC_ATTR(offset, s->cpu[cpu].gicr_typer), 106 val, write, &error_abort); 107 } 108 109 static inline void kvm_gicc_access(GICv3State *s, uint64_t reg, int cpu, 110 uint64_t *val, bool write) 111 { 112 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, 113 KVM_VGIC_ATTR(reg, s->cpu[cpu].gicr_typer), 114 val, write, &error_abort); 115 } 116 117 static inline void kvm_gic_line_level_access(GICv3State *s, int irq, int cpu, 118 uint32_t *val, bool write) 119 { 120 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO, 121 KVM_VGIC_ATTR(irq, s->cpu[cpu].gicr_typer) | 122 (VGIC_LEVEL_INFO_LINE_LEVEL << 123 KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT), 124 val, write, &error_abort); 125 } 126 127 /* Loop through each distributor IRQ related register; since bits 128 * corresponding to SPIs and PPIs are RAZ/WI when affinity routing 129 * is enabled, we skip those. 130 */ 131 #define for_each_dist_irq_reg(_irq, _max, _field_width) \ 132 for (_irq = GIC_INTERNAL; _irq < _max; _irq += (32 / _field_width)) 133 134 static void kvm_dist_get_priority(GICv3State *s, uint32_t offset, uint8_t *bmp) 135 { 136 uint32_t reg, *field; 137 int irq; 138 139 /* For the KVM GICv3, affinity routing is always enabled, and the first 8 140 * GICD_IPRIORITYR<n> registers are always RAZ/WI. The corresponding 141 * functionality is replaced by GICR_IPRIORITYR<n>. It doesn't need to 142 * sync them. So it needs to skip the field of GIC_INTERNAL irqs in bmp and 143 * offset. 144 */ 145 field = (uint32_t *)(bmp + GIC_INTERNAL); 146 offset += (GIC_INTERNAL * 8) / 8; 147 for_each_dist_irq_reg(irq, s->num_irq, 8) { 148 kvm_gicd_access(s, offset, ®, false); 149 *field = reg; 150 offset += 4; 151 field++; 152 } 153 } 154 155 static void kvm_dist_put_priority(GICv3State *s, uint32_t offset, uint8_t *bmp) 156 { 157 uint32_t reg, *field; 158 int irq; 159 160 /* For the KVM GICv3, affinity routing is always enabled, and the first 8 161 * GICD_IPRIORITYR<n> registers are always RAZ/WI. The corresponding 162 * functionality is replaced by GICR_IPRIORITYR<n>. It doesn't need to 163 * sync them. So it needs to skip the field of GIC_INTERNAL irqs in bmp and 164 * offset. 165 */ 166 field = (uint32_t *)(bmp + GIC_INTERNAL); 167 offset += (GIC_INTERNAL * 8) / 8; 168 for_each_dist_irq_reg(irq, s->num_irq, 8) { 169 reg = *field; 170 kvm_gicd_access(s, offset, ®, true); 171 offset += 4; 172 field++; 173 } 174 } 175 176 static void kvm_dist_get_edge_trigger(GICv3State *s, uint32_t offset, 177 uint32_t *bmp) 178 { 179 uint32_t reg; 180 int irq; 181 182 /* For the KVM GICv3, affinity routing is always enabled, and the first 2 183 * GICD_ICFGR<n> registers are always RAZ/WI. The corresponding 184 * functionality is replaced by GICR_ICFGR<n>. It doesn't need to sync 185 * them. So it should increase the offset to skip GIC_INTERNAL irqs. 186 * This matches the for_each_dist_irq_reg() macro which also skips the 187 * first GIC_INTERNAL irqs. 188 */ 189 offset += (GIC_INTERNAL * 2) / 8; 190 for_each_dist_irq_reg(irq, s->num_irq, 2) { 191 kvm_gicd_access(s, offset, ®, false); 192 reg = half_unshuffle32(reg >> 1); 193 if (irq % 32 != 0) { 194 reg = (reg << 16); 195 } 196 *gic_bmp_ptr32(bmp, irq) |= reg; 197 offset += 4; 198 } 199 } 200 201 static void kvm_dist_put_edge_trigger(GICv3State *s, uint32_t offset, 202 uint32_t *bmp) 203 { 204 uint32_t reg; 205 int irq; 206 207 /* For the KVM GICv3, affinity routing is always enabled, and the first 2 208 * GICD_ICFGR<n> registers are always RAZ/WI. The corresponding 209 * functionality is replaced by GICR_ICFGR<n>. It doesn't need to sync 210 * them. So it should increase the offset to skip GIC_INTERNAL irqs. 211 * This matches the for_each_dist_irq_reg() macro which also skips the 212 * first GIC_INTERNAL irqs. 213 */ 214 offset += (GIC_INTERNAL * 2) / 8; 215 for_each_dist_irq_reg(irq, s->num_irq, 2) { 216 reg = *gic_bmp_ptr32(bmp, irq); 217 if (irq % 32 != 0) { 218 reg = (reg & 0xffff0000) >> 16; 219 } else { 220 reg = reg & 0xffff; 221 } 222 reg = half_shuffle32(reg) << 1; 223 kvm_gicd_access(s, offset, ®, true); 224 offset += 4; 225 } 226 } 227 228 static void kvm_gic_get_line_level_bmp(GICv3State *s, uint32_t *bmp) 229 { 230 uint32_t reg; 231 int irq; 232 233 for_each_dist_irq_reg(irq, s->num_irq, 1) { 234 kvm_gic_line_level_access(s, irq, 0, ®, false); 235 *gic_bmp_ptr32(bmp, irq) = reg; 236 } 237 } 238 239 static void kvm_gic_put_line_level_bmp(GICv3State *s, uint32_t *bmp) 240 { 241 uint32_t reg; 242 int irq; 243 244 for_each_dist_irq_reg(irq, s->num_irq, 1) { 245 reg = *gic_bmp_ptr32(bmp, irq); 246 kvm_gic_line_level_access(s, irq, 0, ®, true); 247 } 248 } 249 250 /* Read a bitmap register group from the kernel VGIC. */ 251 static void kvm_dist_getbmp(GICv3State *s, uint32_t offset, uint32_t *bmp) 252 { 253 uint32_t reg; 254 int irq; 255 256 /* For the KVM GICv3, affinity routing is always enabled, and the 257 * GICD_IGROUPR0/GICD_IGRPMODR0/GICD_ISENABLER0/GICD_ISPENDR0/ 258 * GICD_ISACTIVER0 registers are always RAZ/WI. The corresponding 259 * functionality is replaced by the GICR registers. It doesn't need to sync 260 * them. So it should increase the offset to skip GIC_INTERNAL irqs. 261 * This matches the for_each_dist_irq_reg() macro which also skips the 262 * first GIC_INTERNAL irqs. 263 */ 264 offset += (GIC_INTERNAL * 1) / 8; 265 for_each_dist_irq_reg(irq, s->num_irq, 1) { 266 kvm_gicd_access(s, offset, ®, false); 267 *gic_bmp_ptr32(bmp, irq) = reg; 268 offset += 4; 269 } 270 } 271 272 static void kvm_dist_putbmp(GICv3State *s, uint32_t offset, 273 uint32_t clroffset, uint32_t *bmp) 274 { 275 uint32_t reg; 276 int irq; 277 278 /* For the KVM GICv3, affinity routing is always enabled, and the 279 * GICD_IGROUPR0/GICD_IGRPMODR0/GICD_ISENABLER0/GICD_ISPENDR0/ 280 * GICD_ISACTIVER0 registers are always RAZ/WI. The corresponding 281 * functionality is replaced by the GICR registers. It doesn't need to sync 282 * them. So it should increase the offset and clroffset to skip GIC_INTERNAL 283 * irqs. This matches the for_each_dist_irq_reg() macro which also skips the 284 * first GIC_INTERNAL irqs. 285 */ 286 offset += (GIC_INTERNAL * 1) / 8; 287 if (clroffset != 0) { 288 clroffset += (GIC_INTERNAL * 1) / 8; 289 } 290 291 for_each_dist_irq_reg(irq, s->num_irq, 1) { 292 /* If this bitmap is a set/clear register pair, first write to the 293 * clear-reg to clear all bits before using the set-reg to write 294 * the 1 bits. 295 */ 296 if (clroffset != 0) { 297 reg = 0; 298 kvm_gicd_access(s, clroffset, ®, true); 299 clroffset += 4; 300 } 301 reg = *gic_bmp_ptr32(bmp, irq); 302 kvm_gicd_access(s, offset, ®, true); 303 offset += 4; 304 } 305 } 306 307 static void kvm_arm_gicv3_check(GICv3State *s) 308 { 309 uint32_t reg; 310 uint32_t num_irq; 311 312 /* Sanity checking s->num_irq */ 313 kvm_gicd_access(s, GICD_TYPER, ®, false); 314 num_irq = ((reg & 0x1f) + 1) * 32; 315 316 if (num_irq < s->num_irq) { 317 error_report("Model requests %u IRQs, but kernel supports max %u", 318 s->num_irq, num_irq); 319 abort(); 320 } 321 } 322 323 static void kvm_arm_gicv3_put(GICv3State *s) 324 { 325 uint32_t regl, regh, reg; 326 uint64_t reg64, redist_typer; 327 int ncpu, i; 328 329 kvm_arm_gicv3_check(s); 330 331 kvm_gicr_access(s, GICR_TYPER, 0, ®l, false); 332 kvm_gicr_access(s, GICR_TYPER + 4, 0, ®h, false); 333 redist_typer = ((uint64_t)regh << 32) | regl; 334 335 reg = s->gicd_ctlr; 336 kvm_gicd_access(s, GICD_CTLR, ®, true); 337 338 if (redist_typer & GICR_TYPER_PLPIS) { 339 /* 340 * Restore base addresses before LPIs are potentially enabled by 341 * GICR_CTLR write 342 */ 343 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 344 GICv3CPUState *c = &s->cpu[ncpu]; 345 346 reg64 = c->gicr_propbaser; 347 regl = (uint32_t)reg64; 348 kvm_gicr_access(s, GICR_PROPBASER, ncpu, ®l, true); 349 regh = (uint32_t)(reg64 >> 32); 350 kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, ®h, true); 351 352 reg64 = c->gicr_pendbaser; 353 regl = (uint32_t)reg64; 354 kvm_gicr_access(s, GICR_PENDBASER, ncpu, ®l, true); 355 regh = (uint32_t)(reg64 >> 32); 356 kvm_gicr_access(s, GICR_PENDBASER + 4, ncpu, ®h, true); 357 } 358 } 359 360 /* Redistributor state (one per CPU) */ 361 362 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 363 GICv3CPUState *c = &s->cpu[ncpu]; 364 365 reg = c->gicr_ctlr; 366 kvm_gicr_access(s, GICR_CTLR, ncpu, ®, true); 367 368 reg = c->gicr_statusr[GICV3_NS]; 369 kvm_gicr_access(s, GICR_STATUSR, ncpu, ®, true); 370 371 reg = c->gicr_waker; 372 kvm_gicr_access(s, GICR_WAKER, ncpu, ®, true); 373 374 reg = c->gicr_igroupr0; 375 kvm_gicr_access(s, GICR_IGROUPR0, ncpu, ®, true); 376 377 reg = ~0; 378 kvm_gicr_access(s, GICR_ICENABLER0, ncpu, ®, true); 379 reg = c->gicr_ienabler0; 380 kvm_gicr_access(s, GICR_ISENABLER0, ncpu, ®, true); 381 382 /* Restore config before pending so we treat level/edge correctly */ 383 reg = half_shuffle32(c->edge_trigger >> 16) << 1; 384 kvm_gicr_access(s, GICR_ICFGR1, ncpu, ®, true); 385 386 reg = c->level; 387 kvm_gic_line_level_access(s, 0, ncpu, ®, true); 388 389 reg = ~0; 390 kvm_gicr_access(s, GICR_ICPENDR0, ncpu, ®, true); 391 reg = c->gicr_ipendr0; 392 kvm_gicr_access(s, GICR_ISPENDR0, ncpu, ®, true); 393 394 reg = ~0; 395 kvm_gicr_access(s, GICR_ICACTIVER0, ncpu, ®, true); 396 reg = c->gicr_iactiver0; 397 kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, ®, true); 398 399 for (i = 0; i < GIC_INTERNAL; i += 4) { 400 reg = c->gicr_ipriorityr[i] | 401 (c->gicr_ipriorityr[i + 1] << 8) | 402 (c->gicr_ipriorityr[i + 2] << 16) | 403 (c->gicr_ipriorityr[i + 3] << 24); 404 kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, ®, true); 405 } 406 } 407 408 /* Distributor state (shared between all CPUs */ 409 reg = s->gicd_statusr[GICV3_NS]; 410 kvm_gicd_access(s, GICD_STATUSR, ®, true); 411 412 /* s->enable bitmap -> GICD_ISENABLERn */ 413 kvm_dist_putbmp(s, GICD_ISENABLER, GICD_ICENABLER, s->enabled); 414 415 /* s->group bitmap -> GICD_IGROUPRn */ 416 kvm_dist_putbmp(s, GICD_IGROUPR, 0, s->group); 417 418 /* Restore targets before pending to ensure the pending state is set on 419 * the appropriate CPU interfaces in the kernel 420 */ 421 422 /* s->gicd_irouter[irq] -> GICD_IROUTERn 423 * We can't use kvm_dist_put() here because the registers are 64-bit 424 */ 425 for (i = GIC_INTERNAL; i < s->num_irq; i++) { 426 uint32_t offset; 427 428 offset = GICD_IROUTER + (sizeof(uint32_t) * i); 429 reg = (uint32_t)s->gicd_irouter[i]; 430 kvm_gicd_access(s, offset, ®, true); 431 432 offset = GICD_IROUTER + (sizeof(uint32_t) * i) + 4; 433 reg = (uint32_t)(s->gicd_irouter[i] >> 32); 434 kvm_gicd_access(s, offset, ®, true); 435 } 436 437 /* s->trigger bitmap -> GICD_ICFGRn 438 * (restore configuration registers before pending IRQs so we treat 439 * level/edge correctly) 440 */ 441 kvm_dist_put_edge_trigger(s, GICD_ICFGR, s->edge_trigger); 442 443 /* s->level bitmap -> line_level */ 444 kvm_gic_put_line_level_bmp(s, s->level); 445 446 /* s->pending bitmap -> GICD_ISPENDRn */ 447 kvm_dist_putbmp(s, GICD_ISPENDR, GICD_ICPENDR, s->pending); 448 449 /* s->active bitmap -> GICD_ISACTIVERn */ 450 kvm_dist_putbmp(s, GICD_ISACTIVER, GICD_ICACTIVER, s->active); 451 452 /* s->gicd_ipriority[] -> GICD_IPRIORITYRn */ 453 kvm_dist_put_priority(s, GICD_IPRIORITYR, s->gicd_ipriority); 454 455 /* CPU Interface state (one per CPU) */ 456 457 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 458 GICv3CPUState *c = &s->cpu[ncpu]; 459 int num_pri_bits; 460 461 kvm_gicc_access(s, ICC_SRE_EL1, ncpu, &c->icc_sre_el1, true); 462 kvm_gicc_access(s, ICC_CTLR_EL1, ncpu, 463 &c->icc_ctlr_el1[GICV3_NS], true); 464 kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu, 465 &c->icc_igrpen[GICV3_G0], true); 466 kvm_gicc_access(s, ICC_IGRPEN1_EL1, ncpu, 467 &c->icc_igrpen[GICV3_G1NS], true); 468 kvm_gicc_access(s, ICC_PMR_EL1, ncpu, &c->icc_pmr_el1, true); 469 kvm_gicc_access(s, ICC_BPR0_EL1, ncpu, &c->icc_bpr[GICV3_G0], true); 470 kvm_gicc_access(s, ICC_BPR1_EL1, ncpu, &c->icc_bpr[GICV3_G1NS], true); 471 472 num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] & 473 ICC_CTLR_EL1_PRIBITS_MASK) >> 474 ICC_CTLR_EL1_PRIBITS_SHIFT) + 1; 475 476 switch (num_pri_bits) { 477 case 7: 478 reg64 = c->icc_apr[GICV3_G0][3]; 479 kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, ®64, true); 480 reg64 = c->icc_apr[GICV3_G0][2]; 481 kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, ®64, true); 482 case 6: 483 reg64 = c->icc_apr[GICV3_G0][1]; 484 kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, ®64, true); 485 default: 486 reg64 = c->icc_apr[GICV3_G0][0]; 487 kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, ®64, true); 488 } 489 490 switch (num_pri_bits) { 491 case 7: 492 reg64 = c->icc_apr[GICV3_G1NS][3]; 493 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, ®64, true); 494 reg64 = c->icc_apr[GICV3_G1NS][2]; 495 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, ®64, true); 496 case 6: 497 reg64 = c->icc_apr[GICV3_G1NS][1]; 498 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, ®64, true); 499 default: 500 reg64 = c->icc_apr[GICV3_G1NS][0]; 501 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, ®64, true); 502 } 503 } 504 } 505 506 static void kvm_arm_gicv3_get(GICv3State *s) 507 { 508 uint32_t regl, regh, reg; 509 uint64_t reg64, redist_typer; 510 int ncpu, i; 511 512 kvm_arm_gicv3_check(s); 513 514 kvm_gicr_access(s, GICR_TYPER, 0, ®l, false); 515 kvm_gicr_access(s, GICR_TYPER + 4, 0, ®h, false); 516 redist_typer = ((uint64_t)regh << 32) | regl; 517 518 kvm_gicd_access(s, GICD_CTLR, ®, false); 519 s->gicd_ctlr = reg; 520 521 /* Redistributor state (one per CPU) */ 522 523 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 524 GICv3CPUState *c = &s->cpu[ncpu]; 525 526 kvm_gicr_access(s, GICR_CTLR, ncpu, ®, false); 527 c->gicr_ctlr = reg; 528 529 kvm_gicr_access(s, GICR_STATUSR, ncpu, ®, false); 530 c->gicr_statusr[GICV3_NS] = reg; 531 532 kvm_gicr_access(s, GICR_WAKER, ncpu, ®, false); 533 c->gicr_waker = reg; 534 535 kvm_gicr_access(s, GICR_IGROUPR0, ncpu, ®, false); 536 c->gicr_igroupr0 = reg; 537 kvm_gicr_access(s, GICR_ISENABLER0, ncpu, ®, false); 538 c->gicr_ienabler0 = reg; 539 kvm_gicr_access(s, GICR_ICFGR1, ncpu, ®, false); 540 c->edge_trigger = half_unshuffle32(reg >> 1) << 16; 541 kvm_gic_line_level_access(s, 0, ncpu, ®, false); 542 c->level = reg; 543 kvm_gicr_access(s, GICR_ISPENDR0, ncpu, ®, false); 544 c->gicr_ipendr0 = reg; 545 kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, ®, false); 546 c->gicr_iactiver0 = reg; 547 548 for (i = 0; i < GIC_INTERNAL; i += 4) { 549 kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, ®, false); 550 c->gicr_ipriorityr[i] = extract32(reg, 0, 8); 551 c->gicr_ipriorityr[i + 1] = extract32(reg, 8, 8); 552 c->gicr_ipriorityr[i + 2] = extract32(reg, 16, 8); 553 c->gicr_ipriorityr[i + 3] = extract32(reg, 24, 8); 554 } 555 } 556 557 if (redist_typer & GICR_TYPER_PLPIS) { 558 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 559 GICv3CPUState *c = &s->cpu[ncpu]; 560 561 kvm_gicr_access(s, GICR_PROPBASER, ncpu, ®l, false); 562 kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, ®h, false); 563 c->gicr_propbaser = ((uint64_t)regh << 32) | regl; 564 565 kvm_gicr_access(s, GICR_PENDBASER, ncpu, ®l, false); 566 kvm_gicr_access(s, GICR_PENDBASER + 4, ncpu, ®h, false); 567 c->gicr_pendbaser = ((uint64_t)regh << 32) | regl; 568 } 569 } 570 571 /* Distributor state (shared between all CPUs */ 572 573 kvm_gicd_access(s, GICD_STATUSR, ®, false); 574 s->gicd_statusr[GICV3_NS] = reg; 575 576 /* GICD_IGROUPRn -> s->group bitmap */ 577 kvm_dist_getbmp(s, GICD_IGROUPR, s->group); 578 579 /* GICD_ISENABLERn -> s->enabled bitmap */ 580 kvm_dist_getbmp(s, GICD_ISENABLER, s->enabled); 581 582 /* Line level of irq */ 583 kvm_gic_get_line_level_bmp(s, s->level); 584 /* GICD_ISPENDRn -> s->pending bitmap */ 585 kvm_dist_getbmp(s, GICD_ISPENDR, s->pending); 586 587 /* GICD_ISACTIVERn -> s->active bitmap */ 588 kvm_dist_getbmp(s, GICD_ISACTIVER, s->active); 589 590 /* GICD_ICFGRn -> s->trigger bitmap */ 591 kvm_dist_get_edge_trigger(s, GICD_ICFGR, s->edge_trigger); 592 593 /* GICD_IPRIORITYRn -> s->gicd_ipriority[] */ 594 kvm_dist_get_priority(s, GICD_IPRIORITYR, s->gicd_ipriority); 595 596 /* GICD_IROUTERn -> s->gicd_irouter[irq] */ 597 for (i = GIC_INTERNAL; i < s->num_irq; i++) { 598 uint32_t offset; 599 600 offset = GICD_IROUTER + (sizeof(uint32_t) * i); 601 kvm_gicd_access(s, offset, ®l, false); 602 offset = GICD_IROUTER + (sizeof(uint32_t) * i) + 4; 603 kvm_gicd_access(s, offset, ®h, false); 604 s->gicd_irouter[i] = ((uint64_t)regh << 32) | regl; 605 } 606 607 /***************************************************************** 608 * CPU Interface(s) State 609 */ 610 611 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 612 GICv3CPUState *c = &s->cpu[ncpu]; 613 int num_pri_bits; 614 615 kvm_gicc_access(s, ICC_SRE_EL1, ncpu, &c->icc_sre_el1, false); 616 kvm_gicc_access(s, ICC_CTLR_EL1, ncpu, 617 &c->icc_ctlr_el1[GICV3_NS], false); 618 kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu, 619 &c->icc_igrpen[GICV3_G0], false); 620 kvm_gicc_access(s, ICC_IGRPEN1_EL1, ncpu, 621 &c->icc_igrpen[GICV3_G1NS], false); 622 kvm_gicc_access(s, ICC_PMR_EL1, ncpu, &c->icc_pmr_el1, false); 623 kvm_gicc_access(s, ICC_BPR0_EL1, ncpu, &c->icc_bpr[GICV3_G0], false); 624 kvm_gicc_access(s, ICC_BPR1_EL1, ncpu, &c->icc_bpr[GICV3_G1NS], false); 625 num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] & 626 ICC_CTLR_EL1_PRIBITS_MASK) >> 627 ICC_CTLR_EL1_PRIBITS_SHIFT) + 1; 628 629 switch (num_pri_bits) { 630 case 7: 631 kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, ®64, false); 632 c->icc_apr[GICV3_G0][3] = reg64; 633 kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, ®64, false); 634 c->icc_apr[GICV3_G0][2] = reg64; 635 case 6: 636 kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, ®64, false); 637 c->icc_apr[GICV3_G0][1] = reg64; 638 default: 639 kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, ®64, false); 640 c->icc_apr[GICV3_G0][0] = reg64; 641 } 642 643 switch (num_pri_bits) { 644 case 7: 645 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, ®64, false); 646 c->icc_apr[GICV3_G1NS][3] = reg64; 647 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, ®64, false); 648 c->icc_apr[GICV3_G1NS][2] = reg64; 649 case 6: 650 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, ®64, false); 651 c->icc_apr[GICV3_G1NS][1] = reg64; 652 default: 653 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, ®64, false); 654 c->icc_apr[GICV3_G1NS][0] = reg64; 655 } 656 } 657 } 658 659 static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) 660 { 661 GICv3State *s; 662 GICv3CPUState *c; 663 664 c = (GICv3CPUState *)env->gicv3state; 665 s = c->gic; 666 667 c->icc_pmr_el1 = 0; 668 c->icc_bpr[GICV3_G0] = GIC_MIN_BPR; 669 c->icc_bpr[GICV3_G1] = GIC_MIN_BPR; 670 c->icc_bpr[GICV3_G1NS] = GIC_MIN_BPR; 671 672 c->icc_sre_el1 = 0x7; 673 memset(c->icc_apr, 0, sizeof(c->icc_apr)); 674 memset(c->icc_igrpen, 0, sizeof(c->icc_igrpen)); 675 676 if (s->migration_blocker) { 677 return; 678 } 679 680 /* Initialize to actual HW supported configuration */ 681 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, 682 KVM_VGIC_ATTR(ICC_CTLR_EL1, c->gicr_typer), 683 &c->icc_ctlr_el1[GICV3_NS], false, &error_abort); 684 685 c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS]; 686 } 687 688 static void kvm_arm_gicv3_reset(DeviceState *dev) 689 { 690 GICv3State *s = ARM_GICV3_COMMON(dev); 691 KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s); 692 693 DPRINTF("Reset\n"); 694 695 kgc->parent_reset(dev); 696 697 if (s->migration_blocker) { 698 DPRINTF("Cannot put kernel gic state, no kernel interface\n"); 699 return; 700 } 701 702 kvm_arm_gicv3_put(s); 703 } 704 705 /* 706 * CPU interface registers of GIC needs to be reset on CPU reset. 707 * For the calling arm_gicv3_icc_reset() on CPU reset, we register 708 * below ARMCPRegInfo. As we reset the whole cpu interface under single 709 * register reset, we define only one register of CPU interface instead 710 * of defining all the registers. 711 */ 712 static const ARMCPRegInfo gicv3_cpuif_reginfo[] = { 713 { .name = "ICC_CTLR_EL1", .state = ARM_CP_STATE_BOTH, 714 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 4, 715 /* 716 * If ARM_CP_NOP is used, resetfn is not called, 717 * So ARM_CP_NO_RAW is appropriate type. 718 */ 719 .type = ARM_CP_NO_RAW, 720 .access = PL1_RW, 721 .readfn = arm_cp_read_zero, 722 .writefn = arm_cp_write_ignore, 723 /* 724 * We hang the whole cpu interface reset routine off here 725 * rather than parcelling it out into one little function 726 * per register 727 */ 728 .resetfn = arm_gicv3_icc_reset, 729 }, 730 REGINFO_SENTINEL 731 }; 732 733 /** 734 * vm_change_state_handler - VM change state callback aiming at flushing 735 * RDIST pending tables into guest RAM 736 * 737 * The tables get flushed to guest RAM whenever the VM gets stopped. 738 */ 739 static void vm_change_state_handler(void *opaque, int running, 740 RunState state) 741 { 742 GICv3State *s = (GICv3State *)opaque; 743 Error *err = NULL; 744 int ret; 745 746 if (running) { 747 return; 748 } 749 750 ret = kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, 751 KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES, 752 NULL, true, &err); 753 if (err) { 754 error_report_err(err); 755 } 756 if (ret < 0 && ret != -EFAULT) { 757 abort(); 758 } 759 } 760 761 762 static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) 763 { 764 GICv3State *s = KVM_ARM_GICV3(dev); 765 KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s); 766 bool multiple_redist_region_allowed; 767 Error *local_err = NULL; 768 int i; 769 770 DPRINTF("kvm_arm_gicv3_realize\n"); 771 772 kgc->parent_realize(dev, &local_err); 773 if (local_err) { 774 error_propagate(errp, local_err); 775 return; 776 } 777 778 if (s->security_extn) { 779 error_setg(errp, "the in-kernel VGICv3 does not implement the " 780 "security extensions"); 781 return; 782 } 783 784 gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL, &local_err); 785 if (local_err) { 786 error_propagate(errp, local_err); 787 return; 788 } 789 790 for (i = 0; i < s->num_cpu; i++) { 791 ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i)); 792 793 define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); 794 } 795 796 /* Try to create the device via the device control API */ 797 s->dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V3, false); 798 if (s->dev_fd < 0) { 799 error_setg_errno(errp, -s->dev_fd, "error creating in-kernel VGIC"); 800 return; 801 } 802 803 multiple_redist_region_allowed = 804 kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ADDR, 805 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION); 806 807 if (!multiple_redist_region_allowed && s->nb_redist_regions > 1) { 808 error_setg(errp, "Multiple VGICv3 redistributor regions are not " 809 "supported by this host kernel"); 810 error_append_hint(errp, "A maximum of %d VCPUs can be used", 811 s->redist_region_count[0]); 812 return; 813 } 814 815 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 816 0, &s->num_irq, true, &error_abort); 817 818 /* Tell the kernel to complete VGIC initialization now */ 819 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, 820 KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort); 821 822 kvm_arm_register_device(&s->iomem_dist, -1, KVM_DEV_ARM_VGIC_GRP_ADDR, 823 KVM_VGIC_V3_ADDR_TYPE_DIST, s->dev_fd, 0); 824 825 if (!multiple_redist_region_allowed) { 826 kvm_arm_register_device(&s->iomem_redist[0], -1, 827 KVM_DEV_ARM_VGIC_GRP_ADDR, 828 KVM_VGIC_V3_ADDR_TYPE_REDIST, s->dev_fd, 0); 829 } else { 830 /* we register regions in reverse order as "devices" are inserted at 831 * the head of a QSLIST and the list is then popped from the head 832 * onwards by kvm_arm_machine_init_done() 833 */ 834 for (i = s->nb_redist_regions - 1; i >= 0; i--) { 835 /* Address mask made of the rdist region index and count */ 836 uint64_t addr_ormask = 837 i | ((uint64_t)s->redist_region_count[i] << 52); 838 839 kvm_arm_register_device(&s->iomem_redist[i], -1, 840 KVM_DEV_ARM_VGIC_GRP_ADDR, 841 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION, 842 s->dev_fd, addr_ormask); 843 } 844 } 845 846 if (kvm_has_gsi_routing()) { 847 /* set up irq routing */ 848 for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) { 849 kvm_irqchip_add_irq_route(kvm_state, i, 0, i); 850 } 851 852 kvm_gsi_routing_allowed = true; 853 854 kvm_irqchip_commit_routes(kvm_state); 855 } 856 857 if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS, 858 GICD_CTLR)) { 859 error_setg(&s->migration_blocker, "This operating system kernel does " 860 "not support vGICv3 migration"); 861 migrate_add_blocker(s->migration_blocker, &local_err); 862 if (local_err) { 863 error_propagate(errp, local_err); 864 error_free(s->migration_blocker); 865 return; 866 } 867 } 868 if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, 869 KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES)) { 870 qemu_add_vm_change_state_handler(vm_change_state_handler, s); 871 } 872 } 873 874 static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data) 875 { 876 DeviceClass *dc = DEVICE_CLASS(klass); 877 ARMGICv3CommonClass *agcc = ARM_GICV3_COMMON_CLASS(klass); 878 KVMARMGICv3Class *kgc = KVM_ARM_GICV3_CLASS(klass); 879 880 agcc->pre_save = kvm_arm_gicv3_get; 881 agcc->post_load = kvm_arm_gicv3_put; 882 device_class_set_parent_realize(dc, kvm_arm_gicv3_realize, 883 &kgc->parent_realize); 884 device_class_set_parent_reset(dc, kvm_arm_gicv3_reset, &kgc->parent_reset); 885 } 886 887 static const TypeInfo kvm_arm_gicv3_info = { 888 .name = TYPE_KVM_ARM_GICV3, 889 .parent = TYPE_ARM_GICV3_COMMON, 890 .instance_size = sizeof(GICv3State), 891 .class_init = kvm_arm_gicv3_class_init, 892 .class_size = sizeof(KVMARMGICv3Class), 893 }; 894 895 static void kvm_arm_gicv3_register_types(void) 896 { 897 type_register_static(&kvm_arm_gicv3_info); 898 } 899 900 type_init(kvm_arm_gicv3_register_types) 901