xref: /openbmc/qemu/hw/intc/arm_gicv3_its_kvm.c (revision 2b74dd91)
1 /*
2  * KVM-based ITS implementation for a GICv3-based system
3  *
4  * Copyright (c) 2015 Samsung Electronics Co., Ltd.
5  * Written by Pavel Fedin <p.fedin@samsung.com>
6  *
7  * This library is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU Lesser General Public
9  * License as published by the Free Software Foundation; either
10  * version 2.1 of the License, or (at your option) any later version.
11  *
12  * This library is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15  * Lesser General Public License for more details.
16  *
17  * You should have received a copy of the GNU Lesser General Public
18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19  */
20 
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "qemu/module.h"
24 #include "qemu/error-report.h"
25 #include "hw/intc/arm_gicv3_its_common.h"
26 #include "hw/qdev-properties.h"
27 #include "sysemu/runstate.h"
28 #include "sysemu/kvm.h"
29 #include "kvm_arm.h"
30 #include "migration/blocker.h"
31 #include "qom/object.h"
32 
33 #define TYPE_KVM_ARM_ITS "arm-its-kvm"
34 typedef struct KVMARMITSClass KVMARMITSClass;
35 /* This is reusing the GICv3ITSState typedef from ARM_GICV3_ITS_COMMON */
36 DECLARE_OBJ_CHECKERS(GICv3ITSState, KVMARMITSClass,
37                      KVM_ARM_ITS, TYPE_KVM_ARM_ITS)
38 
39 struct KVMARMITSClass {
40     GICv3ITSCommonClass parent_class;
41     ResettablePhases parent_phases;
42 };
43 
44 
45 static int kvm_its_send_msi(GICv3ITSState *s, uint32_t value, uint16_t devid)
46 {
47     struct kvm_msi msi;
48 
49     if (unlikely(!s->translater_gpa_known)) {
50         MemoryRegion *mr = &s->iomem_its_translation;
51         MemoryRegionSection mrs;
52 
53         mrs = memory_region_find(mr, 0, 1);
54         memory_region_unref(mrs.mr);
55         s->gits_translater_gpa = mrs.offset_within_address_space + 0x40;
56         s->translater_gpa_known = true;
57     }
58 
59     msi.address_lo = extract64(s->gits_translater_gpa, 0, 32);
60     msi.address_hi = extract64(s->gits_translater_gpa, 32, 32);
61     msi.data = le32_to_cpu(value);
62     msi.flags = KVM_MSI_VALID_DEVID;
63     msi.devid = devid;
64     memset(msi.pad, 0, sizeof(msi.pad));
65 
66     return kvm_vm_ioctl(kvm_state, KVM_SIGNAL_MSI, &msi);
67 }
68 
69 /**
70  * vm_change_state_handler - VM change state callback aiming at flushing
71  * ITS tables into guest RAM
72  *
73  * The tables get flushed to guest RAM whenever the VM gets stopped.
74  */
75 static void vm_change_state_handler(void *opaque, bool running,
76                                     RunState state)
77 {
78     GICv3ITSState *s = (GICv3ITSState *)opaque;
79     Error *err = NULL;
80 
81     if (running) {
82         return;
83     }
84 
85     kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
86                       KVM_DEV_ARM_ITS_SAVE_TABLES, NULL, true, &err);
87     if (err) {
88         error_report_err(err);
89     }
90 }
91 
92 static void kvm_arm_its_realize(DeviceState *dev, Error **errp)
93 {
94     GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
95 
96     s->dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_ITS, false);
97     if (s->dev_fd < 0) {
98         error_setg_errno(errp, -s->dev_fd, "error creating in-kernel ITS");
99         return;
100     }
101 
102     /* explicit init of the ITS */
103     kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
104                       KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort);
105 
106     /* register the base address */
107     kvm_arm_register_device(&s->iomem_its_cntrl, -1, KVM_DEV_ARM_VGIC_GRP_ADDR,
108                             KVM_VGIC_ITS_ADDR_TYPE, s->dev_fd, 0);
109 
110     gicv3_add_its(s->gicv3, dev);
111 
112     gicv3_its_init_mmio(s, NULL, NULL);
113 
114     if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
115         GITS_CTLR)) {
116         error_setg(&s->migration_blocker, "This operating system kernel "
117                    "does not support vITS migration");
118         if (migrate_add_blocker(&s->migration_blocker, errp) < 0) {
119             return;
120         }
121     } else {
122         qemu_add_vm_change_state_handler(vm_change_state_handler, s);
123     }
124 
125     kvm_msi_use_devid = true;
126     kvm_gsi_direct_mapping = false;
127     kvm_msi_via_irqfd_allowed = true;
128 }
129 
130 /**
131  * kvm_arm_its_pre_save - handles the saving of ITS registers.
132  * ITS tables are flushed into guest RAM separately and earlier,
133  * through the VM change state handler, since at the moment pre_save()
134  * is called, the guest RAM has already been saved.
135  */
136 static void kvm_arm_its_pre_save(GICv3ITSState *s)
137 {
138     int i;
139 
140     for (i = 0; i < 8; i++) {
141         kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
142                           GITS_BASER + i * 8, &s->baser[i], false,
143                           &error_abort);
144     }
145 
146     kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
147                       GITS_CTLR, &s->ctlr, false, &error_abort);
148 
149     kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
150                       GITS_CBASER, &s->cbaser, false, &error_abort);
151 
152     kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
153                       GITS_CREADR, &s->creadr, false, &error_abort);
154 
155     kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
156                       GITS_CWRITER, &s->cwriter, false, &error_abort);
157 
158     kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
159                       GITS_IIDR, &s->iidr, false, &error_abort);
160 }
161 
162 /**
163  * kvm_arm_its_post_load - Restore both the ITS registers and tables
164  */
165 static void kvm_arm_its_post_load(GICv3ITSState *s)
166 {
167     int i;
168 
169     kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
170                       GITS_IIDR, &s->iidr, true, &error_abort);
171 
172     /*
173      * must be written before GITS_CREADR since GITS_CBASER write
174      * access resets GITS_CREADR.
175      */
176     kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
177                       GITS_CBASER, &s->cbaser, true, &error_abort);
178 
179     kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
180                       GITS_CREADR, &s->creadr, true, &error_abort);
181 
182     kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
183                       GITS_CWRITER, &s->cwriter, true, &error_abort);
184 
185 
186     for (i = 0; i < 8; i++) {
187         kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
188                           GITS_BASER + i * 8, &s->baser[i], true,
189                           &error_abort);
190     }
191 
192     kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
193                       KVM_DEV_ARM_ITS_RESTORE_TABLES, NULL, true,
194                       &error_abort);
195 
196     kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
197                       GITS_CTLR, &s->ctlr, true, &error_abort);
198 }
199 
200 static void kvm_arm_its_reset_hold(Object *obj, ResetType type)
201 {
202     GICv3ITSState *s = ARM_GICV3_ITS_COMMON(obj);
203     KVMARMITSClass *c = KVM_ARM_ITS_GET_CLASS(s);
204     int i;
205 
206     if (c->parent_phases.hold) {
207         c->parent_phases.hold(obj, type);
208     }
209 
210     if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
211                                KVM_DEV_ARM_ITS_CTRL_RESET)) {
212         kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
213                           KVM_DEV_ARM_ITS_CTRL_RESET, NULL, true, &error_abort);
214         return;
215     }
216 
217     warn_report("ITS KVM: full reset is not supported by the host kernel");
218 
219     if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
220                                GITS_CTLR)) {
221         return;
222     }
223 
224     kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
225                       GITS_CTLR, &s->ctlr, true, &error_abort);
226 
227     kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
228                       GITS_CBASER, &s->cbaser, true, &error_abort);
229 
230     for (i = 0; i < 8; i++) {
231         kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
232                           GITS_BASER + i * 8, &s->baser[i], true,
233                           &error_abort);
234     }
235 }
236 
237 static Property kvm_arm_its_props[] = {
238     DEFINE_PROP_LINK("parent-gicv3", GICv3ITSState, gicv3, "kvm-arm-gicv3",
239                      GICv3State *),
240     DEFINE_PROP_END_OF_LIST(),
241 };
242 
243 static void kvm_arm_its_class_init(ObjectClass *klass, void *data)
244 {
245     DeviceClass *dc = DEVICE_CLASS(klass);
246     ResettableClass *rc = RESETTABLE_CLASS(klass);
247     GICv3ITSCommonClass *icc = ARM_GICV3_ITS_COMMON_CLASS(klass);
248     KVMARMITSClass *ic = KVM_ARM_ITS_CLASS(klass);
249 
250     dc->realize = kvm_arm_its_realize;
251     device_class_set_props(dc, kvm_arm_its_props);
252     resettable_class_set_parent_phases(rc, NULL, kvm_arm_its_reset_hold, NULL,
253                                        &ic->parent_phases);
254     icc->send_msi = kvm_its_send_msi;
255     icc->pre_save = kvm_arm_its_pre_save;
256     icc->post_load = kvm_arm_its_post_load;
257 }
258 
259 static const TypeInfo kvm_arm_its_info = {
260     .name = TYPE_KVM_ARM_ITS,
261     .parent = TYPE_ARM_GICV3_ITS_COMMON,
262     .instance_size = sizeof(GICv3ITSState),
263     .class_init = kvm_arm_its_class_init,
264     .class_size = sizeof(KVMARMITSClass),
265 };
266 
267 static void kvm_arm_its_register_types(void)
268 {
269     type_register_static(&kvm_arm_its_info);
270 }
271 
272 type_init(kvm_arm_its_register_types)
273