1386ce3c7SPavel Fedin /* 2386ce3c7SPavel Fedin * ITS base class for a GICv3-based system 3386ce3c7SPavel Fedin * 4386ce3c7SPavel Fedin * Copyright (c) 2015 Samsung Electronics Co., Ltd. 5386ce3c7SPavel Fedin * Written by Pavel Fedin 6386ce3c7SPavel Fedin * 7386ce3c7SPavel Fedin * This program is free software; you can redistribute it and/or modify 8386ce3c7SPavel Fedin * it under the terms of the GNU General Public License as published by 9386ce3c7SPavel Fedin * the Free Software Foundation, either version 2 of the License, or 10386ce3c7SPavel Fedin * (at your option) any later version. 11386ce3c7SPavel Fedin * 12386ce3c7SPavel Fedin * This program is distributed in the hope that it will be useful, 13386ce3c7SPavel Fedin * but WITHOUT ANY WARRANTY; without even the implied warranty of 14386ce3c7SPavel Fedin * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15386ce3c7SPavel Fedin * GNU General Public License for more details. 16386ce3c7SPavel Fedin * 17386ce3c7SPavel Fedin * You should have received a copy of the GNU General Public License along 18386ce3c7SPavel Fedin * with this program; if not, see <http://www.gnu.org/licenses/>. 19386ce3c7SPavel Fedin */ 20386ce3c7SPavel Fedin 21386ce3c7SPavel Fedin #include "qemu/osdep.h" 22386ce3c7SPavel Fedin #include "hw/pci/msi.h" 23386ce3c7SPavel Fedin #include "hw/intc/arm_gicv3_its_common.h" 24386ce3c7SPavel Fedin #include "qemu/log.h" 25386ce3c7SPavel Fedin 2644b1ff31SDr. David Alan Gilbert static int gicv3_its_pre_save(void *opaque) 27386ce3c7SPavel Fedin { 28386ce3c7SPavel Fedin GICv3ITSState *s = (GICv3ITSState *)opaque; 29386ce3c7SPavel Fedin GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s); 30386ce3c7SPavel Fedin 31386ce3c7SPavel Fedin if (c->pre_save) { 32386ce3c7SPavel Fedin c->pre_save(s); 33386ce3c7SPavel Fedin } 3444b1ff31SDr. David Alan Gilbert 3544b1ff31SDr. David Alan Gilbert return 0; 36386ce3c7SPavel Fedin } 37386ce3c7SPavel Fedin 38386ce3c7SPavel Fedin static int gicv3_its_post_load(void *opaque, int version_id) 39386ce3c7SPavel Fedin { 40386ce3c7SPavel Fedin GICv3ITSState *s = (GICv3ITSState *)opaque; 41386ce3c7SPavel Fedin GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s); 42386ce3c7SPavel Fedin 43386ce3c7SPavel Fedin if (c->post_load) { 44386ce3c7SPavel Fedin c->post_load(s); 45386ce3c7SPavel Fedin } 46386ce3c7SPavel Fedin return 0; 47386ce3c7SPavel Fedin } 48386ce3c7SPavel Fedin 49386ce3c7SPavel Fedin static const VMStateDescription vmstate_its = { 50386ce3c7SPavel Fedin .name = "arm_gicv3_its", 51386ce3c7SPavel Fedin .pre_save = gicv3_its_pre_save, 52386ce3c7SPavel Fedin .post_load = gicv3_its_post_load, 53252a7a6aSEric Auger .priority = MIG_PRI_GICV3_ITS, 54cddafd8fSEric Auger .fields = (VMStateField[]) { 55cddafd8fSEric Auger VMSTATE_UINT32(ctlr, GICv3ITSState), 56cddafd8fSEric Auger VMSTATE_UINT32(iidr, GICv3ITSState), 57cddafd8fSEric Auger VMSTATE_UINT64(cbaser, GICv3ITSState), 58cddafd8fSEric Auger VMSTATE_UINT64(cwriter, GICv3ITSState), 59cddafd8fSEric Auger VMSTATE_UINT64(creadr, GICv3ITSState), 60cddafd8fSEric Auger VMSTATE_UINT64_ARRAY(baser, GICv3ITSState, 8), 61cddafd8fSEric Auger VMSTATE_END_OF_LIST() 62cddafd8fSEric Auger }, 63386ce3c7SPavel Fedin }; 64386ce3c7SPavel Fedin 65386ce3c7SPavel Fedin static MemTxResult gicv3_its_trans_read(void *opaque, hwaddr offset, 66386ce3c7SPavel Fedin uint64_t *data, unsigned size, 67386ce3c7SPavel Fedin MemTxAttrs attrs) 68386ce3c7SPavel Fedin { 69386ce3c7SPavel Fedin qemu_log_mask(LOG_GUEST_ERROR, "ITS read at offset 0x%"PRIx64"\n", offset); 70*f1945632SPeter Maydell *data = 0; 71*f1945632SPeter Maydell return MEMTX_OK; 72386ce3c7SPavel Fedin } 73386ce3c7SPavel Fedin 74386ce3c7SPavel Fedin static MemTxResult gicv3_its_trans_write(void *opaque, hwaddr offset, 75386ce3c7SPavel Fedin uint64_t value, unsigned size, 76386ce3c7SPavel Fedin MemTxAttrs attrs) 77386ce3c7SPavel Fedin { 78386ce3c7SPavel Fedin if (offset == 0x0040 && ((size == 2) || (size == 4))) { 79386ce3c7SPavel Fedin GICv3ITSState *s = ARM_GICV3_ITS_COMMON(opaque); 80386ce3c7SPavel Fedin GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s); 81386ce3c7SPavel Fedin int ret = c->send_msi(s, le64_to_cpu(value), attrs.requester_id); 82386ce3c7SPavel Fedin 83386ce3c7SPavel Fedin if (ret <= 0) { 84386ce3c7SPavel Fedin qemu_log_mask(LOG_GUEST_ERROR, 85386ce3c7SPavel Fedin "ITS: Error sending MSI: %s\n", strerror(-ret)); 86386ce3c7SPavel Fedin } 87386ce3c7SPavel Fedin } else { 88386ce3c7SPavel Fedin qemu_log_mask(LOG_GUEST_ERROR, 89386ce3c7SPavel Fedin "ITS write at bad offset 0x%"PRIx64"\n", offset); 90386ce3c7SPavel Fedin } 91*f1945632SPeter Maydell return MEMTX_OK; 92386ce3c7SPavel Fedin } 93386ce3c7SPavel Fedin 94386ce3c7SPavel Fedin static const MemoryRegionOps gicv3_its_trans_ops = { 95386ce3c7SPavel Fedin .read_with_attrs = gicv3_its_trans_read, 96386ce3c7SPavel Fedin .write_with_attrs = gicv3_its_trans_write, 97386ce3c7SPavel Fedin .endianness = DEVICE_NATIVE_ENDIAN, 98386ce3c7SPavel Fedin }; 99386ce3c7SPavel Fedin 100386ce3c7SPavel Fedin void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops) 101386ce3c7SPavel Fedin { 102386ce3c7SPavel Fedin SysBusDevice *sbd = SYS_BUS_DEVICE(s); 103386ce3c7SPavel Fedin 104386ce3c7SPavel Fedin memory_region_init_io(&s->iomem_its_cntrl, OBJECT(s), ops, s, 105386ce3c7SPavel Fedin "control", ITS_CONTROL_SIZE); 106386ce3c7SPavel Fedin memory_region_init_io(&s->iomem_its_translation, OBJECT(s), 107386ce3c7SPavel Fedin &gicv3_its_trans_ops, s, 108386ce3c7SPavel Fedin "translation", ITS_TRANS_SIZE); 109386ce3c7SPavel Fedin 110386ce3c7SPavel Fedin /* Our two regions are always adjacent, therefore we now combine them 111386ce3c7SPavel Fedin * into a single one in order to make our users' life easier. 112386ce3c7SPavel Fedin */ 113386ce3c7SPavel Fedin memory_region_init(&s->iomem_main, OBJECT(s), "gicv3_its", ITS_SIZE); 114386ce3c7SPavel Fedin memory_region_add_subregion(&s->iomem_main, 0, &s->iomem_its_cntrl); 115386ce3c7SPavel Fedin memory_region_add_subregion(&s->iomem_main, ITS_CONTROL_SIZE, 116386ce3c7SPavel Fedin &s->iomem_its_translation); 117386ce3c7SPavel Fedin sysbus_init_mmio(sbd, &s->iomem_main); 118386ce3c7SPavel Fedin 119386ce3c7SPavel Fedin msi_nonbroken = true; 120386ce3c7SPavel Fedin } 121386ce3c7SPavel Fedin 122386ce3c7SPavel Fedin static void gicv3_its_common_reset(DeviceState *dev) 123386ce3c7SPavel Fedin { 124386ce3c7SPavel Fedin GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev); 125386ce3c7SPavel Fedin 126386ce3c7SPavel Fedin s->ctlr = 0; 127386ce3c7SPavel Fedin s->cbaser = 0; 128386ce3c7SPavel Fedin s->cwriter = 0; 129386ce3c7SPavel Fedin s->creadr = 0; 130cddafd8fSEric Auger s->iidr = 0; 131386ce3c7SPavel Fedin memset(&s->baser, 0, sizeof(s->baser)); 132386ce3c7SPavel Fedin } 133386ce3c7SPavel Fedin 134386ce3c7SPavel Fedin static void gicv3_its_common_class_init(ObjectClass *klass, void *data) 135386ce3c7SPavel Fedin { 136386ce3c7SPavel Fedin DeviceClass *dc = DEVICE_CLASS(klass); 137386ce3c7SPavel Fedin 138386ce3c7SPavel Fedin dc->reset = gicv3_its_common_reset; 139386ce3c7SPavel Fedin dc->vmsd = &vmstate_its; 140386ce3c7SPavel Fedin } 141386ce3c7SPavel Fedin 142386ce3c7SPavel Fedin static const TypeInfo gicv3_its_common_info = { 143386ce3c7SPavel Fedin .name = TYPE_ARM_GICV3_ITS_COMMON, 144386ce3c7SPavel Fedin .parent = TYPE_SYS_BUS_DEVICE, 145386ce3c7SPavel Fedin .instance_size = sizeof(GICv3ITSState), 146386ce3c7SPavel Fedin .class_size = sizeof(GICv3ITSCommonClass), 147386ce3c7SPavel Fedin .class_init = gicv3_its_common_class_init, 148386ce3c7SPavel Fedin .abstract = true, 149386ce3c7SPavel Fedin }; 150386ce3c7SPavel Fedin 151386ce3c7SPavel Fedin static void gicv3_its_common_register_types(void) 152386ce3c7SPavel Fedin { 153386ce3c7SPavel Fedin type_register_static(&gicv3_its_common_info); 154386ce3c7SPavel Fedin } 155386ce3c7SPavel Fedin 156386ce3c7SPavel Fedin type_init(gicv3_its_common_register_types) 157