1386ce3c7SPavel Fedin /* 2386ce3c7SPavel Fedin * ITS base class for a GICv3-based system 3386ce3c7SPavel Fedin * 4386ce3c7SPavel Fedin * Copyright (c) 2015 Samsung Electronics Co., Ltd. 5386ce3c7SPavel Fedin * Written by Pavel Fedin 6386ce3c7SPavel Fedin * 7386ce3c7SPavel Fedin * This program is free software; you can redistribute it and/or modify 8386ce3c7SPavel Fedin * it under the terms of the GNU General Public License as published by 9386ce3c7SPavel Fedin * the Free Software Foundation, either version 2 of the License, or 10386ce3c7SPavel Fedin * (at your option) any later version. 11386ce3c7SPavel Fedin * 12386ce3c7SPavel Fedin * This program is distributed in the hope that it will be useful, 13386ce3c7SPavel Fedin * but WITHOUT ANY WARRANTY; without even the implied warranty of 14386ce3c7SPavel Fedin * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15386ce3c7SPavel Fedin * GNU General Public License for more details. 16386ce3c7SPavel Fedin * 17386ce3c7SPavel Fedin * You should have received a copy of the GNU General Public License along 18386ce3c7SPavel Fedin * with this program; if not, see <http://www.gnu.org/licenses/>. 19386ce3c7SPavel Fedin */ 20386ce3c7SPavel Fedin 21386ce3c7SPavel Fedin #include "qemu/osdep.h" 22386ce3c7SPavel Fedin #include "hw/pci/msi.h" 23d6454270SMarkus Armbruster #include "migration/vmstate.h" 24386ce3c7SPavel Fedin #include "hw/intc/arm_gicv3_its_common.h" 25386ce3c7SPavel Fedin #include "qemu/log.h" 260b8fa32fSMarkus Armbruster #include "qemu/module.h" 27386ce3c7SPavel Fedin 2844b1ff31SDr. David Alan Gilbert static int gicv3_its_pre_save(void *opaque) 29386ce3c7SPavel Fedin { 30386ce3c7SPavel Fedin GICv3ITSState *s = (GICv3ITSState *)opaque; 31386ce3c7SPavel Fedin GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s); 32386ce3c7SPavel Fedin 33386ce3c7SPavel Fedin if (c->pre_save) { 34386ce3c7SPavel Fedin c->pre_save(s); 35386ce3c7SPavel Fedin } 3644b1ff31SDr. David Alan Gilbert 3744b1ff31SDr. David Alan Gilbert return 0; 38386ce3c7SPavel Fedin } 39386ce3c7SPavel Fedin 40386ce3c7SPavel Fedin static int gicv3_its_post_load(void *opaque, int version_id) 41386ce3c7SPavel Fedin { 42386ce3c7SPavel Fedin GICv3ITSState *s = (GICv3ITSState *)opaque; 43386ce3c7SPavel Fedin GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s); 44386ce3c7SPavel Fedin 45386ce3c7SPavel Fedin if (c->post_load) { 46386ce3c7SPavel Fedin c->post_load(s); 47386ce3c7SPavel Fedin } 48386ce3c7SPavel Fedin return 0; 49386ce3c7SPavel Fedin } 50386ce3c7SPavel Fedin 51386ce3c7SPavel Fedin static const VMStateDescription vmstate_its = { 52386ce3c7SPavel Fedin .name = "arm_gicv3_its", 53386ce3c7SPavel Fedin .pre_save = gicv3_its_pre_save, 54386ce3c7SPavel Fedin .post_load = gicv3_its_post_load, 55252a7a6aSEric Auger .priority = MIG_PRI_GICV3_ITS, 56cddafd8fSEric Auger .fields = (VMStateField[]) { 57cddafd8fSEric Auger VMSTATE_UINT32(ctlr, GICv3ITSState), 58cddafd8fSEric Auger VMSTATE_UINT32(iidr, GICv3ITSState), 59cddafd8fSEric Auger VMSTATE_UINT64(cbaser, GICv3ITSState), 60cddafd8fSEric Auger VMSTATE_UINT64(cwriter, GICv3ITSState), 61cddafd8fSEric Auger VMSTATE_UINT64(creadr, GICv3ITSState), 62cddafd8fSEric Auger VMSTATE_UINT64_ARRAY(baser, GICv3ITSState, 8), 63cddafd8fSEric Auger VMSTATE_END_OF_LIST() 64cddafd8fSEric Auger }, 65386ce3c7SPavel Fedin }; 66386ce3c7SPavel Fedin 67386ce3c7SPavel Fedin static MemTxResult gicv3_its_trans_read(void *opaque, hwaddr offset, 68386ce3c7SPavel Fedin uint64_t *data, unsigned size, 69386ce3c7SPavel Fedin MemTxAttrs attrs) 70386ce3c7SPavel Fedin { 71386ce3c7SPavel Fedin qemu_log_mask(LOG_GUEST_ERROR, "ITS read at offset 0x%"PRIx64"\n", offset); 72f1945632SPeter Maydell *data = 0; 73f1945632SPeter Maydell return MEMTX_OK; 74386ce3c7SPavel Fedin } 75386ce3c7SPavel Fedin 76386ce3c7SPavel Fedin static MemTxResult gicv3_its_trans_write(void *opaque, hwaddr offset, 77386ce3c7SPavel Fedin uint64_t value, unsigned size, 78386ce3c7SPavel Fedin MemTxAttrs attrs) 79386ce3c7SPavel Fedin { 80386ce3c7SPavel Fedin if (offset == 0x0040 && ((size == 2) || (size == 4))) { 81386ce3c7SPavel Fedin GICv3ITSState *s = ARM_GICV3_ITS_COMMON(opaque); 82386ce3c7SPavel Fedin GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s); 83386ce3c7SPavel Fedin int ret = c->send_msi(s, le64_to_cpu(value), attrs.requester_id); 84386ce3c7SPavel Fedin 85386ce3c7SPavel Fedin if (ret <= 0) { 86386ce3c7SPavel Fedin qemu_log_mask(LOG_GUEST_ERROR, 87386ce3c7SPavel Fedin "ITS: Error sending MSI: %s\n", strerror(-ret)); 88386ce3c7SPavel Fedin } 89386ce3c7SPavel Fedin } else { 90386ce3c7SPavel Fedin qemu_log_mask(LOG_GUEST_ERROR, 91386ce3c7SPavel Fedin "ITS write at bad offset 0x%"PRIx64"\n", offset); 92386ce3c7SPavel Fedin } 93f1945632SPeter Maydell return MEMTX_OK; 94386ce3c7SPavel Fedin } 95386ce3c7SPavel Fedin 96386ce3c7SPavel Fedin static const MemoryRegionOps gicv3_its_trans_ops = { 97386ce3c7SPavel Fedin .read_with_attrs = gicv3_its_trans_read, 98386ce3c7SPavel Fedin .write_with_attrs = gicv3_its_trans_write, 99386ce3c7SPavel Fedin .endianness = DEVICE_NATIVE_ENDIAN, 100386ce3c7SPavel Fedin }; 101386ce3c7SPavel Fedin 10218f6290aSShashi Mallela void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops, 10318f6290aSShashi Mallela const MemoryRegionOps *tops) 104386ce3c7SPavel Fedin { 105386ce3c7SPavel Fedin SysBusDevice *sbd = SYS_BUS_DEVICE(s); 106386ce3c7SPavel Fedin 107386ce3c7SPavel Fedin memory_region_init_io(&s->iomem_its_cntrl, OBJECT(s), ops, s, 108386ce3c7SPavel Fedin "control", ITS_CONTROL_SIZE); 109386ce3c7SPavel Fedin memory_region_init_io(&s->iomem_its_translation, OBJECT(s), 11018f6290aSShashi Mallela tops ? tops : &gicv3_its_trans_ops, s, 111386ce3c7SPavel Fedin "translation", ITS_TRANS_SIZE); 112386ce3c7SPavel Fedin 113386ce3c7SPavel Fedin /* Our two regions are always adjacent, therefore we now combine them 114386ce3c7SPavel Fedin * into a single one in order to make our users' life easier. 115386ce3c7SPavel Fedin */ 116386ce3c7SPavel Fedin memory_region_init(&s->iomem_main, OBJECT(s), "gicv3_its", ITS_SIZE); 117386ce3c7SPavel Fedin memory_region_add_subregion(&s->iomem_main, 0, &s->iomem_its_cntrl); 118386ce3c7SPavel Fedin memory_region_add_subregion(&s->iomem_main, ITS_CONTROL_SIZE, 119386ce3c7SPavel Fedin &s->iomem_its_translation); 120386ce3c7SPavel Fedin sysbus_init_mmio(sbd, &s->iomem_main); 121386ce3c7SPavel Fedin 122386ce3c7SPavel Fedin msi_nonbroken = true; 123386ce3c7SPavel Fedin } 124386ce3c7SPavel Fedin 125*1f688761SPeter Maydell static void gicv3_its_common_reset_hold(Object *obj) 126386ce3c7SPavel Fedin { 127*1f688761SPeter Maydell GICv3ITSState *s = ARM_GICV3_ITS_COMMON(obj); 128386ce3c7SPavel Fedin 129386ce3c7SPavel Fedin s->ctlr = 0; 130386ce3c7SPavel Fedin s->cbaser = 0; 131386ce3c7SPavel Fedin s->cwriter = 0; 132386ce3c7SPavel Fedin s->creadr = 0; 133cddafd8fSEric Auger s->iidr = 0; 134386ce3c7SPavel Fedin memset(&s->baser, 0, sizeof(s->baser)); 135386ce3c7SPavel Fedin } 136386ce3c7SPavel Fedin 137386ce3c7SPavel Fedin static void gicv3_its_common_class_init(ObjectClass *klass, void *data) 138386ce3c7SPavel Fedin { 139386ce3c7SPavel Fedin DeviceClass *dc = DEVICE_CLASS(klass); 140*1f688761SPeter Maydell ResettableClass *rc = RESETTABLE_CLASS(klass); 141386ce3c7SPavel Fedin 142*1f688761SPeter Maydell rc->phases.hold = gicv3_its_common_reset_hold; 143386ce3c7SPavel Fedin dc->vmsd = &vmstate_its; 144386ce3c7SPavel Fedin } 145386ce3c7SPavel Fedin 146386ce3c7SPavel Fedin static const TypeInfo gicv3_its_common_info = { 147386ce3c7SPavel Fedin .name = TYPE_ARM_GICV3_ITS_COMMON, 148386ce3c7SPavel Fedin .parent = TYPE_SYS_BUS_DEVICE, 149386ce3c7SPavel Fedin .instance_size = sizeof(GICv3ITSState), 150386ce3c7SPavel Fedin .class_size = sizeof(GICv3ITSCommonClass), 151386ce3c7SPavel Fedin .class_init = gicv3_its_common_class_init, 152386ce3c7SPavel Fedin .abstract = true, 153386ce3c7SPavel Fedin }; 154386ce3c7SPavel Fedin 155386ce3c7SPavel Fedin static void gicv3_its_common_register_types(void) 156386ce3c7SPavel Fedin { 157386ce3c7SPavel Fedin type_register_static(&gicv3_its_common_info); 158386ce3c7SPavel Fedin } 159386ce3c7SPavel Fedin 160386ce3c7SPavel Fedin type_init(gicv3_its_common_register_types) 161