1 /* 2 * ITS emulation for a GICv3-based system 3 * 4 * Copyright Linaro.org 2021 5 * 6 * Authors: 7 * Shashi Mallela <shashi.mallela@linaro.org> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or (at your 10 * option) any later version. See the COPYING file in the top-level directory. 11 * 12 */ 13 14 #include "qemu/osdep.h" 15 #include "qemu/log.h" 16 #include "trace.h" 17 #include "hw/qdev-properties.h" 18 #include "hw/intc/arm_gicv3_its_common.h" 19 #include "gicv3_internal.h" 20 #include "qom/object.h" 21 #include "qapi/error.h" 22 23 typedef struct GICv3ITSClass GICv3ITSClass; 24 /* This is reusing the GICv3ITSState typedef from ARM_GICV3_ITS_COMMON */ 25 DECLARE_OBJ_CHECKERS(GICv3ITSState, GICv3ITSClass, 26 ARM_GICV3_ITS, TYPE_ARM_GICV3_ITS) 27 28 struct GICv3ITSClass { 29 GICv3ITSCommonClass parent_class; 30 void (*parent_reset)(DeviceState *dev); 31 }; 32 33 /* 34 * This is an internal enum used to distinguish between LPI triggered 35 * via command queue and LPI triggered via gits_translater write. 36 */ 37 typedef enum ItsCmdType { 38 NONE = 0, /* internal indication for GITS_TRANSLATER write */ 39 CLEAR = 1, 40 DISCARD = 2, 41 INTERRUPT = 3, 42 } ItsCmdType; 43 44 typedef struct { 45 uint32_t iteh; 46 uint64_t itel; 47 } IteEntry; 48 49 /* 50 * The ITS spec permits a range of CONSTRAINED UNPREDICTABLE options 51 * if a command parameter is not correct. These include both "stall 52 * processing of the command queue" and "ignore this command, and 53 * keep processing the queue". In our implementation we choose that 54 * memory transaction errors reading the command packet provoke a 55 * stall, but errors in parameters cause us to ignore the command 56 * and continue processing. 57 * The process_* functions which handle individual ITS commands all 58 * return an ItsCmdResult which tells process_cmdq() whether it should 59 * stall or keep going. 60 */ 61 typedef enum ItsCmdResult { 62 CMD_STALL = 0, 63 CMD_CONTINUE = 1, 64 } ItsCmdResult; 65 66 static uint64_t baser_base_addr(uint64_t value, uint32_t page_sz) 67 { 68 uint64_t result = 0; 69 70 switch (page_sz) { 71 case GITS_PAGE_SIZE_4K: 72 case GITS_PAGE_SIZE_16K: 73 result = FIELD_EX64(value, GITS_BASER, PHYADDR) << 12; 74 break; 75 76 case GITS_PAGE_SIZE_64K: 77 result = FIELD_EX64(value, GITS_BASER, PHYADDRL_64K) << 16; 78 result |= FIELD_EX64(value, GITS_BASER, PHYADDRH_64K) << 48; 79 break; 80 81 default: 82 break; 83 } 84 return result; 85 } 86 87 static uint64_t table_entry_addr(GICv3ITSState *s, TableDesc *td, 88 uint32_t idx, MemTxResult *res) 89 { 90 /* 91 * Given a TableDesc describing one of the ITS in-guest-memory 92 * tables and an index into it, return the guest address 93 * corresponding to that table entry. 94 * If there was a memory error reading the L1 table of an 95 * indirect table, *res is set accordingly, and we return -1. 96 * If the L1 table entry is marked not valid, we return -1 with 97 * *res set to MEMTX_OK. 98 * 99 * The specification defines the format of level 1 entries of a 100 * 2-level table, but the format of level 2 entries and the format 101 * of flat-mapped tables is IMPDEF. 102 */ 103 AddressSpace *as = &s->gicv3->dma_as; 104 uint32_t l2idx; 105 uint64_t l2; 106 uint32_t num_l2_entries; 107 108 *res = MEMTX_OK; 109 110 if (!td->indirect) { 111 /* Single level table */ 112 return td->base_addr + idx * td->entry_sz; 113 } 114 115 /* Two level table */ 116 l2idx = idx / (td->page_sz / L1TABLE_ENTRY_SIZE); 117 118 l2 = address_space_ldq_le(as, 119 td->base_addr + (l2idx * L1TABLE_ENTRY_SIZE), 120 MEMTXATTRS_UNSPECIFIED, res); 121 if (*res != MEMTX_OK) { 122 return -1; 123 } 124 if (!(l2 & L2_TABLE_VALID_MASK)) { 125 return -1; 126 } 127 128 num_l2_entries = td->page_sz / td->entry_sz; 129 return (l2 & ((1ULL << 51) - 1)) + (idx % num_l2_entries) * td->entry_sz; 130 } 131 132 static bool get_cte(GICv3ITSState *s, uint16_t icid, uint64_t *cte, 133 MemTxResult *res) 134 { 135 AddressSpace *as = &s->gicv3->dma_as; 136 uint64_t entry_addr = table_entry_addr(s, &s->ct, icid, res); 137 138 if (entry_addr == -1) { 139 return false; /* not valid */ 140 } 141 142 *cte = address_space_ldq_le(as, entry_addr, MEMTXATTRS_UNSPECIFIED, res); 143 return FIELD_EX64(*cte, CTE, VALID); 144 } 145 146 static bool update_ite(GICv3ITSState *s, uint32_t eventid, uint64_t dte, 147 IteEntry ite) 148 { 149 AddressSpace *as = &s->gicv3->dma_as; 150 uint64_t itt_addr; 151 MemTxResult res = MEMTX_OK; 152 153 itt_addr = FIELD_EX64(dte, DTE, ITTADDR); 154 itt_addr <<= ITTADDR_SHIFT; /* 256 byte aligned */ 155 156 address_space_stq_le(as, itt_addr + (eventid * (sizeof(uint64_t) + 157 sizeof(uint32_t))), ite.itel, MEMTXATTRS_UNSPECIFIED, 158 &res); 159 160 if (res == MEMTX_OK) { 161 address_space_stl_le(as, itt_addr + (eventid * (sizeof(uint64_t) + 162 sizeof(uint32_t))) + sizeof(uint32_t), ite.iteh, 163 MEMTXATTRS_UNSPECIFIED, &res); 164 } 165 if (res != MEMTX_OK) { 166 return false; 167 } else { 168 return true; 169 } 170 } 171 172 static bool get_ite(GICv3ITSState *s, uint32_t eventid, uint64_t dte, 173 uint16_t *icid, uint32_t *pIntid, MemTxResult *res) 174 { 175 AddressSpace *as = &s->gicv3->dma_as; 176 uint64_t itt_addr; 177 bool status = false; 178 IteEntry ite = {}; 179 180 itt_addr = FIELD_EX64(dte, DTE, ITTADDR); 181 itt_addr <<= ITTADDR_SHIFT; /* 256 byte aligned */ 182 183 ite.itel = address_space_ldq_le(as, itt_addr + 184 (eventid * (sizeof(uint64_t) + 185 sizeof(uint32_t))), MEMTXATTRS_UNSPECIFIED, 186 res); 187 188 if (*res == MEMTX_OK) { 189 ite.iteh = address_space_ldl_le(as, itt_addr + 190 (eventid * (sizeof(uint64_t) + 191 sizeof(uint32_t))) + sizeof(uint32_t), 192 MEMTXATTRS_UNSPECIFIED, res); 193 194 if (*res == MEMTX_OK) { 195 if (FIELD_EX64(ite.itel, ITE_L, VALID)) { 196 int inttype = FIELD_EX64(ite.itel, ITE_L, INTTYPE); 197 if (inttype == ITE_INTTYPE_PHYSICAL) { 198 *pIntid = FIELD_EX64(ite.itel, ITE_L, INTID); 199 *icid = FIELD_EX32(ite.iteh, ITE_H, ICID); 200 status = true; 201 } 202 } 203 } 204 } 205 return status; 206 } 207 208 static uint64_t get_dte(GICv3ITSState *s, uint32_t devid, MemTxResult *res) 209 { 210 AddressSpace *as = &s->gicv3->dma_as; 211 uint64_t entry_addr = table_entry_addr(s, &s->dt, devid, res); 212 213 if (entry_addr == -1) { 214 return 0; /* a DTE entry with the Valid bit clear */ 215 } 216 return address_space_ldq_le(as, entry_addr, MEMTXATTRS_UNSPECIFIED, res); 217 } 218 219 /* 220 * This function handles the processing of following commands based on 221 * the ItsCmdType parameter passed:- 222 * 1. triggering of lpi interrupt translation via ITS INT command 223 * 2. triggering of lpi interrupt translation via gits_translater register 224 * 3. handling of ITS CLEAR command 225 * 4. handling of ITS DISCARD command 226 */ 227 static ItsCmdResult process_its_cmd(GICv3ITSState *s, uint64_t value, 228 uint32_t offset, ItsCmdType cmd) 229 { 230 AddressSpace *as = &s->gicv3->dma_as; 231 uint32_t devid, eventid; 232 MemTxResult res = MEMTX_OK; 233 bool dte_valid; 234 uint64_t dte = 0; 235 uint64_t num_eventids; 236 uint16_t icid = 0; 237 uint32_t pIntid = 0; 238 bool ite_valid = false; 239 uint64_t cte = 0; 240 bool cte_valid = false; 241 uint64_t rdbase; 242 243 if (cmd == NONE) { 244 devid = offset; 245 } else { 246 devid = ((value & DEVID_MASK) >> DEVID_SHIFT); 247 248 offset += NUM_BYTES_IN_DW; 249 value = address_space_ldq_le(as, s->cq.base_addr + offset, 250 MEMTXATTRS_UNSPECIFIED, &res); 251 } 252 253 if (res != MEMTX_OK) { 254 return CMD_STALL; 255 } 256 257 eventid = (value & EVENTID_MASK); 258 259 if (devid >= s->dt.num_entries) { 260 qemu_log_mask(LOG_GUEST_ERROR, 261 "%s: invalid command attributes: devid %d>=%d", 262 __func__, devid, s->dt.num_entries); 263 return CMD_CONTINUE; 264 } 265 266 dte = get_dte(s, devid, &res); 267 268 if (res != MEMTX_OK) { 269 return CMD_STALL; 270 } 271 dte_valid = FIELD_EX64(dte, DTE, VALID); 272 273 if (!dte_valid) { 274 qemu_log_mask(LOG_GUEST_ERROR, 275 "%s: invalid command attributes: " 276 "invalid dte: %"PRIx64" for %d\n", 277 __func__, dte, devid); 278 return CMD_CONTINUE; 279 } 280 281 num_eventids = 1ULL << (FIELD_EX64(dte, DTE, SIZE) + 1); 282 283 if (eventid >= num_eventids) { 284 qemu_log_mask(LOG_GUEST_ERROR, 285 "%s: invalid command attributes: eventid %d >= %" 286 PRId64 "\n", 287 __func__, eventid, num_eventids); 288 return CMD_CONTINUE; 289 } 290 291 ite_valid = get_ite(s, eventid, dte, &icid, &pIntid, &res); 292 if (res != MEMTX_OK) { 293 return CMD_STALL; 294 } 295 296 if (!ite_valid) { 297 qemu_log_mask(LOG_GUEST_ERROR, 298 "%s: invalid command attributes: invalid ITE\n", 299 __func__); 300 return CMD_CONTINUE; 301 } 302 303 if (icid >= s->ct.num_entries) { 304 qemu_log_mask(LOG_GUEST_ERROR, 305 "%s: invalid ICID 0x%x in ITE (table corrupted?)\n", 306 __func__, icid); 307 return CMD_CONTINUE; 308 } 309 310 cte_valid = get_cte(s, icid, &cte, &res); 311 if (res != MEMTX_OK) { 312 return CMD_STALL; 313 } 314 if (!cte_valid) { 315 qemu_log_mask(LOG_GUEST_ERROR, 316 "%s: invalid command attributes: " 317 "invalid cte: %"PRIx64"\n", 318 __func__, cte); 319 return CMD_CONTINUE; 320 } 321 322 /* 323 * Current implementation only supports rdbase == procnum 324 * Hence rdbase physical address is ignored 325 */ 326 rdbase = FIELD_EX64(cte, CTE, RDBASE); 327 328 if (rdbase >= s->gicv3->num_cpu) { 329 return CMD_CONTINUE; 330 } 331 332 if ((cmd == CLEAR) || (cmd == DISCARD)) { 333 gicv3_redist_process_lpi(&s->gicv3->cpu[rdbase], pIntid, 0); 334 } else { 335 gicv3_redist_process_lpi(&s->gicv3->cpu[rdbase], pIntid, 1); 336 } 337 338 if (cmd == DISCARD) { 339 IteEntry ite = {}; 340 /* remove mapping from interrupt translation table */ 341 return update_ite(s, eventid, dte, ite) ? CMD_CONTINUE : CMD_STALL; 342 } 343 return CMD_CONTINUE; 344 } 345 346 static ItsCmdResult process_mapti(GICv3ITSState *s, uint64_t value, 347 uint32_t offset, bool ignore_pInt) 348 { 349 AddressSpace *as = &s->gicv3->dma_as; 350 uint32_t devid, eventid; 351 uint32_t pIntid = 0; 352 uint64_t num_eventids; 353 uint32_t num_intids; 354 bool dte_valid; 355 MemTxResult res = MEMTX_OK; 356 uint16_t icid = 0; 357 uint64_t dte = 0; 358 IteEntry ite = {}; 359 360 devid = ((value & DEVID_MASK) >> DEVID_SHIFT); 361 offset += NUM_BYTES_IN_DW; 362 value = address_space_ldq_le(as, s->cq.base_addr + offset, 363 MEMTXATTRS_UNSPECIFIED, &res); 364 365 if (res != MEMTX_OK) { 366 return CMD_STALL; 367 } 368 369 eventid = (value & EVENTID_MASK); 370 371 if (ignore_pInt) { 372 pIntid = eventid; 373 } else { 374 pIntid = ((value & pINTID_MASK) >> pINTID_SHIFT); 375 } 376 377 offset += NUM_BYTES_IN_DW; 378 value = address_space_ldq_le(as, s->cq.base_addr + offset, 379 MEMTXATTRS_UNSPECIFIED, &res); 380 381 if (res != MEMTX_OK) { 382 return CMD_STALL; 383 } 384 385 icid = value & ICID_MASK; 386 387 if (devid >= s->dt.num_entries) { 388 qemu_log_mask(LOG_GUEST_ERROR, 389 "%s: invalid command attributes: devid %d>=%d", 390 __func__, devid, s->dt.num_entries); 391 return CMD_CONTINUE; 392 } 393 394 dte = get_dte(s, devid, &res); 395 396 if (res != MEMTX_OK) { 397 return CMD_STALL; 398 } 399 dte_valid = FIELD_EX64(dte, DTE, VALID); 400 num_eventids = 1ULL << (FIELD_EX64(dte, DTE, SIZE) + 1); 401 num_intids = 1ULL << (GICD_TYPER_IDBITS + 1); 402 403 if ((icid >= s->ct.num_entries) 404 || !dte_valid || (eventid >= num_eventids) || 405 (((pIntid < GICV3_LPI_INTID_START) || (pIntid >= num_intids)) && 406 (pIntid != INTID_SPURIOUS))) { 407 qemu_log_mask(LOG_GUEST_ERROR, 408 "%s: invalid command attributes " 409 "icid %d or eventid %d or pIntid %d or" 410 "unmapped dte %d\n", __func__, icid, eventid, 411 pIntid, dte_valid); 412 /* 413 * in this implementation, in case of error 414 * we ignore this command and move onto the next 415 * command in the queue 416 */ 417 return CMD_CONTINUE; 418 } 419 420 /* add ite entry to interrupt translation table */ 421 ite.itel = FIELD_DP64(ite.itel, ITE_L, VALID, dte_valid); 422 ite.itel = FIELD_DP64(ite.itel, ITE_L, INTTYPE, ITE_INTTYPE_PHYSICAL); 423 ite.itel = FIELD_DP64(ite.itel, ITE_L, INTID, pIntid); 424 ite.itel = FIELD_DP64(ite.itel, ITE_L, DOORBELL, INTID_SPURIOUS); 425 ite.iteh = FIELD_DP32(ite.iteh, ITE_H, ICID, icid); 426 427 return update_ite(s, eventid, dte, ite) ? CMD_CONTINUE : CMD_STALL; 428 } 429 430 static bool update_cte(GICv3ITSState *s, uint16_t icid, bool valid, 431 uint64_t rdbase) 432 { 433 AddressSpace *as = &s->gicv3->dma_as; 434 uint64_t entry_addr; 435 uint64_t cte = 0; 436 MemTxResult res = MEMTX_OK; 437 438 if (!s->ct.valid) { 439 return true; 440 } 441 442 if (valid) { 443 /* add mapping entry to collection table */ 444 cte = FIELD_DP64(cte, CTE, VALID, 1); 445 cte = FIELD_DP64(cte, CTE, RDBASE, rdbase); 446 } 447 448 entry_addr = table_entry_addr(s, &s->ct, icid, &res); 449 if (res != MEMTX_OK) { 450 /* memory access error: stall */ 451 return false; 452 } 453 if (entry_addr == -1) { 454 /* No L2 table for this index: discard write and continue */ 455 return true; 456 } 457 458 address_space_stq_le(as, entry_addr, cte, MEMTXATTRS_UNSPECIFIED, &res); 459 return res == MEMTX_OK; 460 } 461 462 static ItsCmdResult process_mapc(GICv3ITSState *s, uint32_t offset) 463 { 464 AddressSpace *as = &s->gicv3->dma_as; 465 uint16_t icid; 466 uint64_t rdbase; 467 bool valid; 468 MemTxResult res = MEMTX_OK; 469 uint64_t value; 470 471 offset += NUM_BYTES_IN_DW; 472 offset += NUM_BYTES_IN_DW; 473 474 value = address_space_ldq_le(as, s->cq.base_addr + offset, 475 MEMTXATTRS_UNSPECIFIED, &res); 476 477 if (res != MEMTX_OK) { 478 return CMD_STALL; 479 } 480 481 icid = value & ICID_MASK; 482 483 rdbase = (value & R_MAPC_RDBASE_MASK) >> R_MAPC_RDBASE_SHIFT; 484 rdbase &= RDBASE_PROCNUM_MASK; 485 486 valid = (value & CMD_FIELD_VALID_MASK); 487 488 if ((icid >= s->ct.num_entries) || (rdbase >= s->gicv3->num_cpu)) { 489 qemu_log_mask(LOG_GUEST_ERROR, 490 "ITS MAPC: invalid collection table attributes " 491 "icid %d rdbase %" PRIu64 "\n", icid, rdbase); 492 /* 493 * in this implementation, in case of error 494 * we ignore this command and move onto the next 495 * command in the queue 496 */ 497 return CMD_CONTINUE; 498 } 499 500 return update_cte(s, icid, valid, rdbase) ? CMD_CONTINUE : CMD_STALL; 501 } 502 503 static bool update_dte(GICv3ITSState *s, uint32_t devid, bool valid, 504 uint8_t size, uint64_t itt_addr) 505 { 506 AddressSpace *as = &s->gicv3->dma_as; 507 uint64_t entry_addr; 508 uint64_t dte = 0; 509 MemTxResult res = MEMTX_OK; 510 511 if (s->dt.valid) { 512 if (valid) { 513 /* add mapping entry to device table */ 514 dte = FIELD_DP64(dte, DTE, VALID, 1); 515 dte = FIELD_DP64(dte, DTE, SIZE, size); 516 dte = FIELD_DP64(dte, DTE, ITTADDR, itt_addr); 517 } 518 } else { 519 return true; 520 } 521 522 entry_addr = table_entry_addr(s, &s->dt, devid, &res); 523 if (res != MEMTX_OK) { 524 /* memory access error: stall */ 525 return false; 526 } 527 if (entry_addr == -1) { 528 /* No L2 table for this index: discard write and continue */ 529 return true; 530 } 531 address_space_stq_le(as, entry_addr, dte, MEMTXATTRS_UNSPECIFIED, &res); 532 return res == MEMTX_OK; 533 } 534 535 static ItsCmdResult process_mapd(GICv3ITSState *s, uint64_t value, 536 uint32_t offset) 537 { 538 AddressSpace *as = &s->gicv3->dma_as; 539 uint32_t devid; 540 uint8_t size; 541 uint64_t itt_addr; 542 bool valid; 543 MemTxResult res = MEMTX_OK; 544 545 devid = ((value & DEVID_MASK) >> DEVID_SHIFT); 546 547 offset += NUM_BYTES_IN_DW; 548 value = address_space_ldq_le(as, s->cq.base_addr + offset, 549 MEMTXATTRS_UNSPECIFIED, &res); 550 551 if (res != MEMTX_OK) { 552 return CMD_STALL; 553 } 554 555 size = (value & SIZE_MASK); 556 557 offset += NUM_BYTES_IN_DW; 558 value = address_space_ldq_le(as, s->cq.base_addr + offset, 559 MEMTXATTRS_UNSPECIFIED, &res); 560 561 if (res != MEMTX_OK) { 562 return CMD_STALL; 563 } 564 565 itt_addr = (value & ITTADDR_MASK) >> ITTADDR_SHIFT; 566 567 valid = (value & CMD_FIELD_VALID_MASK); 568 569 if ((devid >= s->dt.num_entries) || 570 (size > FIELD_EX64(s->typer, GITS_TYPER, IDBITS))) { 571 qemu_log_mask(LOG_GUEST_ERROR, 572 "ITS MAPD: invalid device table attributes " 573 "devid %d or size %d\n", devid, size); 574 /* 575 * in this implementation, in case of error 576 * we ignore this command and move onto the next 577 * command in the queue 578 */ 579 return CMD_CONTINUE; 580 } 581 582 return update_dte(s, devid, valid, size, itt_addr) ? CMD_CONTINUE : CMD_STALL; 583 } 584 585 static ItsCmdResult process_movall(GICv3ITSState *s, uint64_t value, 586 uint32_t offset) 587 { 588 AddressSpace *as = &s->gicv3->dma_as; 589 MemTxResult res = MEMTX_OK; 590 uint64_t rd1, rd2; 591 592 /* No fields in dwords 0 or 1 */ 593 offset += NUM_BYTES_IN_DW; 594 offset += NUM_BYTES_IN_DW; 595 value = address_space_ldq_le(as, s->cq.base_addr + offset, 596 MEMTXATTRS_UNSPECIFIED, &res); 597 if (res != MEMTX_OK) { 598 return CMD_STALL; 599 } 600 601 rd1 = FIELD_EX64(value, MOVALL_2, RDBASE1); 602 if (rd1 >= s->gicv3->num_cpu) { 603 qemu_log_mask(LOG_GUEST_ERROR, 604 "%s: RDBASE1 %" PRId64 605 " out of range (must be less than %d)\n", 606 __func__, rd1, s->gicv3->num_cpu); 607 return CMD_CONTINUE; 608 } 609 610 offset += NUM_BYTES_IN_DW; 611 value = address_space_ldq_le(as, s->cq.base_addr + offset, 612 MEMTXATTRS_UNSPECIFIED, &res); 613 if (res != MEMTX_OK) { 614 return CMD_STALL; 615 } 616 617 rd2 = FIELD_EX64(value, MOVALL_3, RDBASE2); 618 if (rd2 >= s->gicv3->num_cpu) { 619 qemu_log_mask(LOG_GUEST_ERROR, 620 "%s: RDBASE2 %" PRId64 621 " out of range (must be less than %d)\n", 622 __func__, rd2, s->gicv3->num_cpu); 623 return CMD_CONTINUE; 624 } 625 626 if (rd1 == rd2) { 627 /* Move to same target must succeed as a no-op */ 628 return CMD_CONTINUE; 629 } 630 631 /* Move all pending LPIs from redistributor 1 to redistributor 2 */ 632 gicv3_redist_movall_lpis(&s->gicv3->cpu[rd1], &s->gicv3->cpu[rd2]); 633 634 return CMD_CONTINUE; 635 } 636 637 /* 638 * Current implementation blocks until all 639 * commands are processed 640 */ 641 static void process_cmdq(GICv3ITSState *s) 642 { 643 uint32_t wr_offset = 0; 644 uint32_t rd_offset = 0; 645 uint32_t cq_offset = 0; 646 uint64_t data; 647 AddressSpace *as = &s->gicv3->dma_as; 648 MemTxResult res = MEMTX_OK; 649 uint8_t cmd; 650 int i; 651 652 if (!(s->ctlr & R_GITS_CTLR_ENABLED_MASK)) { 653 return; 654 } 655 656 wr_offset = FIELD_EX64(s->cwriter, GITS_CWRITER, OFFSET); 657 658 if (wr_offset >= s->cq.num_entries) { 659 qemu_log_mask(LOG_GUEST_ERROR, 660 "%s: invalid write offset " 661 "%d\n", __func__, wr_offset); 662 return; 663 } 664 665 rd_offset = FIELD_EX64(s->creadr, GITS_CREADR, OFFSET); 666 667 if (rd_offset >= s->cq.num_entries) { 668 qemu_log_mask(LOG_GUEST_ERROR, 669 "%s: invalid read offset " 670 "%d\n", __func__, rd_offset); 671 return; 672 } 673 674 while (wr_offset != rd_offset) { 675 ItsCmdResult result = CMD_CONTINUE; 676 677 cq_offset = (rd_offset * GITS_CMDQ_ENTRY_SIZE); 678 data = address_space_ldq_le(as, s->cq.base_addr + cq_offset, 679 MEMTXATTRS_UNSPECIFIED, &res); 680 if (res != MEMTX_OK) { 681 s->creadr = FIELD_DP64(s->creadr, GITS_CREADR, STALLED, 1); 682 qemu_log_mask(LOG_GUEST_ERROR, 683 "%s: could not read command at 0x%" PRIx64 "\n", 684 __func__, s->cq.base_addr + cq_offset); 685 break; 686 } 687 688 cmd = (data & CMD_MASK); 689 690 trace_gicv3_its_process_command(rd_offset, cmd); 691 692 switch (cmd) { 693 case GITS_CMD_INT: 694 result = process_its_cmd(s, data, cq_offset, INTERRUPT); 695 break; 696 case GITS_CMD_CLEAR: 697 result = process_its_cmd(s, data, cq_offset, CLEAR); 698 break; 699 case GITS_CMD_SYNC: 700 /* 701 * Current implementation makes a blocking synchronous call 702 * for every command issued earlier, hence the internal state 703 * is already consistent by the time SYNC command is executed. 704 * Hence no further processing is required for SYNC command. 705 */ 706 break; 707 case GITS_CMD_MAPD: 708 result = process_mapd(s, data, cq_offset); 709 break; 710 case GITS_CMD_MAPC: 711 result = process_mapc(s, cq_offset); 712 break; 713 case GITS_CMD_MAPTI: 714 result = process_mapti(s, data, cq_offset, false); 715 break; 716 case GITS_CMD_MAPI: 717 result = process_mapti(s, data, cq_offset, true); 718 break; 719 case GITS_CMD_DISCARD: 720 result = process_its_cmd(s, data, cq_offset, DISCARD); 721 break; 722 case GITS_CMD_INV: 723 case GITS_CMD_INVALL: 724 /* 725 * Current implementation doesn't cache any ITS tables, 726 * but the calculated lpi priority information. We only 727 * need to trigger lpi priority re-calculation to be in 728 * sync with LPI config table or pending table changes. 729 */ 730 for (i = 0; i < s->gicv3->num_cpu; i++) { 731 gicv3_redist_update_lpi(&s->gicv3->cpu[i]); 732 } 733 break; 734 case GITS_CMD_MOVALL: 735 result = process_movall(s, data, cq_offset); 736 break; 737 default: 738 break; 739 } 740 if (result == CMD_CONTINUE) { 741 rd_offset++; 742 rd_offset %= s->cq.num_entries; 743 s->creadr = FIELD_DP64(s->creadr, GITS_CREADR, OFFSET, rd_offset); 744 } else { 745 /* CMD_STALL */ 746 s->creadr = FIELD_DP64(s->creadr, GITS_CREADR, STALLED, 1); 747 qemu_log_mask(LOG_GUEST_ERROR, 748 "%s: 0x%x cmd processing failed, stalling\n", 749 __func__, cmd); 750 break; 751 } 752 } 753 } 754 755 /* 756 * This function extracts the ITS Device and Collection table specific 757 * parameters (like base_addr, size etc) from GITS_BASER register. 758 * It is called during ITS enable and also during post_load migration 759 */ 760 static void extract_table_params(GICv3ITSState *s) 761 { 762 uint16_t num_pages = 0; 763 uint8_t page_sz_type; 764 uint8_t type; 765 uint32_t page_sz = 0; 766 uint64_t value; 767 768 for (int i = 0; i < 8; i++) { 769 TableDesc *td; 770 int idbits; 771 772 value = s->baser[i]; 773 774 if (!value) { 775 continue; 776 } 777 778 page_sz_type = FIELD_EX64(value, GITS_BASER, PAGESIZE); 779 780 switch (page_sz_type) { 781 case 0: 782 page_sz = GITS_PAGE_SIZE_4K; 783 break; 784 785 case 1: 786 page_sz = GITS_PAGE_SIZE_16K; 787 break; 788 789 case 2: 790 case 3: 791 page_sz = GITS_PAGE_SIZE_64K; 792 break; 793 794 default: 795 g_assert_not_reached(); 796 } 797 798 num_pages = FIELD_EX64(value, GITS_BASER, SIZE) + 1; 799 800 type = FIELD_EX64(value, GITS_BASER, TYPE); 801 802 switch (type) { 803 case GITS_BASER_TYPE_DEVICE: 804 td = &s->dt; 805 idbits = FIELD_EX64(s->typer, GITS_TYPER, DEVBITS) + 1; 806 break; 807 case GITS_BASER_TYPE_COLLECTION: 808 td = &s->ct; 809 if (FIELD_EX64(s->typer, GITS_TYPER, CIL)) { 810 idbits = FIELD_EX64(s->typer, GITS_TYPER, CIDBITS) + 1; 811 } else { 812 /* 16-bit CollectionId supported when CIL == 0 */ 813 idbits = 16; 814 } 815 break; 816 default: 817 /* 818 * GITS_BASER<n>.TYPE is read-only, so GITS_BASER_RO_MASK 819 * ensures we will only see type values corresponding to 820 * the values set up in gicv3_its_reset(). 821 */ 822 g_assert_not_reached(); 823 } 824 825 memset(td, 0, sizeof(*td)); 826 td->valid = FIELD_EX64(value, GITS_BASER, VALID); 827 /* 828 * If GITS_BASER<n>.Valid is 0 for any <n> then we will not process 829 * interrupts. (GITS_TYPER.HCC is 0 for this implementation, so we 830 * do not have a special case where the GITS_BASER<n>.Valid bit is 0 831 * for the register corresponding to the Collection table but we 832 * still have to process interrupts using non-memory-backed 833 * Collection table entries.) 834 */ 835 if (!td->valid) { 836 continue; 837 } 838 td->page_sz = page_sz; 839 td->indirect = FIELD_EX64(value, GITS_BASER, INDIRECT); 840 td->entry_sz = FIELD_EX64(value, GITS_BASER, ENTRYSIZE) + 1; 841 td->base_addr = baser_base_addr(value, page_sz); 842 if (!td->indirect) { 843 td->num_entries = (num_pages * page_sz) / td->entry_sz; 844 } else { 845 td->num_entries = (((num_pages * page_sz) / 846 L1TABLE_ENTRY_SIZE) * 847 (page_sz / td->entry_sz)); 848 } 849 td->num_entries = MIN(td->num_entries, 1ULL << idbits); 850 } 851 } 852 853 static void extract_cmdq_params(GICv3ITSState *s) 854 { 855 uint16_t num_pages = 0; 856 uint64_t value = s->cbaser; 857 858 num_pages = FIELD_EX64(value, GITS_CBASER, SIZE) + 1; 859 860 memset(&s->cq, 0 , sizeof(s->cq)); 861 s->cq.valid = FIELD_EX64(value, GITS_CBASER, VALID); 862 863 if (s->cq.valid) { 864 s->cq.num_entries = (num_pages * GITS_PAGE_SIZE_4K) / 865 GITS_CMDQ_ENTRY_SIZE; 866 s->cq.base_addr = FIELD_EX64(value, GITS_CBASER, PHYADDR); 867 s->cq.base_addr <<= R_GITS_CBASER_PHYADDR_SHIFT; 868 } 869 } 870 871 static MemTxResult gicv3_its_translation_read(void *opaque, hwaddr offset, 872 uint64_t *data, unsigned size, 873 MemTxAttrs attrs) 874 { 875 /* 876 * GITS_TRANSLATER is write-only, and all other addresses 877 * in the interrupt translation space frame are RES0. 878 */ 879 *data = 0; 880 return MEMTX_OK; 881 } 882 883 static MemTxResult gicv3_its_translation_write(void *opaque, hwaddr offset, 884 uint64_t data, unsigned size, 885 MemTxAttrs attrs) 886 { 887 GICv3ITSState *s = (GICv3ITSState *)opaque; 888 bool result = true; 889 uint32_t devid = 0; 890 891 trace_gicv3_its_translation_write(offset, data, size, attrs.requester_id); 892 893 switch (offset) { 894 case GITS_TRANSLATER: 895 if (s->ctlr & R_GITS_CTLR_ENABLED_MASK) { 896 devid = attrs.requester_id; 897 result = process_its_cmd(s, data, devid, NONE); 898 } 899 break; 900 default: 901 break; 902 } 903 904 if (result) { 905 return MEMTX_OK; 906 } else { 907 return MEMTX_ERROR; 908 } 909 } 910 911 static bool its_writel(GICv3ITSState *s, hwaddr offset, 912 uint64_t value, MemTxAttrs attrs) 913 { 914 bool result = true; 915 int index; 916 917 switch (offset) { 918 case GITS_CTLR: 919 if (value & R_GITS_CTLR_ENABLED_MASK) { 920 s->ctlr |= R_GITS_CTLR_ENABLED_MASK; 921 extract_table_params(s); 922 extract_cmdq_params(s); 923 process_cmdq(s); 924 } else { 925 s->ctlr &= ~R_GITS_CTLR_ENABLED_MASK; 926 } 927 break; 928 case GITS_CBASER: 929 /* 930 * IMPDEF choice:- GITS_CBASER register becomes RO if ITS is 931 * already enabled 932 */ 933 if (!(s->ctlr & R_GITS_CTLR_ENABLED_MASK)) { 934 s->cbaser = deposit64(s->cbaser, 0, 32, value); 935 s->creadr = 0; 936 } 937 break; 938 case GITS_CBASER + 4: 939 /* 940 * IMPDEF choice:- GITS_CBASER register becomes RO if ITS is 941 * already enabled 942 */ 943 if (!(s->ctlr & R_GITS_CTLR_ENABLED_MASK)) { 944 s->cbaser = deposit64(s->cbaser, 32, 32, value); 945 s->creadr = 0; 946 } 947 break; 948 case GITS_CWRITER: 949 s->cwriter = deposit64(s->cwriter, 0, 32, 950 (value & ~R_GITS_CWRITER_RETRY_MASK)); 951 if (s->cwriter != s->creadr) { 952 process_cmdq(s); 953 } 954 break; 955 case GITS_CWRITER + 4: 956 s->cwriter = deposit64(s->cwriter, 32, 32, value); 957 break; 958 case GITS_CREADR: 959 if (s->gicv3->gicd_ctlr & GICD_CTLR_DS) { 960 s->creadr = deposit64(s->creadr, 0, 32, 961 (value & ~R_GITS_CREADR_STALLED_MASK)); 962 } else { 963 /* RO register, ignore the write */ 964 qemu_log_mask(LOG_GUEST_ERROR, 965 "%s: invalid guest write to RO register at offset " 966 TARGET_FMT_plx "\n", __func__, offset); 967 } 968 break; 969 case GITS_CREADR + 4: 970 if (s->gicv3->gicd_ctlr & GICD_CTLR_DS) { 971 s->creadr = deposit64(s->creadr, 32, 32, value); 972 } else { 973 /* RO register, ignore the write */ 974 qemu_log_mask(LOG_GUEST_ERROR, 975 "%s: invalid guest write to RO register at offset " 976 TARGET_FMT_plx "\n", __func__, offset); 977 } 978 break; 979 case GITS_BASER ... GITS_BASER + 0x3f: 980 /* 981 * IMPDEF choice:- GITS_BASERn register becomes RO if ITS is 982 * already enabled 983 */ 984 if (!(s->ctlr & R_GITS_CTLR_ENABLED_MASK)) { 985 index = (offset - GITS_BASER) / 8; 986 987 if (s->baser[index] == 0) { 988 /* Unimplemented GITS_BASERn: RAZ/WI */ 989 break; 990 } 991 if (offset & 7) { 992 value <<= 32; 993 value &= ~GITS_BASER_RO_MASK; 994 s->baser[index] &= GITS_BASER_RO_MASK | MAKE_64BIT_MASK(0, 32); 995 s->baser[index] |= value; 996 } else { 997 value &= ~GITS_BASER_RO_MASK; 998 s->baser[index] &= GITS_BASER_RO_MASK | MAKE_64BIT_MASK(32, 32); 999 s->baser[index] |= value; 1000 } 1001 } 1002 break; 1003 case GITS_IIDR: 1004 case GITS_IDREGS ... GITS_IDREGS + 0x2f: 1005 /* RO registers, ignore the write */ 1006 qemu_log_mask(LOG_GUEST_ERROR, 1007 "%s: invalid guest write to RO register at offset " 1008 TARGET_FMT_plx "\n", __func__, offset); 1009 break; 1010 default: 1011 result = false; 1012 break; 1013 } 1014 return result; 1015 } 1016 1017 static bool its_readl(GICv3ITSState *s, hwaddr offset, 1018 uint64_t *data, MemTxAttrs attrs) 1019 { 1020 bool result = true; 1021 int index; 1022 1023 switch (offset) { 1024 case GITS_CTLR: 1025 *data = s->ctlr; 1026 break; 1027 case GITS_IIDR: 1028 *data = gicv3_iidr(); 1029 break; 1030 case GITS_IDREGS ... GITS_IDREGS + 0x2f: 1031 /* ID registers */ 1032 *data = gicv3_idreg(offset - GITS_IDREGS); 1033 break; 1034 case GITS_TYPER: 1035 *data = extract64(s->typer, 0, 32); 1036 break; 1037 case GITS_TYPER + 4: 1038 *data = extract64(s->typer, 32, 32); 1039 break; 1040 case GITS_CBASER: 1041 *data = extract64(s->cbaser, 0, 32); 1042 break; 1043 case GITS_CBASER + 4: 1044 *data = extract64(s->cbaser, 32, 32); 1045 break; 1046 case GITS_CREADR: 1047 *data = extract64(s->creadr, 0, 32); 1048 break; 1049 case GITS_CREADR + 4: 1050 *data = extract64(s->creadr, 32, 32); 1051 break; 1052 case GITS_CWRITER: 1053 *data = extract64(s->cwriter, 0, 32); 1054 break; 1055 case GITS_CWRITER + 4: 1056 *data = extract64(s->cwriter, 32, 32); 1057 break; 1058 case GITS_BASER ... GITS_BASER + 0x3f: 1059 index = (offset - GITS_BASER) / 8; 1060 if (offset & 7) { 1061 *data = extract64(s->baser[index], 32, 32); 1062 } else { 1063 *data = extract64(s->baser[index], 0, 32); 1064 } 1065 break; 1066 default: 1067 result = false; 1068 break; 1069 } 1070 return result; 1071 } 1072 1073 static bool its_writell(GICv3ITSState *s, hwaddr offset, 1074 uint64_t value, MemTxAttrs attrs) 1075 { 1076 bool result = true; 1077 int index; 1078 1079 switch (offset) { 1080 case GITS_BASER ... GITS_BASER + 0x3f: 1081 /* 1082 * IMPDEF choice:- GITS_BASERn register becomes RO if ITS is 1083 * already enabled 1084 */ 1085 if (!(s->ctlr & R_GITS_CTLR_ENABLED_MASK)) { 1086 index = (offset - GITS_BASER) / 8; 1087 if (s->baser[index] == 0) { 1088 /* Unimplemented GITS_BASERn: RAZ/WI */ 1089 break; 1090 } 1091 s->baser[index] &= GITS_BASER_RO_MASK; 1092 s->baser[index] |= (value & ~GITS_BASER_RO_MASK); 1093 } 1094 break; 1095 case GITS_CBASER: 1096 /* 1097 * IMPDEF choice:- GITS_CBASER register becomes RO if ITS is 1098 * already enabled 1099 */ 1100 if (!(s->ctlr & R_GITS_CTLR_ENABLED_MASK)) { 1101 s->cbaser = value; 1102 s->creadr = 0; 1103 } 1104 break; 1105 case GITS_CWRITER: 1106 s->cwriter = value & ~R_GITS_CWRITER_RETRY_MASK; 1107 if (s->cwriter != s->creadr) { 1108 process_cmdq(s); 1109 } 1110 break; 1111 case GITS_CREADR: 1112 if (s->gicv3->gicd_ctlr & GICD_CTLR_DS) { 1113 s->creadr = value & ~R_GITS_CREADR_STALLED_MASK; 1114 } else { 1115 /* RO register, ignore the write */ 1116 qemu_log_mask(LOG_GUEST_ERROR, 1117 "%s: invalid guest write to RO register at offset " 1118 TARGET_FMT_plx "\n", __func__, offset); 1119 } 1120 break; 1121 case GITS_TYPER: 1122 /* RO registers, ignore the write */ 1123 qemu_log_mask(LOG_GUEST_ERROR, 1124 "%s: invalid guest write to RO register at offset " 1125 TARGET_FMT_plx "\n", __func__, offset); 1126 break; 1127 default: 1128 result = false; 1129 break; 1130 } 1131 return result; 1132 } 1133 1134 static bool its_readll(GICv3ITSState *s, hwaddr offset, 1135 uint64_t *data, MemTxAttrs attrs) 1136 { 1137 bool result = true; 1138 int index; 1139 1140 switch (offset) { 1141 case GITS_TYPER: 1142 *data = s->typer; 1143 break; 1144 case GITS_BASER ... GITS_BASER + 0x3f: 1145 index = (offset - GITS_BASER) / 8; 1146 *data = s->baser[index]; 1147 break; 1148 case GITS_CBASER: 1149 *data = s->cbaser; 1150 break; 1151 case GITS_CREADR: 1152 *data = s->creadr; 1153 break; 1154 case GITS_CWRITER: 1155 *data = s->cwriter; 1156 break; 1157 default: 1158 result = false; 1159 break; 1160 } 1161 return result; 1162 } 1163 1164 static MemTxResult gicv3_its_read(void *opaque, hwaddr offset, uint64_t *data, 1165 unsigned size, MemTxAttrs attrs) 1166 { 1167 GICv3ITSState *s = (GICv3ITSState *)opaque; 1168 bool result; 1169 1170 switch (size) { 1171 case 4: 1172 result = its_readl(s, offset, data, attrs); 1173 break; 1174 case 8: 1175 result = its_readll(s, offset, data, attrs); 1176 break; 1177 default: 1178 result = false; 1179 break; 1180 } 1181 1182 if (!result) { 1183 qemu_log_mask(LOG_GUEST_ERROR, 1184 "%s: invalid guest read at offset " TARGET_FMT_plx 1185 "size %u\n", __func__, offset, size); 1186 trace_gicv3_its_badread(offset, size); 1187 /* 1188 * The spec requires that reserved registers are RAZ/WI; 1189 * so use false returns from leaf functions as a way to 1190 * trigger the guest-error logging but don't return it to 1191 * the caller, or we'll cause a spurious guest data abort. 1192 */ 1193 *data = 0; 1194 } else { 1195 trace_gicv3_its_read(offset, *data, size); 1196 } 1197 return MEMTX_OK; 1198 } 1199 1200 static MemTxResult gicv3_its_write(void *opaque, hwaddr offset, uint64_t data, 1201 unsigned size, MemTxAttrs attrs) 1202 { 1203 GICv3ITSState *s = (GICv3ITSState *)opaque; 1204 bool result; 1205 1206 switch (size) { 1207 case 4: 1208 result = its_writel(s, offset, data, attrs); 1209 break; 1210 case 8: 1211 result = its_writell(s, offset, data, attrs); 1212 break; 1213 default: 1214 result = false; 1215 break; 1216 } 1217 1218 if (!result) { 1219 qemu_log_mask(LOG_GUEST_ERROR, 1220 "%s: invalid guest write at offset " TARGET_FMT_plx 1221 "size %u\n", __func__, offset, size); 1222 trace_gicv3_its_badwrite(offset, data, size); 1223 /* 1224 * The spec requires that reserved registers are RAZ/WI; 1225 * so use false returns from leaf functions as a way to 1226 * trigger the guest-error logging but don't return it to 1227 * the caller, or we'll cause a spurious guest data abort. 1228 */ 1229 } else { 1230 trace_gicv3_its_write(offset, data, size); 1231 } 1232 return MEMTX_OK; 1233 } 1234 1235 static const MemoryRegionOps gicv3_its_control_ops = { 1236 .read_with_attrs = gicv3_its_read, 1237 .write_with_attrs = gicv3_its_write, 1238 .valid.min_access_size = 4, 1239 .valid.max_access_size = 8, 1240 .impl.min_access_size = 4, 1241 .impl.max_access_size = 8, 1242 .endianness = DEVICE_NATIVE_ENDIAN, 1243 }; 1244 1245 static const MemoryRegionOps gicv3_its_translation_ops = { 1246 .read_with_attrs = gicv3_its_translation_read, 1247 .write_with_attrs = gicv3_its_translation_write, 1248 .valid.min_access_size = 2, 1249 .valid.max_access_size = 4, 1250 .impl.min_access_size = 2, 1251 .impl.max_access_size = 4, 1252 .endianness = DEVICE_NATIVE_ENDIAN, 1253 }; 1254 1255 static void gicv3_arm_its_realize(DeviceState *dev, Error **errp) 1256 { 1257 GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev); 1258 int i; 1259 1260 for (i = 0; i < s->gicv3->num_cpu; i++) { 1261 if (!(s->gicv3->cpu[i].gicr_typer & GICR_TYPER_PLPIS)) { 1262 error_setg(errp, "Physical LPI not supported by CPU %d", i); 1263 return; 1264 } 1265 } 1266 1267 gicv3_its_init_mmio(s, &gicv3_its_control_ops, &gicv3_its_translation_ops); 1268 1269 /* set the ITS default features supported */ 1270 s->typer = FIELD_DP64(s->typer, GITS_TYPER, PHYSICAL, 1); 1271 s->typer = FIELD_DP64(s->typer, GITS_TYPER, ITT_ENTRY_SIZE, 1272 ITS_ITT_ENTRY_SIZE - 1); 1273 s->typer = FIELD_DP64(s->typer, GITS_TYPER, IDBITS, ITS_IDBITS); 1274 s->typer = FIELD_DP64(s->typer, GITS_TYPER, DEVBITS, ITS_DEVBITS); 1275 s->typer = FIELD_DP64(s->typer, GITS_TYPER, CIL, 1); 1276 s->typer = FIELD_DP64(s->typer, GITS_TYPER, CIDBITS, ITS_CIDBITS); 1277 } 1278 1279 static void gicv3_its_reset(DeviceState *dev) 1280 { 1281 GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev); 1282 GICv3ITSClass *c = ARM_GICV3_ITS_GET_CLASS(s); 1283 1284 c->parent_reset(dev); 1285 1286 /* Quiescent bit reset to 1 */ 1287 s->ctlr = FIELD_DP32(s->ctlr, GITS_CTLR, QUIESCENT, 1); 1288 1289 /* 1290 * setting GITS_BASER0.Type = 0b001 (Device) 1291 * GITS_BASER1.Type = 0b100 (Collection Table) 1292 * GITS_BASER<n>.Type,where n = 3 to 7 are 0b00 (Unimplemented) 1293 * GITS_BASER<0,1>.Page_Size = 64KB 1294 * and default translation table entry size to 16 bytes 1295 */ 1296 s->baser[0] = FIELD_DP64(s->baser[0], GITS_BASER, TYPE, 1297 GITS_BASER_TYPE_DEVICE); 1298 s->baser[0] = FIELD_DP64(s->baser[0], GITS_BASER, PAGESIZE, 1299 GITS_BASER_PAGESIZE_64K); 1300 s->baser[0] = FIELD_DP64(s->baser[0], GITS_BASER, ENTRYSIZE, 1301 GITS_DTE_SIZE - 1); 1302 1303 s->baser[1] = FIELD_DP64(s->baser[1], GITS_BASER, TYPE, 1304 GITS_BASER_TYPE_COLLECTION); 1305 s->baser[1] = FIELD_DP64(s->baser[1], GITS_BASER, PAGESIZE, 1306 GITS_BASER_PAGESIZE_64K); 1307 s->baser[1] = FIELD_DP64(s->baser[1], GITS_BASER, ENTRYSIZE, 1308 GITS_CTE_SIZE - 1); 1309 } 1310 1311 static void gicv3_its_post_load(GICv3ITSState *s) 1312 { 1313 if (s->ctlr & R_GITS_CTLR_ENABLED_MASK) { 1314 extract_table_params(s); 1315 extract_cmdq_params(s); 1316 } 1317 } 1318 1319 static Property gicv3_its_props[] = { 1320 DEFINE_PROP_LINK("parent-gicv3", GICv3ITSState, gicv3, "arm-gicv3", 1321 GICv3State *), 1322 DEFINE_PROP_END_OF_LIST(), 1323 }; 1324 1325 static void gicv3_its_class_init(ObjectClass *klass, void *data) 1326 { 1327 DeviceClass *dc = DEVICE_CLASS(klass); 1328 GICv3ITSClass *ic = ARM_GICV3_ITS_CLASS(klass); 1329 GICv3ITSCommonClass *icc = ARM_GICV3_ITS_COMMON_CLASS(klass); 1330 1331 dc->realize = gicv3_arm_its_realize; 1332 device_class_set_props(dc, gicv3_its_props); 1333 device_class_set_parent_reset(dc, gicv3_its_reset, &ic->parent_reset); 1334 icc->post_load = gicv3_its_post_load; 1335 } 1336 1337 static const TypeInfo gicv3_its_info = { 1338 .name = TYPE_ARM_GICV3_ITS, 1339 .parent = TYPE_ARM_GICV3_ITS_COMMON, 1340 .instance_size = sizeof(GICv3ITSState), 1341 .class_init = gicv3_its_class_init, 1342 .class_size = sizeof(GICv3ITSClass), 1343 }; 1344 1345 static void gicv3_its_register_types(void) 1346 { 1347 type_register_static(&gicv3_its_info); 1348 } 1349 1350 type_init(gicv3_its_register_types) 1351