1 /* 2 * ITS emulation for a GICv3-based system 3 * 4 * Copyright Linaro.org 2021 5 * 6 * Authors: 7 * Shashi Mallela <shashi.mallela@linaro.org> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or (at your 10 * option) any later version. See the COPYING file in the top-level directory. 11 * 12 */ 13 14 #include "qemu/osdep.h" 15 #include "qemu/log.h" 16 #include "hw/qdev-properties.h" 17 #include "hw/intc/arm_gicv3_its_common.h" 18 #include "gicv3_internal.h" 19 #include "qom/object.h" 20 #include "qapi/error.h" 21 22 typedef struct GICv3ITSClass GICv3ITSClass; 23 /* This is reusing the GICv3ITSState typedef from ARM_GICV3_ITS_COMMON */ 24 DECLARE_OBJ_CHECKERS(GICv3ITSState, GICv3ITSClass, 25 ARM_GICV3_ITS, TYPE_ARM_GICV3_ITS) 26 27 struct GICv3ITSClass { 28 GICv3ITSCommonClass parent_class; 29 void (*parent_reset)(DeviceState *dev); 30 }; 31 32 /* 33 * This is an internal enum used to distinguish between LPI triggered 34 * via command queue and LPI triggered via gits_translater write. 35 */ 36 typedef enum ItsCmdType { 37 NONE = 0, /* internal indication for GITS_TRANSLATER write */ 38 CLEAR = 1, 39 DISCARD = 2, 40 INTERRUPT = 3, 41 } ItsCmdType; 42 43 typedef struct { 44 uint32_t iteh; 45 uint64_t itel; 46 } IteEntry; 47 48 /* 49 * The ITS spec permits a range of CONSTRAINED UNPREDICTABLE options 50 * if a command parameter is not correct. These include both "stall 51 * processing of the command queue" and "ignore this command, and 52 * keep processing the queue". In our implementation we choose that 53 * memory transaction errors reading the command packet provoke a 54 * stall, but errors in parameters cause us to ignore the command 55 * and continue processing. 56 * The process_* functions which handle individual ITS commands all 57 * return an ItsCmdResult which tells process_cmdq() whether it should 58 * stall or keep going. 59 */ 60 typedef enum ItsCmdResult { 61 CMD_STALL = 0, 62 CMD_CONTINUE = 1, 63 } ItsCmdResult; 64 65 static uint64_t baser_base_addr(uint64_t value, uint32_t page_sz) 66 { 67 uint64_t result = 0; 68 69 switch (page_sz) { 70 case GITS_PAGE_SIZE_4K: 71 case GITS_PAGE_SIZE_16K: 72 result = FIELD_EX64(value, GITS_BASER, PHYADDR) << 12; 73 break; 74 75 case GITS_PAGE_SIZE_64K: 76 result = FIELD_EX64(value, GITS_BASER, PHYADDRL_64K) << 16; 77 result |= FIELD_EX64(value, GITS_BASER, PHYADDRH_64K) << 48; 78 break; 79 80 default: 81 break; 82 } 83 return result; 84 } 85 86 static bool get_cte(GICv3ITSState *s, uint16_t icid, uint64_t *cte, 87 MemTxResult *res) 88 { 89 AddressSpace *as = &s->gicv3->dma_as; 90 uint64_t l2t_addr; 91 uint64_t value; 92 bool valid_l2t; 93 uint32_t l2t_id; 94 uint32_t num_l2_entries; 95 96 if (s->ct.indirect) { 97 l2t_id = icid / (s->ct.page_sz / L1TABLE_ENTRY_SIZE); 98 99 value = address_space_ldq_le(as, 100 s->ct.base_addr + 101 (l2t_id * L1TABLE_ENTRY_SIZE), 102 MEMTXATTRS_UNSPECIFIED, res); 103 104 if (*res == MEMTX_OK) { 105 valid_l2t = (value & L2_TABLE_VALID_MASK) != 0; 106 107 if (valid_l2t) { 108 num_l2_entries = s->ct.page_sz / s->ct.entry_sz; 109 110 l2t_addr = value & ((1ULL << 51) - 1); 111 112 *cte = address_space_ldq_le(as, l2t_addr + 113 ((icid % num_l2_entries) * GITS_CTE_SIZE), 114 MEMTXATTRS_UNSPECIFIED, res); 115 } 116 } 117 } else { 118 /* Flat level table */ 119 *cte = address_space_ldq_le(as, s->ct.base_addr + 120 (icid * GITS_CTE_SIZE), 121 MEMTXATTRS_UNSPECIFIED, res); 122 } 123 124 return FIELD_EX64(*cte, CTE, VALID); 125 } 126 127 static bool update_ite(GICv3ITSState *s, uint32_t eventid, uint64_t dte, 128 IteEntry ite) 129 { 130 AddressSpace *as = &s->gicv3->dma_as; 131 uint64_t itt_addr; 132 MemTxResult res = MEMTX_OK; 133 134 itt_addr = FIELD_EX64(dte, DTE, ITTADDR); 135 itt_addr <<= ITTADDR_SHIFT; /* 256 byte aligned */ 136 137 address_space_stq_le(as, itt_addr + (eventid * (sizeof(uint64_t) + 138 sizeof(uint32_t))), ite.itel, MEMTXATTRS_UNSPECIFIED, 139 &res); 140 141 if (res == MEMTX_OK) { 142 address_space_stl_le(as, itt_addr + (eventid * (sizeof(uint64_t) + 143 sizeof(uint32_t))) + sizeof(uint32_t), ite.iteh, 144 MEMTXATTRS_UNSPECIFIED, &res); 145 } 146 if (res != MEMTX_OK) { 147 return false; 148 } else { 149 return true; 150 } 151 } 152 153 static bool get_ite(GICv3ITSState *s, uint32_t eventid, uint64_t dte, 154 uint16_t *icid, uint32_t *pIntid, MemTxResult *res) 155 { 156 AddressSpace *as = &s->gicv3->dma_as; 157 uint64_t itt_addr; 158 bool status = false; 159 IteEntry ite = {}; 160 161 itt_addr = FIELD_EX64(dte, DTE, ITTADDR); 162 itt_addr <<= ITTADDR_SHIFT; /* 256 byte aligned */ 163 164 ite.itel = address_space_ldq_le(as, itt_addr + 165 (eventid * (sizeof(uint64_t) + 166 sizeof(uint32_t))), MEMTXATTRS_UNSPECIFIED, 167 res); 168 169 if (*res == MEMTX_OK) { 170 ite.iteh = address_space_ldl_le(as, itt_addr + 171 (eventid * (sizeof(uint64_t) + 172 sizeof(uint32_t))) + sizeof(uint32_t), 173 MEMTXATTRS_UNSPECIFIED, res); 174 175 if (*res == MEMTX_OK) { 176 if (FIELD_EX64(ite.itel, ITE_L, VALID)) { 177 int inttype = FIELD_EX64(ite.itel, ITE_L, INTTYPE); 178 if (inttype == ITE_INTTYPE_PHYSICAL) { 179 *pIntid = FIELD_EX64(ite.itel, ITE_L, INTID); 180 *icid = FIELD_EX32(ite.iteh, ITE_H, ICID); 181 status = true; 182 } 183 } 184 } 185 } 186 return status; 187 } 188 189 static uint64_t get_dte(GICv3ITSState *s, uint32_t devid, MemTxResult *res) 190 { 191 AddressSpace *as = &s->gicv3->dma_as; 192 uint64_t l2t_addr; 193 uint64_t value; 194 bool valid_l2t; 195 uint32_t l2t_id; 196 uint32_t num_l2_entries; 197 198 if (s->dt.indirect) { 199 l2t_id = devid / (s->dt.page_sz / L1TABLE_ENTRY_SIZE); 200 201 value = address_space_ldq_le(as, 202 s->dt.base_addr + 203 (l2t_id * L1TABLE_ENTRY_SIZE), 204 MEMTXATTRS_UNSPECIFIED, res); 205 206 if (*res == MEMTX_OK) { 207 valid_l2t = (value & L2_TABLE_VALID_MASK) != 0; 208 209 if (valid_l2t) { 210 num_l2_entries = s->dt.page_sz / s->dt.entry_sz; 211 212 l2t_addr = value & ((1ULL << 51) - 1); 213 214 value = address_space_ldq_le(as, l2t_addr + 215 ((devid % num_l2_entries) * GITS_DTE_SIZE), 216 MEMTXATTRS_UNSPECIFIED, res); 217 } 218 } 219 } else { 220 /* Flat level table */ 221 value = address_space_ldq_le(as, s->dt.base_addr + 222 (devid * GITS_DTE_SIZE), 223 MEMTXATTRS_UNSPECIFIED, res); 224 } 225 226 return value; 227 } 228 229 /* 230 * This function handles the processing of following commands based on 231 * the ItsCmdType parameter passed:- 232 * 1. triggering of lpi interrupt translation via ITS INT command 233 * 2. triggering of lpi interrupt translation via gits_translater register 234 * 3. handling of ITS CLEAR command 235 * 4. handling of ITS DISCARD command 236 */ 237 static ItsCmdResult process_its_cmd(GICv3ITSState *s, uint64_t value, 238 uint32_t offset, ItsCmdType cmd) 239 { 240 AddressSpace *as = &s->gicv3->dma_as; 241 uint32_t devid, eventid; 242 MemTxResult res = MEMTX_OK; 243 bool dte_valid; 244 uint64_t dte = 0; 245 uint64_t num_eventids; 246 uint16_t icid = 0; 247 uint32_t pIntid = 0; 248 bool ite_valid = false; 249 uint64_t cte = 0; 250 bool cte_valid = false; 251 uint64_t rdbase; 252 253 if (cmd == NONE) { 254 devid = offset; 255 } else { 256 devid = ((value & DEVID_MASK) >> DEVID_SHIFT); 257 258 offset += NUM_BYTES_IN_DW; 259 value = address_space_ldq_le(as, s->cq.base_addr + offset, 260 MEMTXATTRS_UNSPECIFIED, &res); 261 } 262 263 if (res != MEMTX_OK) { 264 return CMD_STALL; 265 } 266 267 eventid = (value & EVENTID_MASK); 268 269 dte = get_dte(s, devid, &res); 270 271 if (res != MEMTX_OK) { 272 return CMD_STALL; 273 } 274 dte_valid = FIELD_EX64(dte, DTE, VALID); 275 276 if (!dte_valid) { 277 qemu_log_mask(LOG_GUEST_ERROR, 278 "%s: invalid command attributes: " 279 "invalid dte: %"PRIx64" for %d\n", 280 __func__, dte, devid); 281 return CMD_CONTINUE; 282 } 283 284 num_eventids = 1ULL << (FIELD_EX64(dte, DTE, SIZE) + 1); 285 286 ite_valid = get_ite(s, eventid, dte, &icid, &pIntid, &res); 287 if (res != MEMTX_OK) { 288 return CMD_STALL; 289 } 290 291 if (!ite_valid) { 292 qemu_log_mask(LOG_GUEST_ERROR, 293 "%s: invalid command attributes: invalid ITE\n", 294 __func__); 295 return CMD_CONTINUE; 296 } 297 298 cte_valid = get_cte(s, icid, &cte, &res); 299 if (res != MEMTX_OK) { 300 return CMD_STALL; 301 } 302 if (!cte_valid) { 303 qemu_log_mask(LOG_GUEST_ERROR, 304 "%s: invalid command attributes: " 305 "invalid cte: %"PRIx64"\n", 306 __func__, cte); 307 return CMD_CONTINUE; 308 } 309 310 if (devid >= s->dt.num_ids) { 311 qemu_log_mask(LOG_GUEST_ERROR, 312 "%s: invalid command attributes: devid %d>=%d", 313 __func__, devid, s->dt.num_ids); 314 return CMD_CONTINUE; 315 } 316 if (eventid >= num_eventids) { 317 qemu_log_mask(LOG_GUEST_ERROR, 318 "%s: invalid command attributes: eventid %d >= %" 319 PRId64 "\n", 320 __func__, eventid, num_eventids); 321 return CMD_CONTINUE; 322 } 323 324 /* 325 * Current implementation only supports rdbase == procnum 326 * Hence rdbase physical address is ignored 327 */ 328 rdbase = FIELD_EX64(cte, CTE, RDBASE); 329 330 if (rdbase >= s->gicv3->num_cpu) { 331 return CMD_CONTINUE; 332 } 333 334 if ((cmd == CLEAR) || (cmd == DISCARD)) { 335 gicv3_redist_process_lpi(&s->gicv3->cpu[rdbase], pIntid, 0); 336 } else { 337 gicv3_redist_process_lpi(&s->gicv3->cpu[rdbase], pIntid, 1); 338 } 339 340 if (cmd == DISCARD) { 341 IteEntry ite = {}; 342 /* remove mapping from interrupt translation table */ 343 return update_ite(s, eventid, dte, ite) ? CMD_CONTINUE : CMD_STALL; 344 } 345 return CMD_CONTINUE; 346 } 347 348 static ItsCmdResult process_mapti(GICv3ITSState *s, uint64_t value, 349 uint32_t offset, bool ignore_pInt) 350 { 351 AddressSpace *as = &s->gicv3->dma_as; 352 uint32_t devid, eventid; 353 uint32_t pIntid = 0; 354 uint64_t num_eventids; 355 uint32_t num_intids; 356 bool dte_valid; 357 MemTxResult res = MEMTX_OK; 358 uint16_t icid = 0; 359 uint64_t dte = 0; 360 IteEntry ite = {}; 361 362 devid = ((value & DEVID_MASK) >> DEVID_SHIFT); 363 offset += NUM_BYTES_IN_DW; 364 value = address_space_ldq_le(as, s->cq.base_addr + offset, 365 MEMTXATTRS_UNSPECIFIED, &res); 366 367 if (res != MEMTX_OK) { 368 return CMD_STALL; 369 } 370 371 eventid = (value & EVENTID_MASK); 372 373 if (ignore_pInt) { 374 pIntid = eventid; 375 } else { 376 pIntid = ((value & pINTID_MASK) >> pINTID_SHIFT); 377 } 378 379 offset += NUM_BYTES_IN_DW; 380 value = address_space_ldq_le(as, s->cq.base_addr + offset, 381 MEMTXATTRS_UNSPECIFIED, &res); 382 383 if (res != MEMTX_OK) { 384 return CMD_STALL; 385 } 386 387 icid = value & ICID_MASK; 388 389 dte = get_dte(s, devid, &res); 390 391 if (res != MEMTX_OK) { 392 return CMD_STALL; 393 } 394 dte_valid = FIELD_EX64(dte, DTE, VALID); 395 num_eventids = 1ULL << (FIELD_EX64(dte, DTE, SIZE) + 1); 396 num_intids = 1ULL << (GICD_TYPER_IDBITS + 1); 397 398 if ((devid >= s->dt.num_ids) || (icid >= s->ct.num_ids) 399 || !dte_valid || (eventid >= num_eventids) || 400 (((pIntid < GICV3_LPI_INTID_START) || (pIntid >= num_intids)) && 401 (pIntid != INTID_SPURIOUS))) { 402 qemu_log_mask(LOG_GUEST_ERROR, 403 "%s: invalid command attributes " 404 "devid %d or icid %d or eventid %d or pIntid %d or" 405 "unmapped dte %d\n", __func__, devid, icid, eventid, 406 pIntid, dte_valid); 407 /* 408 * in this implementation, in case of error 409 * we ignore this command and move onto the next 410 * command in the queue 411 */ 412 return CMD_CONTINUE; 413 } 414 415 /* add ite entry to interrupt translation table */ 416 ite.itel = FIELD_DP64(ite.itel, ITE_L, VALID, dte_valid); 417 ite.itel = FIELD_DP64(ite.itel, ITE_L, INTTYPE, ITE_INTTYPE_PHYSICAL); 418 ite.itel = FIELD_DP64(ite.itel, ITE_L, INTID, pIntid); 419 ite.itel = FIELD_DP64(ite.itel, ITE_L, DOORBELL, INTID_SPURIOUS); 420 ite.iteh = FIELD_DP32(ite.iteh, ITE_H, ICID, icid); 421 422 return update_ite(s, eventid, dte, ite) ? CMD_CONTINUE : CMD_STALL; 423 } 424 425 static bool update_cte(GICv3ITSState *s, uint16_t icid, bool valid, 426 uint64_t rdbase) 427 { 428 AddressSpace *as = &s->gicv3->dma_as; 429 uint64_t value; 430 uint64_t l2t_addr; 431 bool valid_l2t; 432 uint32_t l2t_id; 433 uint32_t num_l2_entries; 434 uint64_t cte = 0; 435 MemTxResult res = MEMTX_OK; 436 437 if (!s->ct.valid) { 438 return true; 439 } 440 441 if (valid) { 442 /* add mapping entry to collection table */ 443 cte = FIELD_DP64(cte, CTE, VALID, 1); 444 cte = FIELD_DP64(cte, CTE, RDBASE, rdbase); 445 } 446 447 /* 448 * The specification defines the format of level 1 entries of a 449 * 2-level table, but the format of level 2 entries and the format 450 * of flat-mapped tables is IMPDEF. 451 */ 452 if (s->ct.indirect) { 453 l2t_id = icid / (s->ct.page_sz / L1TABLE_ENTRY_SIZE); 454 455 value = address_space_ldq_le(as, 456 s->ct.base_addr + 457 (l2t_id * L1TABLE_ENTRY_SIZE), 458 MEMTXATTRS_UNSPECIFIED, &res); 459 460 if (res != MEMTX_OK) { 461 return false; 462 } 463 464 valid_l2t = (value & L2_TABLE_VALID_MASK) != 0; 465 466 if (valid_l2t) { 467 num_l2_entries = s->ct.page_sz / s->ct.entry_sz; 468 469 l2t_addr = value & ((1ULL << 51) - 1); 470 471 address_space_stq_le(as, l2t_addr + 472 ((icid % num_l2_entries) * GITS_CTE_SIZE), 473 cte, MEMTXATTRS_UNSPECIFIED, &res); 474 } 475 } else { 476 /* Flat level table */ 477 address_space_stq_le(as, s->ct.base_addr + (icid * GITS_CTE_SIZE), 478 cte, MEMTXATTRS_UNSPECIFIED, &res); 479 } 480 if (res != MEMTX_OK) { 481 return false; 482 } else { 483 return true; 484 } 485 } 486 487 static ItsCmdResult process_mapc(GICv3ITSState *s, uint32_t offset) 488 { 489 AddressSpace *as = &s->gicv3->dma_as; 490 uint16_t icid; 491 uint64_t rdbase; 492 bool valid; 493 MemTxResult res = MEMTX_OK; 494 uint64_t value; 495 496 offset += NUM_BYTES_IN_DW; 497 offset += NUM_BYTES_IN_DW; 498 499 value = address_space_ldq_le(as, s->cq.base_addr + offset, 500 MEMTXATTRS_UNSPECIFIED, &res); 501 502 if (res != MEMTX_OK) { 503 return CMD_STALL; 504 } 505 506 icid = value & ICID_MASK; 507 508 rdbase = (value & R_MAPC_RDBASE_MASK) >> R_MAPC_RDBASE_SHIFT; 509 rdbase &= RDBASE_PROCNUM_MASK; 510 511 valid = (value & CMD_FIELD_VALID_MASK); 512 513 if ((icid >= s->ct.num_ids) || (rdbase >= s->gicv3->num_cpu)) { 514 qemu_log_mask(LOG_GUEST_ERROR, 515 "ITS MAPC: invalid collection table attributes " 516 "icid %d rdbase %" PRIu64 "\n", icid, rdbase); 517 /* 518 * in this implementation, in case of error 519 * we ignore this command and move onto the next 520 * command in the queue 521 */ 522 return CMD_CONTINUE; 523 } 524 525 return update_cte(s, icid, valid, rdbase) ? CMD_CONTINUE : CMD_STALL; 526 } 527 528 static bool update_dte(GICv3ITSState *s, uint32_t devid, bool valid, 529 uint8_t size, uint64_t itt_addr) 530 { 531 AddressSpace *as = &s->gicv3->dma_as; 532 uint64_t value; 533 uint64_t l2t_addr; 534 bool valid_l2t; 535 uint32_t l2t_id; 536 uint32_t num_l2_entries; 537 uint64_t dte = 0; 538 MemTxResult res = MEMTX_OK; 539 540 if (s->dt.valid) { 541 if (valid) { 542 /* add mapping entry to device table */ 543 dte = FIELD_DP64(dte, DTE, VALID, 1); 544 dte = FIELD_DP64(dte, DTE, SIZE, size); 545 dte = FIELD_DP64(dte, DTE, ITTADDR, itt_addr); 546 } 547 } else { 548 return true; 549 } 550 551 /* 552 * The specification defines the format of level 1 entries of a 553 * 2-level table, but the format of level 2 entries and the format 554 * of flat-mapped tables is IMPDEF. 555 */ 556 if (s->dt.indirect) { 557 l2t_id = devid / (s->dt.page_sz / L1TABLE_ENTRY_SIZE); 558 559 value = address_space_ldq_le(as, 560 s->dt.base_addr + 561 (l2t_id * L1TABLE_ENTRY_SIZE), 562 MEMTXATTRS_UNSPECIFIED, &res); 563 564 if (res != MEMTX_OK) { 565 return false; 566 } 567 568 valid_l2t = (value & L2_TABLE_VALID_MASK) != 0; 569 570 if (valid_l2t) { 571 num_l2_entries = s->dt.page_sz / s->dt.entry_sz; 572 573 l2t_addr = value & ((1ULL << 51) - 1); 574 575 address_space_stq_le(as, l2t_addr + 576 ((devid % num_l2_entries) * GITS_DTE_SIZE), 577 dte, MEMTXATTRS_UNSPECIFIED, &res); 578 } 579 } else { 580 /* Flat level table */ 581 address_space_stq_le(as, s->dt.base_addr + (devid * GITS_DTE_SIZE), 582 dte, MEMTXATTRS_UNSPECIFIED, &res); 583 } 584 if (res != MEMTX_OK) { 585 return false; 586 } else { 587 return true; 588 } 589 } 590 591 static ItsCmdResult process_mapd(GICv3ITSState *s, uint64_t value, 592 uint32_t offset) 593 { 594 AddressSpace *as = &s->gicv3->dma_as; 595 uint32_t devid; 596 uint8_t size; 597 uint64_t itt_addr; 598 bool valid; 599 MemTxResult res = MEMTX_OK; 600 ItsCmdResult result = CMD_STALL; 601 602 devid = ((value & DEVID_MASK) >> DEVID_SHIFT); 603 604 offset += NUM_BYTES_IN_DW; 605 value = address_space_ldq_le(as, s->cq.base_addr + offset, 606 MEMTXATTRS_UNSPECIFIED, &res); 607 608 if (res != MEMTX_OK) { 609 return result; 610 } 611 612 size = (value & SIZE_MASK); 613 614 offset += NUM_BYTES_IN_DW; 615 value = address_space_ldq_le(as, s->cq.base_addr + offset, 616 MEMTXATTRS_UNSPECIFIED, &res); 617 618 if (res != MEMTX_OK) { 619 return result; 620 } 621 622 itt_addr = (value & ITTADDR_MASK) >> ITTADDR_SHIFT; 623 624 valid = (value & CMD_FIELD_VALID_MASK); 625 626 if ((devid >= s->dt.num_ids) || 627 (size > FIELD_EX64(s->typer, GITS_TYPER, IDBITS))) { 628 qemu_log_mask(LOG_GUEST_ERROR, 629 "ITS MAPD: invalid device table attributes " 630 "devid %d or size %d\n", devid, size); 631 /* 632 * in this implementation, in case of error 633 * we ignore this command and move onto the next 634 * command in the queue 635 */ 636 } else { 637 result = update_dte(s, devid, valid, size, itt_addr) ? CMD_CONTINUE : CMD_STALL; 638 } 639 640 return result; 641 } 642 643 /* 644 * Current implementation blocks until all 645 * commands are processed 646 */ 647 static void process_cmdq(GICv3ITSState *s) 648 { 649 uint32_t wr_offset = 0; 650 uint32_t rd_offset = 0; 651 uint32_t cq_offset = 0; 652 uint64_t data; 653 AddressSpace *as = &s->gicv3->dma_as; 654 MemTxResult res = MEMTX_OK; 655 uint8_t cmd; 656 int i; 657 658 if (!(s->ctlr & R_GITS_CTLR_ENABLED_MASK)) { 659 return; 660 } 661 662 wr_offset = FIELD_EX64(s->cwriter, GITS_CWRITER, OFFSET); 663 664 if (wr_offset >= s->cq.num_entries) { 665 qemu_log_mask(LOG_GUEST_ERROR, 666 "%s: invalid write offset " 667 "%d\n", __func__, wr_offset); 668 return; 669 } 670 671 rd_offset = FIELD_EX64(s->creadr, GITS_CREADR, OFFSET); 672 673 if (rd_offset >= s->cq.num_entries) { 674 qemu_log_mask(LOG_GUEST_ERROR, 675 "%s: invalid read offset " 676 "%d\n", __func__, rd_offset); 677 return; 678 } 679 680 while (wr_offset != rd_offset) { 681 ItsCmdResult result = CMD_CONTINUE; 682 683 cq_offset = (rd_offset * GITS_CMDQ_ENTRY_SIZE); 684 data = address_space_ldq_le(as, s->cq.base_addr + cq_offset, 685 MEMTXATTRS_UNSPECIFIED, &res); 686 if (res != MEMTX_OK) { 687 s->creadr = FIELD_DP64(s->creadr, GITS_CREADR, STALLED, 1); 688 qemu_log_mask(LOG_GUEST_ERROR, 689 "%s: could not read command at 0x%" PRIx64 "\n", 690 __func__, s->cq.base_addr + cq_offset); 691 break; 692 } 693 694 cmd = (data & CMD_MASK); 695 696 switch (cmd) { 697 case GITS_CMD_INT: 698 result = process_its_cmd(s, data, cq_offset, INTERRUPT); 699 break; 700 case GITS_CMD_CLEAR: 701 result = process_its_cmd(s, data, cq_offset, CLEAR); 702 break; 703 case GITS_CMD_SYNC: 704 /* 705 * Current implementation makes a blocking synchronous call 706 * for every command issued earlier, hence the internal state 707 * is already consistent by the time SYNC command is executed. 708 * Hence no further processing is required for SYNC command. 709 */ 710 break; 711 case GITS_CMD_MAPD: 712 result = process_mapd(s, data, cq_offset); 713 break; 714 case GITS_CMD_MAPC: 715 result = process_mapc(s, cq_offset); 716 break; 717 case GITS_CMD_MAPTI: 718 result = process_mapti(s, data, cq_offset, false); 719 break; 720 case GITS_CMD_MAPI: 721 result = process_mapti(s, data, cq_offset, true); 722 break; 723 case GITS_CMD_DISCARD: 724 result = process_its_cmd(s, data, cq_offset, DISCARD); 725 break; 726 case GITS_CMD_INV: 727 case GITS_CMD_INVALL: 728 /* 729 * Current implementation doesn't cache any ITS tables, 730 * but the calculated lpi priority information. We only 731 * need to trigger lpi priority re-calculation to be in 732 * sync with LPI config table or pending table changes. 733 */ 734 for (i = 0; i < s->gicv3->num_cpu; i++) { 735 gicv3_redist_update_lpi(&s->gicv3->cpu[i]); 736 } 737 break; 738 default: 739 break; 740 } 741 if (result == CMD_CONTINUE) { 742 rd_offset++; 743 rd_offset %= s->cq.num_entries; 744 s->creadr = FIELD_DP64(s->creadr, GITS_CREADR, OFFSET, rd_offset); 745 } else { 746 /* CMD_STALL */ 747 s->creadr = FIELD_DP64(s->creadr, GITS_CREADR, STALLED, 1); 748 qemu_log_mask(LOG_GUEST_ERROR, 749 "%s: 0x%x cmd processing failed, stalling\n", 750 __func__, cmd); 751 break; 752 } 753 } 754 } 755 756 /* 757 * This function extracts the ITS Device and Collection table specific 758 * parameters (like base_addr, size etc) from GITS_BASER register. 759 * It is called during ITS enable and also during post_load migration 760 */ 761 static void extract_table_params(GICv3ITSState *s) 762 { 763 uint16_t num_pages = 0; 764 uint8_t page_sz_type; 765 uint8_t type; 766 uint32_t page_sz = 0; 767 uint64_t value; 768 769 for (int i = 0; i < 8; i++) { 770 TableDesc *td; 771 int idbits; 772 773 value = s->baser[i]; 774 775 if (!value) { 776 continue; 777 } 778 779 page_sz_type = FIELD_EX64(value, GITS_BASER, PAGESIZE); 780 781 switch (page_sz_type) { 782 case 0: 783 page_sz = GITS_PAGE_SIZE_4K; 784 break; 785 786 case 1: 787 page_sz = GITS_PAGE_SIZE_16K; 788 break; 789 790 case 2: 791 case 3: 792 page_sz = GITS_PAGE_SIZE_64K; 793 break; 794 795 default: 796 g_assert_not_reached(); 797 } 798 799 num_pages = FIELD_EX64(value, GITS_BASER, SIZE) + 1; 800 801 type = FIELD_EX64(value, GITS_BASER, TYPE); 802 803 switch (type) { 804 case GITS_BASER_TYPE_DEVICE: 805 td = &s->dt; 806 idbits = FIELD_EX64(s->typer, GITS_TYPER, DEVBITS) + 1; 807 break; 808 case GITS_BASER_TYPE_COLLECTION: 809 td = &s->ct; 810 if (FIELD_EX64(s->typer, GITS_TYPER, CIL)) { 811 idbits = FIELD_EX64(s->typer, GITS_TYPER, CIDBITS) + 1; 812 } else { 813 /* 16-bit CollectionId supported when CIL == 0 */ 814 idbits = 16; 815 } 816 break; 817 default: 818 /* 819 * GITS_BASER<n>.TYPE is read-only, so GITS_BASER_RO_MASK 820 * ensures we will only see type values corresponding to 821 * the values set up in gicv3_its_reset(). 822 */ 823 g_assert_not_reached(); 824 } 825 826 memset(td, 0, sizeof(*td)); 827 td->valid = FIELD_EX64(value, GITS_BASER, VALID); 828 /* 829 * If GITS_BASER<n>.Valid is 0 for any <n> then we will not process 830 * interrupts. (GITS_TYPER.HCC is 0 for this implementation, so we 831 * do not have a special case where the GITS_BASER<n>.Valid bit is 0 832 * for the register corresponding to the Collection table but we 833 * still have to process interrupts using non-memory-backed 834 * Collection table entries.) 835 */ 836 if (!td->valid) { 837 continue; 838 } 839 td->page_sz = page_sz; 840 td->indirect = FIELD_EX64(value, GITS_BASER, INDIRECT); 841 td->entry_sz = FIELD_EX64(value, GITS_BASER, ENTRYSIZE) + 1; 842 td->base_addr = baser_base_addr(value, page_sz); 843 if (!td->indirect) { 844 td->num_entries = (num_pages * page_sz) / td->entry_sz; 845 } else { 846 td->num_entries = (((num_pages * page_sz) / 847 L1TABLE_ENTRY_SIZE) * 848 (page_sz / td->entry_sz)); 849 } 850 td->num_ids = 1ULL << idbits; 851 } 852 } 853 854 static void extract_cmdq_params(GICv3ITSState *s) 855 { 856 uint16_t num_pages = 0; 857 uint64_t value = s->cbaser; 858 859 num_pages = FIELD_EX64(value, GITS_CBASER, SIZE) + 1; 860 861 memset(&s->cq, 0 , sizeof(s->cq)); 862 s->cq.valid = FIELD_EX64(value, GITS_CBASER, VALID); 863 864 if (s->cq.valid) { 865 s->cq.num_entries = (num_pages * GITS_PAGE_SIZE_4K) / 866 GITS_CMDQ_ENTRY_SIZE; 867 s->cq.base_addr = FIELD_EX64(value, GITS_CBASER, PHYADDR); 868 s->cq.base_addr <<= R_GITS_CBASER_PHYADDR_SHIFT; 869 } 870 } 871 872 static MemTxResult gicv3_its_translation_write(void *opaque, hwaddr offset, 873 uint64_t data, unsigned size, 874 MemTxAttrs attrs) 875 { 876 GICv3ITSState *s = (GICv3ITSState *)opaque; 877 bool result = true; 878 uint32_t devid = 0; 879 880 switch (offset) { 881 case GITS_TRANSLATER: 882 if (s->ctlr & R_GITS_CTLR_ENABLED_MASK) { 883 devid = attrs.requester_id; 884 result = process_its_cmd(s, data, devid, NONE); 885 } 886 break; 887 default: 888 break; 889 } 890 891 if (result) { 892 return MEMTX_OK; 893 } else { 894 return MEMTX_ERROR; 895 } 896 } 897 898 static bool its_writel(GICv3ITSState *s, hwaddr offset, 899 uint64_t value, MemTxAttrs attrs) 900 { 901 bool result = true; 902 int index; 903 904 switch (offset) { 905 case GITS_CTLR: 906 if (value & R_GITS_CTLR_ENABLED_MASK) { 907 s->ctlr |= R_GITS_CTLR_ENABLED_MASK; 908 extract_table_params(s); 909 extract_cmdq_params(s); 910 s->creadr = 0; 911 process_cmdq(s); 912 } else { 913 s->ctlr &= ~R_GITS_CTLR_ENABLED_MASK; 914 } 915 break; 916 case GITS_CBASER: 917 /* 918 * IMPDEF choice:- GITS_CBASER register becomes RO if ITS is 919 * already enabled 920 */ 921 if (!(s->ctlr & R_GITS_CTLR_ENABLED_MASK)) { 922 s->cbaser = deposit64(s->cbaser, 0, 32, value); 923 s->creadr = 0; 924 s->cwriter = s->creadr; 925 } 926 break; 927 case GITS_CBASER + 4: 928 /* 929 * IMPDEF choice:- GITS_CBASER register becomes RO if ITS is 930 * already enabled 931 */ 932 if (!(s->ctlr & R_GITS_CTLR_ENABLED_MASK)) { 933 s->cbaser = deposit64(s->cbaser, 32, 32, value); 934 s->creadr = 0; 935 s->cwriter = s->creadr; 936 } 937 break; 938 case GITS_CWRITER: 939 s->cwriter = deposit64(s->cwriter, 0, 32, 940 (value & ~R_GITS_CWRITER_RETRY_MASK)); 941 if (s->cwriter != s->creadr) { 942 process_cmdq(s); 943 } 944 break; 945 case GITS_CWRITER + 4: 946 s->cwriter = deposit64(s->cwriter, 32, 32, value); 947 break; 948 case GITS_CREADR: 949 if (s->gicv3->gicd_ctlr & GICD_CTLR_DS) { 950 s->creadr = deposit64(s->creadr, 0, 32, 951 (value & ~R_GITS_CREADR_STALLED_MASK)); 952 } else { 953 /* RO register, ignore the write */ 954 qemu_log_mask(LOG_GUEST_ERROR, 955 "%s: invalid guest write to RO register at offset " 956 TARGET_FMT_plx "\n", __func__, offset); 957 } 958 break; 959 case GITS_CREADR + 4: 960 if (s->gicv3->gicd_ctlr & GICD_CTLR_DS) { 961 s->creadr = deposit64(s->creadr, 32, 32, value); 962 } else { 963 /* RO register, ignore the write */ 964 qemu_log_mask(LOG_GUEST_ERROR, 965 "%s: invalid guest write to RO register at offset " 966 TARGET_FMT_plx "\n", __func__, offset); 967 } 968 break; 969 case GITS_BASER ... GITS_BASER + 0x3f: 970 /* 971 * IMPDEF choice:- GITS_BASERn register becomes RO if ITS is 972 * already enabled 973 */ 974 if (!(s->ctlr & R_GITS_CTLR_ENABLED_MASK)) { 975 index = (offset - GITS_BASER) / 8; 976 977 if (offset & 7) { 978 value <<= 32; 979 value &= ~GITS_BASER_RO_MASK; 980 s->baser[index] &= GITS_BASER_RO_MASK | MAKE_64BIT_MASK(0, 32); 981 s->baser[index] |= value; 982 } else { 983 value &= ~GITS_BASER_RO_MASK; 984 s->baser[index] &= GITS_BASER_RO_MASK | MAKE_64BIT_MASK(32, 32); 985 s->baser[index] |= value; 986 } 987 } 988 break; 989 case GITS_IIDR: 990 case GITS_IDREGS ... GITS_IDREGS + 0x2f: 991 /* RO registers, ignore the write */ 992 qemu_log_mask(LOG_GUEST_ERROR, 993 "%s: invalid guest write to RO register at offset " 994 TARGET_FMT_plx "\n", __func__, offset); 995 break; 996 default: 997 result = false; 998 break; 999 } 1000 return result; 1001 } 1002 1003 static bool its_readl(GICv3ITSState *s, hwaddr offset, 1004 uint64_t *data, MemTxAttrs attrs) 1005 { 1006 bool result = true; 1007 int index; 1008 1009 switch (offset) { 1010 case GITS_CTLR: 1011 *data = s->ctlr; 1012 break; 1013 case GITS_IIDR: 1014 *data = gicv3_iidr(); 1015 break; 1016 case GITS_IDREGS ... GITS_IDREGS + 0x2f: 1017 /* ID registers */ 1018 *data = gicv3_idreg(offset - GITS_IDREGS); 1019 break; 1020 case GITS_TYPER: 1021 *data = extract64(s->typer, 0, 32); 1022 break; 1023 case GITS_TYPER + 4: 1024 *data = extract64(s->typer, 32, 32); 1025 break; 1026 case GITS_CBASER: 1027 *data = extract64(s->cbaser, 0, 32); 1028 break; 1029 case GITS_CBASER + 4: 1030 *data = extract64(s->cbaser, 32, 32); 1031 break; 1032 case GITS_CREADR: 1033 *data = extract64(s->creadr, 0, 32); 1034 break; 1035 case GITS_CREADR + 4: 1036 *data = extract64(s->creadr, 32, 32); 1037 break; 1038 case GITS_CWRITER: 1039 *data = extract64(s->cwriter, 0, 32); 1040 break; 1041 case GITS_CWRITER + 4: 1042 *data = extract64(s->cwriter, 32, 32); 1043 break; 1044 case GITS_BASER ... GITS_BASER + 0x3f: 1045 index = (offset - GITS_BASER) / 8; 1046 if (offset & 7) { 1047 *data = extract64(s->baser[index], 32, 32); 1048 } else { 1049 *data = extract64(s->baser[index], 0, 32); 1050 } 1051 break; 1052 default: 1053 result = false; 1054 break; 1055 } 1056 return result; 1057 } 1058 1059 static bool its_writell(GICv3ITSState *s, hwaddr offset, 1060 uint64_t value, MemTxAttrs attrs) 1061 { 1062 bool result = true; 1063 int index; 1064 1065 switch (offset) { 1066 case GITS_BASER ... GITS_BASER + 0x3f: 1067 /* 1068 * IMPDEF choice:- GITS_BASERn register becomes RO if ITS is 1069 * already enabled 1070 */ 1071 if (!(s->ctlr & R_GITS_CTLR_ENABLED_MASK)) { 1072 index = (offset - GITS_BASER) / 8; 1073 s->baser[index] &= GITS_BASER_RO_MASK; 1074 s->baser[index] |= (value & ~GITS_BASER_RO_MASK); 1075 } 1076 break; 1077 case GITS_CBASER: 1078 /* 1079 * IMPDEF choice:- GITS_CBASER register becomes RO if ITS is 1080 * already enabled 1081 */ 1082 if (!(s->ctlr & R_GITS_CTLR_ENABLED_MASK)) { 1083 s->cbaser = value; 1084 s->creadr = 0; 1085 s->cwriter = s->creadr; 1086 } 1087 break; 1088 case GITS_CWRITER: 1089 s->cwriter = value & ~R_GITS_CWRITER_RETRY_MASK; 1090 if (s->cwriter != s->creadr) { 1091 process_cmdq(s); 1092 } 1093 break; 1094 case GITS_CREADR: 1095 if (s->gicv3->gicd_ctlr & GICD_CTLR_DS) { 1096 s->creadr = value & ~R_GITS_CREADR_STALLED_MASK; 1097 } else { 1098 /* RO register, ignore the write */ 1099 qemu_log_mask(LOG_GUEST_ERROR, 1100 "%s: invalid guest write to RO register at offset " 1101 TARGET_FMT_plx "\n", __func__, offset); 1102 } 1103 break; 1104 case GITS_TYPER: 1105 /* RO registers, ignore the write */ 1106 qemu_log_mask(LOG_GUEST_ERROR, 1107 "%s: invalid guest write to RO register at offset " 1108 TARGET_FMT_plx "\n", __func__, offset); 1109 break; 1110 default: 1111 result = false; 1112 break; 1113 } 1114 return result; 1115 } 1116 1117 static bool its_readll(GICv3ITSState *s, hwaddr offset, 1118 uint64_t *data, MemTxAttrs attrs) 1119 { 1120 bool result = true; 1121 int index; 1122 1123 switch (offset) { 1124 case GITS_TYPER: 1125 *data = s->typer; 1126 break; 1127 case GITS_BASER ... GITS_BASER + 0x3f: 1128 index = (offset - GITS_BASER) / 8; 1129 *data = s->baser[index]; 1130 break; 1131 case GITS_CBASER: 1132 *data = s->cbaser; 1133 break; 1134 case GITS_CREADR: 1135 *data = s->creadr; 1136 break; 1137 case GITS_CWRITER: 1138 *data = s->cwriter; 1139 break; 1140 default: 1141 result = false; 1142 break; 1143 } 1144 return result; 1145 } 1146 1147 static MemTxResult gicv3_its_read(void *opaque, hwaddr offset, uint64_t *data, 1148 unsigned size, MemTxAttrs attrs) 1149 { 1150 GICv3ITSState *s = (GICv3ITSState *)opaque; 1151 bool result; 1152 1153 switch (size) { 1154 case 4: 1155 result = its_readl(s, offset, data, attrs); 1156 break; 1157 case 8: 1158 result = its_readll(s, offset, data, attrs); 1159 break; 1160 default: 1161 result = false; 1162 break; 1163 } 1164 1165 if (!result) { 1166 qemu_log_mask(LOG_GUEST_ERROR, 1167 "%s: invalid guest read at offset " TARGET_FMT_plx 1168 "size %u\n", __func__, offset, size); 1169 /* 1170 * The spec requires that reserved registers are RAZ/WI; 1171 * so use false returns from leaf functions as a way to 1172 * trigger the guest-error logging but don't return it to 1173 * the caller, or we'll cause a spurious guest data abort. 1174 */ 1175 *data = 0; 1176 } 1177 return MEMTX_OK; 1178 } 1179 1180 static MemTxResult gicv3_its_write(void *opaque, hwaddr offset, uint64_t data, 1181 unsigned size, MemTxAttrs attrs) 1182 { 1183 GICv3ITSState *s = (GICv3ITSState *)opaque; 1184 bool result; 1185 1186 switch (size) { 1187 case 4: 1188 result = its_writel(s, offset, data, attrs); 1189 break; 1190 case 8: 1191 result = its_writell(s, offset, data, attrs); 1192 break; 1193 default: 1194 result = false; 1195 break; 1196 } 1197 1198 if (!result) { 1199 qemu_log_mask(LOG_GUEST_ERROR, 1200 "%s: invalid guest write at offset " TARGET_FMT_plx 1201 "size %u\n", __func__, offset, size); 1202 /* 1203 * The spec requires that reserved registers are RAZ/WI; 1204 * so use false returns from leaf functions as a way to 1205 * trigger the guest-error logging but don't return it to 1206 * the caller, or we'll cause a spurious guest data abort. 1207 */ 1208 } 1209 return MEMTX_OK; 1210 } 1211 1212 static const MemoryRegionOps gicv3_its_control_ops = { 1213 .read_with_attrs = gicv3_its_read, 1214 .write_with_attrs = gicv3_its_write, 1215 .valid.min_access_size = 4, 1216 .valid.max_access_size = 8, 1217 .impl.min_access_size = 4, 1218 .impl.max_access_size = 8, 1219 .endianness = DEVICE_NATIVE_ENDIAN, 1220 }; 1221 1222 static const MemoryRegionOps gicv3_its_translation_ops = { 1223 .write_with_attrs = gicv3_its_translation_write, 1224 .valid.min_access_size = 2, 1225 .valid.max_access_size = 4, 1226 .impl.min_access_size = 2, 1227 .impl.max_access_size = 4, 1228 .endianness = DEVICE_NATIVE_ENDIAN, 1229 }; 1230 1231 static void gicv3_arm_its_realize(DeviceState *dev, Error **errp) 1232 { 1233 GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev); 1234 int i; 1235 1236 for (i = 0; i < s->gicv3->num_cpu; i++) { 1237 if (!(s->gicv3->cpu[i].gicr_typer & GICR_TYPER_PLPIS)) { 1238 error_setg(errp, "Physical LPI not supported by CPU %d", i); 1239 return; 1240 } 1241 } 1242 1243 gicv3_its_init_mmio(s, &gicv3_its_control_ops, &gicv3_its_translation_ops); 1244 1245 address_space_init(&s->gicv3->dma_as, s->gicv3->dma, 1246 "gicv3-its-sysmem"); 1247 1248 /* set the ITS default features supported */ 1249 s->typer = FIELD_DP64(s->typer, GITS_TYPER, PHYSICAL, 1); 1250 s->typer = FIELD_DP64(s->typer, GITS_TYPER, ITT_ENTRY_SIZE, 1251 ITS_ITT_ENTRY_SIZE - 1); 1252 s->typer = FIELD_DP64(s->typer, GITS_TYPER, IDBITS, ITS_IDBITS); 1253 s->typer = FIELD_DP64(s->typer, GITS_TYPER, DEVBITS, ITS_DEVBITS); 1254 s->typer = FIELD_DP64(s->typer, GITS_TYPER, CIL, 1); 1255 s->typer = FIELD_DP64(s->typer, GITS_TYPER, CIDBITS, ITS_CIDBITS); 1256 } 1257 1258 static void gicv3_its_reset(DeviceState *dev) 1259 { 1260 GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev); 1261 GICv3ITSClass *c = ARM_GICV3_ITS_GET_CLASS(s); 1262 1263 c->parent_reset(dev); 1264 1265 /* Quiescent bit reset to 1 */ 1266 s->ctlr = FIELD_DP32(s->ctlr, GITS_CTLR, QUIESCENT, 1); 1267 1268 /* 1269 * setting GITS_BASER0.Type = 0b001 (Device) 1270 * GITS_BASER1.Type = 0b100 (Collection Table) 1271 * GITS_BASER<n>.Type,where n = 3 to 7 are 0b00 (Unimplemented) 1272 * GITS_BASER<0,1>.Page_Size = 64KB 1273 * and default translation table entry size to 16 bytes 1274 */ 1275 s->baser[0] = FIELD_DP64(s->baser[0], GITS_BASER, TYPE, 1276 GITS_BASER_TYPE_DEVICE); 1277 s->baser[0] = FIELD_DP64(s->baser[0], GITS_BASER, PAGESIZE, 1278 GITS_BASER_PAGESIZE_64K); 1279 s->baser[0] = FIELD_DP64(s->baser[0], GITS_BASER, ENTRYSIZE, 1280 GITS_DTE_SIZE - 1); 1281 1282 s->baser[1] = FIELD_DP64(s->baser[1], GITS_BASER, TYPE, 1283 GITS_BASER_TYPE_COLLECTION); 1284 s->baser[1] = FIELD_DP64(s->baser[1], GITS_BASER, PAGESIZE, 1285 GITS_BASER_PAGESIZE_64K); 1286 s->baser[1] = FIELD_DP64(s->baser[1], GITS_BASER, ENTRYSIZE, 1287 GITS_CTE_SIZE - 1); 1288 } 1289 1290 static void gicv3_its_post_load(GICv3ITSState *s) 1291 { 1292 if (s->ctlr & R_GITS_CTLR_ENABLED_MASK) { 1293 extract_table_params(s); 1294 extract_cmdq_params(s); 1295 } 1296 } 1297 1298 static Property gicv3_its_props[] = { 1299 DEFINE_PROP_LINK("parent-gicv3", GICv3ITSState, gicv3, "arm-gicv3", 1300 GICv3State *), 1301 DEFINE_PROP_END_OF_LIST(), 1302 }; 1303 1304 static void gicv3_its_class_init(ObjectClass *klass, void *data) 1305 { 1306 DeviceClass *dc = DEVICE_CLASS(klass); 1307 GICv3ITSClass *ic = ARM_GICV3_ITS_CLASS(klass); 1308 GICv3ITSCommonClass *icc = ARM_GICV3_ITS_COMMON_CLASS(klass); 1309 1310 dc->realize = gicv3_arm_its_realize; 1311 device_class_set_props(dc, gicv3_its_props); 1312 device_class_set_parent_reset(dc, gicv3_its_reset, &ic->parent_reset); 1313 icc->post_load = gicv3_its_post_load; 1314 } 1315 1316 static const TypeInfo gicv3_its_info = { 1317 .name = TYPE_ARM_GICV3_ITS, 1318 .parent = TYPE_ARM_GICV3_ITS_COMMON, 1319 .instance_size = sizeof(GICv3ITSState), 1320 .class_init = gicv3_its_class_init, 1321 .class_size = sizeof(GICv3ITSClass), 1322 }; 1323 1324 static void gicv3_its_register_types(void) 1325 { 1326 type_register_static(&gicv3_its_info); 1327 } 1328 1329 type_init(gicv3_its_register_types) 1330