1 /* 2 * ARM GICv3 emulation: Distributor 3 * 4 * Copyright (c) 2015 Huawei. 5 * Copyright (c) 2016 Linaro Limited. 6 * Written by Shlomo Pongratz, Peter Maydell 7 * 8 * This code is licensed under the GPL, version 2 or (at your option) 9 * any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/log.h" 14 #include "trace.h" 15 #include "gicv3_internal.h" 16 17 /* The GICD_NSACR registers contain a two bit field for each interrupt which 18 * allows the guest to give NonSecure code access to registers controlling 19 * Secure interrupts: 20 * 0b00: no access (NS accesses to bits for Secure interrupts will RAZ/WI) 21 * 0b01: NS r/w accesses permitted to ISPENDR, SETSPI_NSR, SGIR 22 * 0b10: as 0b01, and also r/w to ICPENDR, r/o to ISACTIVER/ICACTIVER, 23 * and w/o to CLRSPI_NSR 24 * 0b11: as 0b10, and also r/w to IROUTER and ITARGETSR 25 * 26 * Given a (multiple-of-32) interrupt number, these mask functions return 27 * a mask word where each bit is 1 if the NSACR settings permit access 28 * to the interrupt. The mask returned can then be ORed with the GICD_GROUP 29 * word for this set of interrupts to give an overall mask. 30 */ 31 32 typedef uint32_t maskfn(GICv3State *s, int irq); 33 34 static uint32_t mask_nsacr_ge1(GICv3State *s, int irq) 35 { 36 /* Return a mask where each bit is set if the NSACR field is >= 1 */ 37 uint64_t raw_nsacr = s->gicd_nsacr[irq / 16 + 1]; 38 39 raw_nsacr = raw_nsacr << 32 | s->gicd_nsacr[irq / 16]; 40 raw_nsacr = (raw_nsacr >> 1) | raw_nsacr; 41 return half_unshuffle64(raw_nsacr); 42 } 43 44 static uint32_t mask_nsacr_ge2(GICv3State *s, int irq) 45 { 46 /* Return a mask where each bit is set if the NSACR field is >= 2 */ 47 uint64_t raw_nsacr = s->gicd_nsacr[irq / 16 + 1]; 48 49 raw_nsacr = raw_nsacr << 32 | s->gicd_nsacr[irq / 16]; 50 raw_nsacr = raw_nsacr >> 1; 51 return half_unshuffle64(raw_nsacr); 52 } 53 54 /* We don't need a mask_nsacr_ge3() because IROUTER<n> isn't a bitmap register, 55 * but it would be implemented using: 56 * raw_nsacr = (raw_nsacr >> 1) & raw_nsacr; 57 */ 58 59 static uint32_t mask_group_and_nsacr(GICv3State *s, MemTxAttrs attrs, 60 maskfn *maskfn, int irq) 61 { 62 /* Return a 32-bit mask which should be applied for this set of 32 63 * interrupts; each bit is 1 if access is permitted by the 64 * combination of attrs.secure, GICD_GROUPR and GICD_NSACR. 65 */ 66 uint32_t mask; 67 68 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { 69 /* bits for Group 0 or Secure Group 1 interrupts are RAZ/WI 70 * unless the NSACR bits permit access. 71 */ 72 mask = *gic_bmp_ptr32(s->group, irq); 73 if (maskfn) { 74 mask |= maskfn(s, irq); 75 } 76 return mask; 77 } 78 return 0xFFFFFFFFU; 79 } 80 81 static int gicd_ns_access(GICv3State *s, int irq) 82 { 83 /* Return the 2 bit NS_access<x> field from GICD_NSACR<n> for the 84 * specified interrupt. 85 */ 86 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 87 return 0; 88 } 89 return extract32(s->gicd_nsacr[irq / 16], (irq % 16) * 2, 2); 90 } 91 92 static void gicd_write_set_bitmap_reg(GICv3State *s, MemTxAttrs attrs, 93 uint32_t *bmp, 94 maskfn *maskfn, 95 int offset, uint32_t val) 96 { 97 /* Helper routine to implement writing to a "set-bitmap" register 98 * (GICD_ISENABLER, GICD_ISPENDR, etc). 99 * Semantics implemented here: 100 * RAZ/WI for SGIs, PPIs, unimplemented IRQs 101 * Bits corresponding to Group 0 or Secure Group 1 interrupts RAZ/WI. 102 * Writing 1 means "set bit in bitmap"; writing 0 is ignored. 103 * offset should be the offset in bytes of the register from the start 104 * of its group. 105 */ 106 int irq = offset * 8; 107 108 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 109 return; 110 } 111 val &= mask_group_and_nsacr(s, attrs, maskfn, irq); 112 *gic_bmp_ptr32(bmp, irq) |= val; 113 gicv3_update(s, irq, 32); 114 } 115 116 static void gicd_write_clear_bitmap_reg(GICv3State *s, MemTxAttrs attrs, 117 uint32_t *bmp, 118 maskfn *maskfn, 119 int offset, uint32_t val) 120 { 121 /* Helper routine to implement writing to a "clear-bitmap" register 122 * (GICD_ICENABLER, GICD_ICPENDR, etc). 123 * Semantics implemented here: 124 * RAZ/WI for SGIs, PPIs, unimplemented IRQs 125 * Bits corresponding to Group 0 or Secure Group 1 interrupts RAZ/WI. 126 * Writing 1 means "clear bit in bitmap"; writing 0 is ignored. 127 * offset should be the offset in bytes of the register from the start 128 * of its group. 129 */ 130 int irq = offset * 8; 131 132 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 133 return; 134 } 135 val &= mask_group_and_nsacr(s, attrs, maskfn, irq); 136 *gic_bmp_ptr32(bmp, irq) &= ~val; 137 gicv3_update(s, irq, 32); 138 } 139 140 static uint32_t gicd_read_bitmap_reg(GICv3State *s, MemTxAttrs attrs, 141 uint32_t *bmp, 142 maskfn *maskfn, 143 int offset) 144 { 145 /* Helper routine to implement reading a "set/clear-bitmap" register 146 * (GICD_ICENABLER, GICD_ISENABLER, GICD_ICPENDR, etc). 147 * Semantics implemented here: 148 * RAZ/WI for SGIs, PPIs, unimplemented IRQs 149 * Bits corresponding to Group 0 or Secure Group 1 interrupts RAZ/WI. 150 * offset should be the offset in bytes of the register from the start 151 * of its group. 152 */ 153 int irq = offset * 8; 154 uint32_t val; 155 156 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 157 return 0; 158 } 159 val = *gic_bmp_ptr32(bmp, irq); 160 if (bmp == s->pending) { 161 /* The PENDING register is a special case -- for level triggered 162 * interrupts, the PENDING state is the logical OR of the state of 163 * the PENDING latch with the input line level. 164 */ 165 uint32_t edge = *gic_bmp_ptr32(s->edge_trigger, irq); 166 uint32_t level = *gic_bmp_ptr32(s->level, irq); 167 val |= (~edge & level); 168 } 169 val &= mask_group_and_nsacr(s, attrs, maskfn, irq); 170 return val; 171 } 172 173 static uint8_t gicd_read_ipriorityr(GICv3State *s, MemTxAttrs attrs, int irq) 174 { 175 /* Read the value of GICD_IPRIORITYR<n> for the specified interrupt, 176 * honouring security state (these are RAZ/WI for Group 0 or Secure 177 * Group 1 interrupts). 178 */ 179 uint32_t prio; 180 181 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 182 return 0; 183 } 184 185 prio = s->gicd_ipriority[irq]; 186 187 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { 188 if (!gicv3_gicd_group_test(s, irq)) { 189 /* Fields for Group 0 or Secure Group 1 interrupts are RAZ/WI */ 190 return 0; 191 } 192 /* NS view of the interrupt priority */ 193 prio = (prio << 1) & 0xff; 194 } 195 return prio; 196 } 197 198 static void gicd_write_ipriorityr(GICv3State *s, MemTxAttrs attrs, int irq, 199 uint8_t value) 200 { 201 /* Write the value of GICD_IPRIORITYR<n> for the specified interrupt, 202 * honouring security state (these are RAZ/WI for Group 0 or Secure 203 * Group 1 interrupts). 204 */ 205 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 206 return; 207 } 208 209 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { 210 if (!gicv3_gicd_group_test(s, irq)) { 211 /* Fields for Group 0 or Secure Group 1 interrupts are RAZ/WI */ 212 return; 213 } 214 /* NS view of the interrupt priority */ 215 value = 0x80 | (value >> 1); 216 } 217 s->gicd_ipriority[irq] = value; 218 } 219 220 static uint64_t gicd_read_irouter(GICv3State *s, MemTxAttrs attrs, int irq) 221 { 222 /* Read the value of GICD_IROUTER<n> for the specified interrupt, 223 * honouring security state. 224 */ 225 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 226 return 0; 227 } 228 229 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { 230 /* RAZ/WI for NS accesses to secure interrupts */ 231 if (!gicv3_gicd_group_test(s, irq)) { 232 if (gicd_ns_access(s, irq) != 3) { 233 return 0; 234 } 235 } 236 } 237 238 return s->gicd_irouter[irq]; 239 } 240 241 static void gicd_write_irouter(GICv3State *s, MemTxAttrs attrs, int irq, 242 uint64_t val) 243 { 244 /* Write the value of GICD_IROUTER<n> for the specified interrupt, 245 * honouring security state. 246 */ 247 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 248 return; 249 } 250 251 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { 252 /* RAZ/WI for NS accesses to secure interrupts */ 253 if (!gicv3_gicd_group_test(s, irq)) { 254 if (gicd_ns_access(s, irq) != 3) { 255 return; 256 } 257 } 258 } 259 260 s->gicd_irouter[irq] = val; 261 gicv3_cache_target_cpustate(s, irq); 262 gicv3_update(s, irq, 1); 263 } 264 265 /** 266 * gicd_readb 267 * gicd_readw 268 * gicd_readl 269 * gicd_readq 270 * gicd_writeb 271 * gicd_writew 272 * gicd_writel 273 * gicd_writeq 274 * 275 * Return %true if the operation succeeded, %false otherwise. 276 */ 277 278 static bool gicd_readb(GICv3State *s, hwaddr offset, 279 uint64_t *data, MemTxAttrs attrs) 280 { 281 /* Most GICv3 distributor registers do not support byte accesses. */ 282 switch (offset) { 283 case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf: 284 case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf: 285 case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff: 286 /* This GIC implementation always has affinity routing enabled, 287 * so these registers are all RAZ/WI. 288 */ 289 return true; 290 case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff: 291 *data = gicd_read_ipriorityr(s, attrs, offset - GICD_IPRIORITYR); 292 return true; 293 default: 294 return false; 295 } 296 } 297 298 static bool gicd_writeb(GICv3State *s, hwaddr offset, 299 uint64_t value, MemTxAttrs attrs) 300 { 301 /* Most GICv3 distributor registers do not support byte accesses. */ 302 switch (offset) { 303 case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf: 304 case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf: 305 case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff: 306 /* This GIC implementation always has affinity routing enabled, 307 * so these registers are all RAZ/WI. 308 */ 309 return true; 310 case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff: 311 { 312 int irq = offset - GICD_IPRIORITYR; 313 314 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 315 return true; 316 } 317 gicd_write_ipriorityr(s, attrs, irq, value); 318 gicv3_update(s, irq, 1); 319 return true; 320 } 321 default: 322 return false; 323 } 324 } 325 326 static bool gicd_readw(GICv3State *s, hwaddr offset, 327 uint64_t *data, MemTxAttrs attrs) 328 { 329 /* Only GICD_SETSPI_NSR, GICD_CLRSPI_NSR, GICD_SETSPI_SR and GICD_SETSPI_NSR 330 * support 16 bit accesses, and those registers are all part of the 331 * optional message-based SPI feature which this GIC does not currently 332 * implement (ie for us GICD_TYPER.MBIS == 0), so for us they are 333 * reserved. 334 */ 335 return false; 336 } 337 338 static bool gicd_writew(GICv3State *s, hwaddr offset, 339 uint64_t value, MemTxAttrs attrs) 340 { 341 /* Only GICD_SETSPI_NSR, GICD_CLRSPI_NSR, GICD_SETSPI_SR and GICD_SETSPI_NSR 342 * support 16 bit accesses, and those registers are all part of the 343 * optional message-based SPI feature which this GIC does not currently 344 * implement (ie for us GICD_TYPER.MBIS == 0), so for us they are 345 * reserved. 346 */ 347 return false; 348 } 349 350 static bool gicd_readl(GICv3State *s, hwaddr offset, 351 uint64_t *data, MemTxAttrs attrs) 352 { 353 /* Almost all GICv3 distributor registers are 32-bit. 354 * Note that WO registers must return an UNKNOWN value on reads, 355 * not an abort. 356 */ 357 358 switch (offset) { 359 case GICD_CTLR: 360 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { 361 /* The NS view of the GICD_CTLR sees only certain bits: 362 * + bit [31] (RWP) is an alias of the Secure bit [31] 363 * + bit [4] (ARE_NS) is an alias of Secure bit [5] 364 * + bit [1] (EnableGrp1A) is an alias of Secure bit [1] if 365 * NS affinity routing is enabled, otherwise RES0 366 * + bit [0] (EnableGrp1) is an alias of Secure bit [1] if 367 * NS affinity routing is not enabled, otherwise RES0 368 * Since for QEMU affinity routing is always enabled 369 * for both S and NS this means that bits [4] and [5] are 370 * both always 1, and we can simply make the NS view 371 * be bits 31, 4 and 1 of the S view. 372 */ 373 *data = s->gicd_ctlr & (GICD_CTLR_ARE_S | 374 GICD_CTLR_EN_GRP1NS | 375 GICD_CTLR_RWP); 376 } else { 377 *data = s->gicd_ctlr; 378 } 379 return true; 380 case GICD_TYPER: 381 { 382 /* For this implementation: 383 * No1N == 1 (1-of-N SPI interrupts not supported) 384 * A3V == 1 (non-zero values of Affinity level 3 supported) 385 * IDbits == 0xf (we support 16-bit interrupt identifiers) 386 * DVIS == 0 (Direct virtual LPI injection not supported) 387 * LPIS == 1 (LPIs are supported if affinity routing is enabled) 388 * num_LPIs == 0b00000 (bits [15:11],Number of LPIs as indicated 389 * by GICD_TYPER.IDbits) 390 * MBIS == 0 (message-based SPIs not supported) 391 * SecurityExtn == 1 if security extns supported 392 * CPUNumber == 0 since for us ARE is always 1 393 * ITLinesNumber == (num external irqs / 32) - 1 394 */ 395 int itlinesnumber = ((s->num_irq - GIC_INTERNAL) / 32) - 1; 396 /* 397 * SecurityExtn must be RAZ if GICD_CTLR.DS == 1, and 398 * "security extensions not supported" always implies DS == 1, 399 * so we only need to check the DS bit. 400 */ 401 bool sec_extn = !(s->gicd_ctlr & GICD_CTLR_DS); 402 403 *data = (1 << 25) | (1 << 24) | (sec_extn << 10) | 404 (s->lpi_enable << GICD_TYPER_LPIS_SHIFT) | 405 (0xf << 19) | itlinesnumber; 406 return true; 407 } 408 case GICD_IIDR: 409 /* We claim to be an ARM r0p0 with a zero ProductID. 410 * This is the same as an r0p0 GIC-500. 411 */ 412 *data = gicv3_iidr(); 413 return true; 414 case GICD_STATUSR: 415 /* RAZ/WI for us (this is an optional register and our implementation 416 * does not track RO/WO/reserved violations to report them to the guest) 417 */ 418 *data = 0; 419 return true; 420 case GICD_IGROUPR ... GICD_IGROUPR + 0x7f: 421 { 422 int irq; 423 424 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { 425 *data = 0; 426 return true; 427 } 428 /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ 429 irq = (offset - GICD_IGROUPR) * 8; 430 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 431 *data = 0; 432 return true; 433 } 434 *data = *gic_bmp_ptr32(s->group, irq); 435 return true; 436 } 437 case GICD_ISENABLER ... GICD_ISENABLER + 0x7f: 438 *data = gicd_read_bitmap_reg(s, attrs, s->enabled, NULL, 439 offset - GICD_ISENABLER); 440 return true; 441 case GICD_ICENABLER ... GICD_ICENABLER + 0x7f: 442 *data = gicd_read_bitmap_reg(s, attrs, s->enabled, NULL, 443 offset - GICD_ICENABLER); 444 return true; 445 case GICD_ISPENDR ... GICD_ISPENDR + 0x7f: 446 *data = gicd_read_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge1, 447 offset - GICD_ISPENDR); 448 return true; 449 case GICD_ICPENDR ... GICD_ICPENDR + 0x7f: 450 *data = gicd_read_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge2, 451 offset - GICD_ICPENDR); 452 return true; 453 case GICD_ISACTIVER ... GICD_ISACTIVER + 0x7f: 454 *data = gicd_read_bitmap_reg(s, attrs, s->active, mask_nsacr_ge2, 455 offset - GICD_ISACTIVER); 456 return true; 457 case GICD_ICACTIVER ... GICD_ICACTIVER + 0x7f: 458 *data = gicd_read_bitmap_reg(s, attrs, s->active, mask_nsacr_ge2, 459 offset - GICD_ICACTIVER); 460 return true; 461 case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff: 462 { 463 int i, irq = offset - GICD_IPRIORITYR; 464 uint32_t value = 0; 465 466 for (i = irq + 3; i >= irq; i--) { 467 value <<= 8; 468 value |= gicd_read_ipriorityr(s, attrs, i); 469 } 470 *data = value; 471 return true; 472 } 473 case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff: 474 /* RAZ/WI since affinity routing is always enabled */ 475 *data = 0; 476 return true; 477 case GICD_ICFGR ... GICD_ICFGR + 0xff: 478 { 479 /* Here only the even bits are used; odd bits are RES0 */ 480 int irq = (offset - GICD_ICFGR) * 4; 481 uint32_t value = 0; 482 483 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 484 *data = 0; 485 return true; 486 } 487 488 /* Since our edge_trigger bitmap is one bit per irq, we only need 489 * half of the 32-bit word, which we can then spread out 490 * into the odd bits. 491 */ 492 value = *gic_bmp_ptr32(s->edge_trigger, irq & ~0x1f); 493 value &= mask_group_and_nsacr(s, attrs, NULL, irq & ~0x1f); 494 value = extract32(value, (irq & 0x1f) ? 16 : 0, 16); 495 value = half_shuffle32(value) << 1; 496 *data = value; 497 return true; 498 } 499 case GICD_IGRPMODR ... GICD_IGRPMODR + 0xff: 500 { 501 int irq; 502 503 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) { 504 /* RAZ/WI if security disabled, or if 505 * security enabled and this is an NS access 506 */ 507 *data = 0; 508 return true; 509 } 510 /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ 511 irq = (offset - GICD_IGRPMODR) * 8; 512 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 513 *data = 0; 514 return true; 515 } 516 *data = *gic_bmp_ptr32(s->grpmod, irq); 517 return true; 518 } 519 case GICD_NSACR ... GICD_NSACR + 0xff: 520 { 521 /* Two bits per interrupt */ 522 int irq = (offset - GICD_NSACR) * 4; 523 524 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 525 *data = 0; 526 return true; 527 } 528 529 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) { 530 /* RAZ/WI if security disabled, or if 531 * security enabled and this is an NS access 532 */ 533 *data = 0; 534 return true; 535 } 536 537 *data = s->gicd_nsacr[irq / 16]; 538 return true; 539 } 540 case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf: 541 case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf: 542 /* RAZ/WI since affinity routing is always enabled */ 543 *data = 0; 544 return true; 545 case GICD_IROUTER ... GICD_IROUTER + 0x1fdf: 546 { 547 uint64_t r; 548 int irq = (offset - GICD_IROUTER) / 8; 549 550 r = gicd_read_irouter(s, attrs, irq); 551 if (offset & 7) { 552 *data = r >> 32; 553 } else { 554 *data = (uint32_t)r; 555 } 556 return true; 557 } 558 case GICD_IDREGS ... GICD_IDREGS + 0x2f: 559 /* ID registers */ 560 *data = gicv3_idreg(offset - GICD_IDREGS); 561 return true; 562 case GICD_SGIR: 563 /* WO registers, return unknown value */ 564 qemu_log_mask(LOG_GUEST_ERROR, 565 "%s: invalid guest read from WO register at offset " 566 TARGET_FMT_plx "\n", __func__, offset); 567 *data = 0; 568 return true; 569 default: 570 return false; 571 } 572 } 573 574 static bool gicd_writel(GICv3State *s, hwaddr offset, 575 uint64_t value, MemTxAttrs attrs) 576 { 577 /* Almost all GICv3 distributor registers are 32-bit. Note that 578 * RO registers must ignore writes, not abort. 579 */ 580 581 switch (offset) { 582 case GICD_CTLR: 583 { 584 uint32_t mask; 585 /* GICv3 5.3.20 */ 586 if (s->gicd_ctlr & GICD_CTLR_DS) { 587 /* With only one security state, E1NWF is RAZ/WI, DS is RAO/WI, 588 * ARE is RAO/WI (affinity routing always on), and only 589 * bits 0 and 1 (group enables) are writable. 590 */ 591 mask = GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1NS; 592 } else { 593 if (attrs.secure) { 594 /* for secure access: 595 * ARE_NS and ARE_S are RAO/WI (affinity routing always on) 596 * E1NWF is RAZ/WI (we don't support enable-1-of-n-wakeup) 597 * 598 * We can only modify bits[2:0] (the group enables). 599 */ 600 mask = GICD_CTLR_DS | GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1_ALL; 601 } else { 602 /* For non secure access ARE_NS is RAO/WI and EnableGrp1 603 * is RES0. The only writable bit is [1] (EnableGrp1A), which 604 * is an alias of the Secure bit [1]. 605 */ 606 mask = GICD_CTLR_EN_GRP1NS; 607 } 608 } 609 s->gicd_ctlr = (s->gicd_ctlr & ~mask) | (value & mask); 610 if (value & mask & GICD_CTLR_DS) { 611 /* We just set DS, so the ARE_NS and EnG1S bits are now RES0. 612 * Note that this is a one-way transition because if DS is set 613 * then it's not writeable, so it can only go back to 0 with a 614 * hardware reset. 615 */ 616 s->gicd_ctlr &= ~(GICD_CTLR_EN_GRP1S | GICD_CTLR_ARE_NS); 617 } 618 gicv3_full_update(s); 619 return true; 620 } 621 case GICD_STATUSR: 622 /* RAZ/WI for our implementation */ 623 return true; 624 case GICD_IGROUPR ... GICD_IGROUPR + 0x7f: 625 { 626 int irq; 627 628 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { 629 return true; 630 } 631 /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ 632 irq = (offset - GICD_IGROUPR) * 8; 633 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 634 return true; 635 } 636 *gic_bmp_ptr32(s->group, irq) = value; 637 gicv3_update(s, irq, 32); 638 return true; 639 } 640 case GICD_ISENABLER ... GICD_ISENABLER + 0x7f: 641 gicd_write_set_bitmap_reg(s, attrs, s->enabled, NULL, 642 offset - GICD_ISENABLER, value); 643 return true; 644 case GICD_ICENABLER ... GICD_ICENABLER + 0x7f: 645 gicd_write_clear_bitmap_reg(s, attrs, s->enabled, NULL, 646 offset - GICD_ICENABLER, value); 647 return true; 648 case GICD_ISPENDR ... GICD_ISPENDR + 0x7f: 649 gicd_write_set_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge1, 650 offset - GICD_ISPENDR, value); 651 return true; 652 case GICD_ICPENDR ... GICD_ICPENDR + 0x7f: 653 gicd_write_clear_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge2, 654 offset - GICD_ICPENDR, value); 655 return true; 656 case GICD_ISACTIVER ... GICD_ISACTIVER + 0x7f: 657 gicd_write_set_bitmap_reg(s, attrs, s->active, NULL, 658 offset - GICD_ISACTIVER, value); 659 return true; 660 case GICD_ICACTIVER ... GICD_ICACTIVER + 0x7f: 661 gicd_write_clear_bitmap_reg(s, attrs, s->active, NULL, 662 offset - GICD_ICACTIVER, value); 663 return true; 664 case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff: 665 { 666 int i, irq = offset - GICD_IPRIORITYR; 667 668 if (irq < GIC_INTERNAL || irq + 3 >= s->num_irq) { 669 return true; 670 } 671 672 for (i = irq; i < irq + 4; i++, value >>= 8) { 673 gicd_write_ipriorityr(s, attrs, i, value); 674 } 675 gicv3_update(s, irq, 4); 676 return true; 677 } 678 case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff: 679 /* RAZ/WI since affinity routing is always enabled */ 680 return true; 681 case GICD_ICFGR ... GICD_ICFGR + 0xff: 682 { 683 /* Here only the odd bits are used; even bits are RES0 */ 684 int irq = (offset - GICD_ICFGR) * 4; 685 uint32_t mask, oldval; 686 687 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 688 return true; 689 } 690 691 /* Since our edge_trigger bitmap is one bit per irq, our input 692 * 32-bits will compress down into 16 bits which we need 693 * to write into the bitmap. 694 */ 695 value = half_unshuffle32(value >> 1); 696 mask = mask_group_and_nsacr(s, attrs, NULL, irq & ~0x1f); 697 if (irq & 0x1f) { 698 value <<= 16; 699 mask &= 0xffff0000U; 700 } else { 701 mask &= 0xffff; 702 } 703 oldval = *gic_bmp_ptr32(s->edge_trigger, (irq & ~0x1f)); 704 value = (oldval & ~mask) | (value & mask); 705 *gic_bmp_ptr32(s->edge_trigger, irq & ~0x1f) = value; 706 return true; 707 } 708 case GICD_IGRPMODR ... GICD_IGRPMODR + 0xff: 709 { 710 int irq; 711 712 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) { 713 /* RAZ/WI if security disabled, or if 714 * security enabled and this is an NS access 715 */ 716 return true; 717 } 718 /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ 719 irq = (offset - GICD_IGRPMODR) * 8; 720 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 721 return true; 722 } 723 *gic_bmp_ptr32(s->grpmod, irq) = value; 724 gicv3_update(s, irq, 32); 725 return true; 726 } 727 case GICD_NSACR ... GICD_NSACR + 0xff: 728 { 729 /* Two bits per interrupt */ 730 int irq = (offset - GICD_NSACR) * 4; 731 732 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 733 return true; 734 } 735 736 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) { 737 /* RAZ/WI if security disabled, or if 738 * security enabled and this is an NS access 739 */ 740 return true; 741 } 742 743 s->gicd_nsacr[irq / 16] = value; 744 /* No update required as this only affects access permission checks */ 745 return true; 746 } 747 case GICD_SGIR: 748 /* RES0 if affinity routing is enabled */ 749 return true; 750 case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf: 751 case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf: 752 /* RAZ/WI since affinity routing is always enabled */ 753 return true; 754 case GICD_IROUTER ... GICD_IROUTER + 0x1fdf: 755 { 756 uint64_t r; 757 int irq = (offset - GICD_IROUTER) / 8; 758 759 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 760 return true; 761 } 762 763 /* Write half of the 64-bit register */ 764 r = gicd_read_irouter(s, attrs, irq); 765 r = deposit64(r, (offset & 7) ? 32 : 0, 32, value); 766 gicd_write_irouter(s, attrs, irq, r); 767 return true; 768 } 769 case GICD_IDREGS ... GICD_IDREGS + 0x2f: 770 case GICD_TYPER: 771 case GICD_IIDR: 772 /* RO registers, ignore the write */ 773 qemu_log_mask(LOG_GUEST_ERROR, 774 "%s: invalid guest write to RO register at offset " 775 TARGET_FMT_plx "\n", __func__, offset); 776 return true; 777 default: 778 return false; 779 } 780 } 781 782 static bool gicd_writeq(GICv3State *s, hwaddr offset, 783 uint64_t value, MemTxAttrs attrs) 784 { 785 /* Our only 64-bit registers are GICD_IROUTER<n> */ 786 int irq; 787 788 switch (offset) { 789 case GICD_IROUTER ... GICD_IROUTER + 0x1fdf: 790 irq = (offset - GICD_IROUTER) / 8; 791 gicd_write_irouter(s, attrs, irq, value); 792 return true; 793 default: 794 return false; 795 } 796 } 797 798 static bool gicd_readq(GICv3State *s, hwaddr offset, 799 uint64_t *data, MemTxAttrs attrs) 800 { 801 /* Our only 64-bit registers are GICD_IROUTER<n> */ 802 int irq; 803 804 switch (offset) { 805 case GICD_IROUTER ... GICD_IROUTER + 0x1fdf: 806 irq = (offset - GICD_IROUTER) / 8; 807 *data = gicd_read_irouter(s, attrs, irq); 808 return true; 809 default: 810 return false; 811 } 812 } 813 814 MemTxResult gicv3_dist_read(void *opaque, hwaddr offset, uint64_t *data, 815 unsigned size, MemTxAttrs attrs) 816 { 817 GICv3State *s = (GICv3State *)opaque; 818 bool r; 819 820 switch (size) { 821 case 1: 822 r = gicd_readb(s, offset, data, attrs); 823 break; 824 case 2: 825 r = gicd_readw(s, offset, data, attrs); 826 break; 827 case 4: 828 r = gicd_readl(s, offset, data, attrs); 829 break; 830 case 8: 831 r = gicd_readq(s, offset, data, attrs); 832 break; 833 default: 834 r = false; 835 break; 836 } 837 838 if (!r) { 839 qemu_log_mask(LOG_GUEST_ERROR, 840 "%s: invalid guest read at offset " TARGET_FMT_plx 841 " size %u\n", __func__, offset, size); 842 trace_gicv3_dist_badread(offset, size, attrs.secure); 843 /* The spec requires that reserved registers are RAZ/WI; 844 * so use MEMTX_ERROR returns from leaf functions as a way to 845 * trigger the guest-error logging but don't return it to 846 * the caller, or we'll cause a spurious guest data abort. 847 */ 848 *data = 0; 849 } else { 850 trace_gicv3_dist_read(offset, *data, size, attrs.secure); 851 } 852 return MEMTX_OK; 853 } 854 855 MemTxResult gicv3_dist_write(void *opaque, hwaddr offset, uint64_t data, 856 unsigned size, MemTxAttrs attrs) 857 { 858 GICv3State *s = (GICv3State *)opaque; 859 bool r; 860 861 switch (size) { 862 case 1: 863 r = gicd_writeb(s, offset, data, attrs); 864 break; 865 case 2: 866 r = gicd_writew(s, offset, data, attrs); 867 break; 868 case 4: 869 r = gicd_writel(s, offset, data, attrs); 870 break; 871 case 8: 872 r = gicd_writeq(s, offset, data, attrs); 873 break; 874 default: 875 r = false; 876 break; 877 } 878 879 if (!r) { 880 qemu_log_mask(LOG_GUEST_ERROR, 881 "%s: invalid guest write at offset " TARGET_FMT_plx 882 " size %u\n", __func__, offset, size); 883 trace_gicv3_dist_badwrite(offset, data, size, attrs.secure); 884 /* The spec requires that reserved registers are RAZ/WI; 885 * so use MEMTX_ERROR returns from leaf functions as a way to 886 * trigger the guest-error logging but don't return it to 887 * the caller, or we'll cause a spurious guest data abort. 888 */ 889 } else { 890 trace_gicv3_dist_write(offset, data, size, attrs.secure); 891 } 892 return MEMTX_OK; 893 } 894 895 void gicv3_dist_set_irq(GICv3State *s, int irq, int level) 896 { 897 /* Update distributor state for a change in an external SPI input line */ 898 if (level == gicv3_gicd_level_test(s, irq)) { 899 return; 900 } 901 902 trace_gicv3_dist_set_irq(irq, level); 903 904 gicv3_gicd_level_replace(s, irq, level); 905 906 if (level) { 907 /* 0->1 edges latch the pending bit for edge-triggered interrupts */ 908 if (gicv3_gicd_edge_trigger_test(s, irq)) { 909 gicv3_gicd_pending_set(s, irq); 910 } 911 } 912 913 gicv3_update(s, irq, 1); 914 } 915