1 /* 2 * ARM GICv3 emulation: Distributor 3 * 4 * Copyright (c) 2015 Huawei. 5 * Copyright (c) 2016 Linaro Limited. 6 * Written by Shlomo Pongratz, Peter Maydell 7 * 8 * This code is licensed under the GPL, version 2 or (at your option) 9 * any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/log.h" 14 #include "trace.h" 15 #include "gicv3_internal.h" 16 17 /* The GICD_NSACR registers contain a two bit field for each interrupt which 18 * allows the guest to give NonSecure code access to registers controlling 19 * Secure interrupts: 20 * 0b00: no access (NS accesses to bits for Secure interrupts will RAZ/WI) 21 * 0b01: NS r/w accesses permitted to ISPENDR, SETSPI_NSR, SGIR 22 * 0b10: as 0b01, and also r/w to ICPENDR, r/o to ISACTIVER/ICACTIVER, 23 * and w/o to CLRSPI_NSR 24 * 0b11: as 0b10, and also r/w to IROUTER and ITARGETSR 25 * 26 * Given a (multiple-of-32) interrupt number, these mask functions return 27 * a mask word where each bit is 1 if the NSACR settings permit access 28 * to the interrupt. The mask returned can then be ORed with the GICD_GROUP 29 * word for this set of interrupts to give an overall mask. 30 */ 31 32 typedef uint32_t maskfn(GICv3State *s, int irq); 33 34 static uint32_t mask_nsacr_ge1(GICv3State *s, int irq) 35 { 36 /* Return a mask where each bit is set if the NSACR field is >= 1 */ 37 uint64_t raw_nsacr = s->gicd_nsacr[irq / 16 + 1]; 38 39 raw_nsacr = raw_nsacr << 32 | s->gicd_nsacr[irq / 16]; 40 raw_nsacr = (raw_nsacr >> 1) | raw_nsacr; 41 return half_unshuffle64(raw_nsacr); 42 } 43 44 static uint32_t mask_nsacr_ge2(GICv3State *s, int irq) 45 { 46 /* Return a mask where each bit is set if the NSACR field is >= 2 */ 47 uint64_t raw_nsacr = s->gicd_nsacr[irq / 16 + 1]; 48 49 raw_nsacr = raw_nsacr << 32 | s->gicd_nsacr[irq / 16]; 50 raw_nsacr = raw_nsacr >> 1; 51 return half_unshuffle64(raw_nsacr); 52 } 53 54 /* We don't need a mask_nsacr_ge3() because IROUTER<n> isn't a bitmap register, 55 * but it would be implemented using: 56 * raw_nsacr = (raw_nsacr >> 1) & raw_nsacr; 57 */ 58 59 static uint32_t mask_group_and_nsacr(GICv3State *s, MemTxAttrs attrs, 60 maskfn *maskfn, int irq) 61 { 62 /* Return a 32-bit mask which should be applied for this set of 32 63 * interrupts; each bit is 1 if access is permitted by the 64 * combination of attrs.secure, GICD_GROUPR and GICD_NSACR. 65 */ 66 uint32_t mask; 67 68 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { 69 /* bits for Group 0 or Secure Group 1 interrupts are RAZ/WI 70 * unless the NSACR bits permit access. 71 */ 72 mask = *gic_bmp_ptr32(s->group, irq); 73 if (maskfn) { 74 mask |= maskfn(s, irq); 75 } 76 return mask; 77 } 78 return 0xFFFFFFFFU; 79 } 80 81 static int gicd_ns_access(GICv3State *s, int irq) 82 { 83 /* Return the 2 bit NS_access<x> field from GICD_NSACR<n> for the 84 * specified interrupt. 85 */ 86 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 87 return 0; 88 } 89 return extract32(s->gicd_nsacr[irq / 16], (irq % 16) * 2, 2); 90 } 91 92 static void gicd_write_set_bitmap_reg(GICv3State *s, MemTxAttrs attrs, 93 uint32_t *bmp, 94 maskfn *maskfn, 95 int offset, uint32_t val) 96 { 97 /* Helper routine to implement writing to a "set-bitmap" register 98 * (GICD_ISENABLER, GICD_ISPENDR, etc). 99 * Semantics implemented here: 100 * RAZ/WI for SGIs, PPIs, unimplemented IRQs 101 * Bits corresponding to Group 0 or Secure Group 1 interrupts RAZ/WI. 102 * Writing 1 means "set bit in bitmap"; writing 0 is ignored. 103 * offset should be the offset in bytes of the register from the start 104 * of its group. 105 */ 106 int irq = offset * 8; 107 108 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 109 return; 110 } 111 val &= mask_group_and_nsacr(s, attrs, maskfn, irq); 112 *gic_bmp_ptr32(bmp, irq) |= val; 113 gicv3_update(s, irq, 32); 114 } 115 116 static void gicd_write_clear_bitmap_reg(GICv3State *s, MemTxAttrs attrs, 117 uint32_t *bmp, 118 maskfn *maskfn, 119 int offset, uint32_t val) 120 { 121 /* Helper routine to implement writing to a "clear-bitmap" register 122 * (GICD_ICENABLER, GICD_ICPENDR, etc). 123 * Semantics implemented here: 124 * RAZ/WI for SGIs, PPIs, unimplemented IRQs 125 * Bits corresponding to Group 0 or Secure Group 1 interrupts RAZ/WI. 126 * Writing 1 means "clear bit in bitmap"; writing 0 is ignored. 127 * offset should be the offset in bytes of the register from the start 128 * of its group. 129 */ 130 int irq = offset * 8; 131 132 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 133 return; 134 } 135 val &= mask_group_and_nsacr(s, attrs, maskfn, irq); 136 *gic_bmp_ptr32(bmp, irq) &= ~val; 137 gicv3_update(s, irq, 32); 138 } 139 140 static uint32_t gicd_read_bitmap_reg(GICv3State *s, MemTxAttrs attrs, 141 uint32_t *bmp, 142 maskfn *maskfn, 143 int offset) 144 { 145 /* Helper routine to implement reading a "set/clear-bitmap" register 146 * (GICD_ICENABLER, GICD_ISENABLER, GICD_ICPENDR, etc). 147 * Semantics implemented here: 148 * RAZ/WI for SGIs, PPIs, unimplemented IRQs 149 * Bits corresponding to Group 0 or Secure Group 1 interrupts RAZ/WI. 150 * offset should be the offset in bytes of the register from the start 151 * of its group. 152 */ 153 int irq = offset * 8; 154 uint32_t val; 155 156 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 157 return 0; 158 } 159 val = *gic_bmp_ptr32(bmp, irq); 160 if (bmp == s->pending) { 161 /* The PENDING register is a special case -- for level triggered 162 * interrupts, the PENDING state is the logical OR of the state of 163 * the PENDING latch with the input line level. 164 */ 165 uint32_t edge = *gic_bmp_ptr32(s->edge_trigger, irq); 166 uint32_t level = *gic_bmp_ptr32(s->level, irq); 167 val |= (~edge & level); 168 } 169 val &= mask_group_and_nsacr(s, attrs, maskfn, irq); 170 return val; 171 } 172 173 static uint8_t gicd_read_ipriorityr(GICv3State *s, MemTxAttrs attrs, int irq) 174 { 175 /* Read the value of GICD_IPRIORITYR<n> for the specified interrupt, 176 * honouring security state (these are RAZ/WI for Group 0 or Secure 177 * Group 1 interrupts). 178 */ 179 uint32_t prio; 180 181 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 182 return 0; 183 } 184 185 prio = s->gicd_ipriority[irq]; 186 187 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { 188 if (!gicv3_gicd_group_test(s, irq)) { 189 /* Fields for Group 0 or Secure Group 1 interrupts are RAZ/WI */ 190 return 0; 191 } 192 /* NS view of the interrupt priority */ 193 prio = (prio << 1) & 0xff; 194 } 195 return prio; 196 } 197 198 static void gicd_write_ipriorityr(GICv3State *s, MemTxAttrs attrs, int irq, 199 uint8_t value) 200 { 201 /* Write the value of GICD_IPRIORITYR<n> for the specified interrupt, 202 * honouring security state (these are RAZ/WI for Group 0 or Secure 203 * Group 1 interrupts). 204 */ 205 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 206 return; 207 } 208 209 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { 210 if (!gicv3_gicd_group_test(s, irq)) { 211 /* Fields for Group 0 or Secure Group 1 interrupts are RAZ/WI */ 212 return; 213 } 214 /* NS view of the interrupt priority */ 215 value = 0x80 | (value >> 1); 216 } 217 s->gicd_ipriority[irq] = value; 218 } 219 220 static uint64_t gicd_read_irouter(GICv3State *s, MemTxAttrs attrs, int irq) 221 { 222 /* Read the value of GICD_IROUTER<n> for the specified interrupt, 223 * honouring security state. 224 */ 225 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 226 return 0; 227 } 228 229 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { 230 /* RAZ/WI for NS accesses to secure interrupts */ 231 if (!gicv3_gicd_group_test(s, irq)) { 232 if (gicd_ns_access(s, irq) != 3) { 233 return 0; 234 } 235 } 236 } 237 238 return s->gicd_irouter[irq]; 239 } 240 241 static void gicd_write_irouter(GICv3State *s, MemTxAttrs attrs, int irq, 242 uint64_t val) 243 { 244 /* Write the value of GICD_IROUTER<n> for the specified interrupt, 245 * honouring security state. 246 */ 247 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 248 return; 249 } 250 251 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { 252 /* RAZ/WI for NS accesses to secure interrupts */ 253 if (!gicv3_gicd_group_test(s, irq)) { 254 if (gicd_ns_access(s, irq) != 3) { 255 return; 256 } 257 } 258 } 259 260 s->gicd_irouter[irq] = val; 261 gicv3_cache_target_cpustate(s, irq); 262 gicv3_update(s, irq, 1); 263 } 264 265 static MemTxResult gicd_readb(GICv3State *s, hwaddr offset, 266 uint64_t *data, MemTxAttrs attrs) 267 { 268 /* Most GICv3 distributor registers do not support byte accesses. */ 269 switch (offset) { 270 case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf: 271 case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf: 272 case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff: 273 /* This GIC implementation always has affinity routing enabled, 274 * so these registers are all RAZ/WI. 275 */ 276 return MEMTX_OK; 277 case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff: 278 *data = gicd_read_ipriorityr(s, attrs, offset - GICD_IPRIORITYR); 279 return MEMTX_OK; 280 default: 281 return MEMTX_ERROR; 282 } 283 } 284 285 static MemTxResult gicd_writeb(GICv3State *s, hwaddr offset, 286 uint64_t value, MemTxAttrs attrs) 287 { 288 /* Most GICv3 distributor registers do not support byte accesses. */ 289 switch (offset) { 290 case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf: 291 case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf: 292 case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff: 293 /* This GIC implementation always has affinity routing enabled, 294 * so these registers are all RAZ/WI. 295 */ 296 return MEMTX_OK; 297 case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff: 298 { 299 int irq = offset - GICD_IPRIORITYR; 300 301 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 302 return MEMTX_OK; 303 } 304 gicd_write_ipriorityr(s, attrs, irq, value); 305 gicv3_update(s, irq, 1); 306 return MEMTX_OK; 307 } 308 default: 309 return MEMTX_ERROR; 310 } 311 } 312 313 static MemTxResult gicd_readw(GICv3State *s, hwaddr offset, 314 uint64_t *data, MemTxAttrs attrs) 315 { 316 /* Only GICD_SETSPI_NSR, GICD_CLRSPI_NSR, GICD_SETSPI_SR and GICD_SETSPI_NSR 317 * support 16 bit accesses, and those registers are all part of the 318 * optional message-based SPI feature which this GIC does not currently 319 * implement (ie for us GICD_TYPER.MBIS == 0), so for us they are 320 * reserved. 321 */ 322 return MEMTX_ERROR; 323 } 324 325 static MemTxResult gicd_writew(GICv3State *s, hwaddr offset, 326 uint64_t value, MemTxAttrs attrs) 327 { 328 /* Only GICD_SETSPI_NSR, GICD_CLRSPI_NSR, GICD_SETSPI_SR and GICD_SETSPI_NSR 329 * support 16 bit accesses, and those registers are all part of the 330 * optional message-based SPI feature which this GIC does not currently 331 * implement (ie for us GICD_TYPER.MBIS == 0), so for us they are 332 * reserved. 333 */ 334 return MEMTX_ERROR; 335 } 336 337 static MemTxResult gicd_readl(GICv3State *s, hwaddr offset, 338 uint64_t *data, MemTxAttrs attrs) 339 { 340 /* Almost all GICv3 distributor registers are 32-bit. 341 * Note that WO registers must return an UNKNOWN value on reads, 342 * not an abort. 343 */ 344 345 switch (offset) { 346 case GICD_CTLR: 347 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { 348 /* The NS view of the GICD_CTLR sees only certain bits: 349 * + bit [31] (RWP) is an alias of the Secure bit [31] 350 * + bit [4] (ARE_NS) is an alias of Secure bit [5] 351 * + bit [1] (EnableGrp1A) is an alias of Secure bit [1] if 352 * NS affinity routing is enabled, otherwise RES0 353 * + bit [0] (EnableGrp1) is an alias of Secure bit [1] if 354 * NS affinity routing is not enabled, otherwise RES0 355 * Since for QEMU affinity routing is always enabled 356 * for both S and NS this means that bits [4] and [5] are 357 * both always 1, and we can simply make the NS view 358 * be bits 31, 4 and 1 of the S view. 359 */ 360 *data = s->gicd_ctlr & (GICD_CTLR_ARE_S | 361 GICD_CTLR_EN_GRP1NS | 362 GICD_CTLR_RWP); 363 } else { 364 *data = s->gicd_ctlr; 365 } 366 return MEMTX_OK; 367 case GICD_TYPER: 368 { 369 /* For this implementation: 370 * No1N == 1 (1-of-N SPI interrupts not supported) 371 * A3V == 1 (non-zero values of Affinity level 3 supported) 372 * IDbits == 0xf (we support 16-bit interrupt identifiers) 373 * DVIS == 0 (Direct virtual LPI injection not supported) 374 * LPIS == 0 (LPIs not supported) 375 * MBIS == 0 (message-based SPIs not supported) 376 * SecurityExtn == 1 if security extns supported 377 * CPUNumber == 0 since for us ARE is always 1 378 * ITLinesNumber == (num external irqs / 32) - 1 379 */ 380 int itlinesnumber = ((s->num_irq - GIC_INTERNAL) / 32) - 1; 381 /* 382 * SecurityExtn must be RAZ if GICD_CTLR.DS == 1, and 383 * "security extensions not supported" always implies DS == 1, 384 * so we only need to check the DS bit. 385 */ 386 bool sec_extn = !(s->gicd_ctlr & GICD_CTLR_DS); 387 388 *data = (1 << 25) | (1 << 24) | (sec_extn << 10) | 389 (0xf << 19) | itlinesnumber; 390 return MEMTX_OK; 391 } 392 case GICD_IIDR: 393 /* We claim to be an ARM r0p0 with a zero ProductID. 394 * This is the same as an r0p0 GIC-500. 395 */ 396 *data = gicv3_iidr(); 397 return MEMTX_OK; 398 case GICD_STATUSR: 399 /* RAZ/WI for us (this is an optional register and our implementation 400 * does not track RO/WO/reserved violations to report them to the guest) 401 */ 402 *data = 0; 403 return MEMTX_OK; 404 case GICD_IGROUPR ... GICD_IGROUPR + 0x7f: 405 { 406 int irq; 407 408 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { 409 *data = 0; 410 return MEMTX_OK; 411 } 412 /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ 413 irq = (offset - GICD_IGROUPR) * 8; 414 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 415 *data = 0; 416 return MEMTX_OK; 417 } 418 *data = *gic_bmp_ptr32(s->group, irq); 419 return MEMTX_OK; 420 } 421 case GICD_ISENABLER ... GICD_ISENABLER + 0x7f: 422 *data = gicd_read_bitmap_reg(s, attrs, s->enabled, NULL, 423 offset - GICD_ISENABLER); 424 return MEMTX_OK; 425 case GICD_ICENABLER ... GICD_ICENABLER + 0x7f: 426 *data = gicd_read_bitmap_reg(s, attrs, s->enabled, NULL, 427 offset - GICD_ICENABLER); 428 return MEMTX_OK; 429 case GICD_ISPENDR ... GICD_ISPENDR + 0x7f: 430 *data = gicd_read_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge1, 431 offset - GICD_ISPENDR); 432 return MEMTX_OK; 433 case GICD_ICPENDR ... GICD_ICPENDR + 0x7f: 434 *data = gicd_read_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge2, 435 offset - GICD_ICPENDR); 436 return MEMTX_OK; 437 case GICD_ISACTIVER ... GICD_ISACTIVER + 0x7f: 438 *data = gicd_read_bitmap_reg(s, attrs, s->active, mask_nsacr_ge2, 439 offset - GICD_ISACTIVER); 440 return MEMTX_OK; 441 case GICD_ICACTIVER ... GICD_ICACTIVER + 0x7f: 442 *data = gicd_read_bitmap_reg(s, attrs, s->active, mask_nsacr_ge2, 443 offset - GICD_ICACTIVER); 444 return MEMTX_OK; 445 case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff: 446 { 447 int i, irq = offset - GICD_IPRIORITYR; 448 uint32_t value = 0; 449 450 for (i = irq + 3; i >= irq; i--) { 451 value <<= 8; 452 value |= gicd_read_ipriorityr(s, attrs, i); 453 } 454 *data = value; 455 return MEMTX_OK; 456 } 457 case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff: 458 /* RAZ/WI since affinity routing is always enabled */ 459 *data = 0; 460 return MEMTX_OK; 461 case GICD_ICFGR ... GICD_ICFGR + 0xff: 462 { 463 /* Here only the even bits are used; odd bits are RES0 */ 464 int irq = (offset - GICD_ICFGR) * 4; 465 uint32_t value = 0; 466 467 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 468 *data = 0; 469 return MEMTX_OK; 470 } 471 472 /* Since our edge_trigger bitmap is one bit per irq, we only need 473 * half of the 32-bit word, which we can then spread out 474 * into the odd bits. 475 */ 476 value = *gic_bmp_ptr32(s->edge_trigger, irq & ~0x1f); 477 value &= mask_group_and_nsacr(s, attrs, NULL, irq & ~0x1f); 478 value = extract32(value, (irq & 0x1f) ? 16 : 0, 16); 479 value = half_shuffle32(value) << 1; 480 *data = value; 481 return MEMTX_OK; 482 } 483 case GICD_IGRPMODR ... GICD_IGRPMODR + 0xff: 484 { 485 int irq; 486 487 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) { 488 /* RAZ/WI if security disabled, or if 489 * security enabled and this is an NS access 490 */ 491 *data = 0; 492 return MEMTX_OK; 493 } 494 /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ 495 irq = (offset - GICD_IGRPMODR) * 8; 496 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 497 *data = 0; 498 return MEMTX_OK; 499 } 500 *data = *gic_bmp_ptr32(s->grpmod, irq); 501 return MEMTX_OK; 502 } 503 case GICD_NSACR ... GICD_NSACR + 0xff: 504 { 505 /* Two bits per interrupt */ 506 int irq = (offset - GICD_NSACR) * 4; 507 508 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 509 *data = 0; 510 return MEMTX_OK; 511 } 512 513 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) { 514 /* RAZ/WI if security disabled, or if 515 * security enabled and this is an NS access 516 */ 517 *data = 0; 518 return MEMTX_OK; 519 } 520 521 *data = s->gicd_nsacr[irq / 16]; 522 return MEMTX_OK; 523 } 524 case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf: 525 case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf: 526 /* RAZ/WI since affinity routing is always enabled */ 527 *data = 0; 528 return MEMTX_OK; 529 case GICD_IROUTER ... GICD_IROUTER + 0x1fdf: 530 { 531 uint64_t r; 532 int irq = (offset - GICD_IROUTER) / 8; 533 534 r = gicd_read_irouter(s, attrs, irq); 535 if (offset & 7) { 536 *data = r >> 32; 537 } else { 538 *data = (uint32_t)r; 539 } 540 return MEMTX_OK; 541 } 542 case GICD_IDREGS ... GICD_IDREGS + 0x2f: 543 /* ID registers */ 544 *data = gicv3_idreg(offset - GICD_IDREGS); 545 return MEMTX_OK; 546 case GICD_SGIR: 547 /* WO registers, return unknown value */ 548 qemu_log_mask(LOG_GUEST_ERROR, 549 "%s: invalid guest read from WO register at offset " 550 TARGET_FMT_plx "\n", __func__, offset); 551 *data = 0; 552 return MEMTX_OK; 553 default: 554 return MEMTX_ERROR; 555 } 556 } 557 558 static MemTxResult gicd_writel(GICv3State *s, hwaddr offset, 559 uint64_t value, MemTxAttrs attrs) 560 { 561 /* Almost all GICv3 distributor registers are 32-bit. Note that 562 * RO registers must ignore writes, not abort. 563 */ 564 565 switch (offset) { 566 case GICD_CTLR: 567 { 568 uint32_t mask; 569 /* GICv3 5.3.20 */ 570 if (s->gicd_ctlr & GICD_CTLR_DS) { 571 /* With only one security state, E1NWF is RAZ/WI, DS is RAO/WI, 572 * ARE is RAO/WI (affinity routing always on), and only 573 * bits 0 and 1 (group enables) are writable. 574 */ 575 mask = GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1NS; 576 } else { 577 if (attrs.secure) { 578 /* for secure access: 579 * ARE_NS and ARE_S are RAO/WI (affinity routing always on) 580 * E1NWF is RAZ/WI (we don't support enable-1-of-n-wakeup) 581 * 582 * We can only modify bits[2:0] (the group enables). 583 */ 584 mask = GICD_CTLR_DS | GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1_ALL; 585 } else { 586 /* For non secure access ARE_NS is RAO/WI and EnableGrp1 587 * is RES0. The only writable bit is [1] (EnableGrp1A), which 588 * is an alias of the Secure bit [1]. 589 */ 590 mask = GICD_CTLR_EN_GRP1NS; 591 } 592 } 593 s->gicd_ctlr = (s->gicd_ctlr & ~mask) | (value & mask); 594 if (value & mask & GICD_CTLR_DS) { 595 /* We just set DS, so the ARE_NS and EnG1S bits are now RES0. 596 * Note that this is a one-way transition because if DS is set 597 * then it's not writeable, so it can only go back to 0 with a 598 * hardware reset. 599 */ 600 s->gicd_ctlr &= ~(GICD_CTLR_EN_GRP1S | GICD_CTLR_ARE_NS); 601 } 602 gicv3_full_update(s); 603 return MEMTX_OK; 604 } 605 case GICD_STATUSR: 606 /* RAZ/WI for our implementation */ 607 return MEMTX_OK; 608 case GICD_IGROUPR ... GICD_IGROUPR + 0x7f: 609 { 610 int irq; 611 612 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { 613 return MEMTX_OK; 614 } 615 /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ 616 irq = (offset - GICD_IGROUPR) * 8; 617 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 618 return MEMTX_OK; 619 } 620 *gic_bmp_ptr32(s->group, irq) = value; 621 gicv3_update(s, irq, 32); 622 return MEMTX_OK; 623 } 624 case GICD_ISENABLER ... GICD_ISENABLER + 0x7f: 625 gicd_write_set_bitmap_reg(s, attrs, s->enabled, NULL, 626 offset - GICD_ISENABLER, value); 627 return MEMTX_OK; 628 case GICD_ICENABLER ... GICD_ICENABLER + 0x7f: 629 gicd_write_clear_bitmap_reg(s, attrs, s->enabled, NULL, 630 offset - GICD_ICENABLER, value); 631 return MEMTX_OK; 632 case GICD_ISPENDR ... GICD_ISPENDR + 0x7f: 633 gicd_write_set_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge1, 634 offset - GICD_ISPENDR, value); 635 return MEMTX_OK; 636 case GICD_ICPENDR ... GICD_ICPENDR + 0x7f: 637 gicd_write_clear_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge2, 638 offset - GICD_ICPENDR, value); 639 return MEMTX_OK; 640 case GICD_ISACTIVER ... GICD_ISACTIVER + 0x7f: 641 gicd_write_set_bitmap_reg(s, attrs, s->active, NULL, 642 offset - GICD_ISACTIVER, value); 643 return MEMTX_OK; 644 case GICD_ICACTIVER ... GICD_ICACTIVER + 0x7f: 645 gicd_write_clear_bitmap_reg(s, attrs, s->active, NULL, 646 offset - GICD_ICACTIVER, value); 647 return MEMTX_OK; 648 case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff: 649 { 650 int i, irq = offset - GICD_IPRIORITYR; 651 652 if (irq < GIC_INTERNAL || irq + 3 >= s->num_irq) { 653 return MEMTX_OK; 654 } 655 656 for (i = irq; i < irq + 4; i++, value >>= 8) { 657 gicd_write_ipriorityr(s, attrs, i, value); 658 } 659 gicv3_update(s, irq, 4); 660 return MEMTX_OK; 661 } 662 case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff: 663 /* RAZ/WI since affinity routing is always enabled */ 664 return MEMTX_OK; 665 case GICD_ICFGR ... GICD_ICFGR + 0xff: 666 { 667 /* Here only the odd bits are used; even bits are RES0 */ 668 int irq = (offset - GICD_ICFGR) * 4; 669 uint32_t mask, oldval; 670 671 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 672 return MEMTX_OK; 673 } 674 675 /* Since our edge_trigger bitmap is one bit per irq, our input 676 * 32-bits will compress down into 16 bits which we need 677 * to write into the bitmap. 678 */ 679 value = half_unshuffle32(value >> 1); 680 mask = mask_group_and_nsacr(s, attrs, NULL, irq & ~0x1f); 681 if (irq & 0x1f) { 682 value <<= 16; 683 mask &= 0xffff0000U; 684 } else { 685 mask &= 0xffff; 686 } 687 oldval = *gic_bmp_ptr32(s->edge_trigger, (irq & ~0x1f)); 688 value = (oldval & ~mask) | (value & mask); 689 *gic_bmp_ptr32(s->edge_trigger, irq & ~0x1f) = value; 690 return MEMTX_OK; 691 } 692 case GICD_IGRPMODR ... GICD_IGRPMODR + 0xff: 693 { 694 int irq; 695 696 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) { 697 /* RAZ/WI if security disabled, or if 698 * security enabled and this is an NS access 699 */ 700 return MEMTX_OK; 701 } 702 /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ 703 irq = (offset - GICD_IGRPMODR) * 8; 704 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 705 return MEMTX_OK; 706 } 707 *gic_bmp_ptr32(s->grpmod, irq) = value; 708 gicv3_update(s, irq, 32); 709 return MEMTX_OK; 710 } 711 case GICD_NSACR ... GICD_NSACR + 0xff: 712 { 713 /* Two bits per interrupt */ 714 int irq = (offset - GICD_NSACR) * 4; 715 716 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 717 return MEMTX_OK; 718 } 719 720 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) { 721 /* RAZ/WI if security disabled, or if 722 * security enabled and this is an NS access 723 */ 724 return MEMTX_OK; 725 } 726 727 s->gicd_nsacr[irq / 16] = value; 728 /* No update required as this only affects access permission checks */ 729 return MEMTX_OK; 730 } 731 case GICD_SGIR: 732 /* RES0 if affinity routing is enabled */ 733 return MEMTX_OK; 734 case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf: 735 case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf: 736 /* RAZ/WI since affinity routing is always enabled */ 737 return MEMTX_OK; 738 case GICD_IROUTER ... GICD_IROUTER + 0x1fdf: 739 { 740 uint64_t r; 741 int irq = (offset - GICD_IROUTER) / 8; 742 743 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 744 return MEMTX_OK; 745 } 746 747 /* Write half of the 64-bit register */ 748 r = gicd_read_irouter(s, attrs, irq); 749 r = deposit64(r, (offset & 7) ? 32 : 0, 32, value); 750 gicd_write_irouter(s, attrs, irq, r); 751 return MEMTX_OK; 752 } 753 case GICD_IDREGS ... GICD_IDREGS + 0x2f: 754 case GICD_TYPER: 755 case GICD_IIDR: 756 /* RO registers, ignore the write */ 757 qemu_log_mask(LOG_GUEST_ERROR, 758 "%s: invalid guest write to RO register at offset " 759 TARGET_FMT_plx "\n", __func__, offset); 760 return MEMTX_OK; 761 default: 762 return MEMTX_ERROR; 763 } 764 } 765 766 static MemTxResult gicd_writell(GICv3State *s, hwaddr offset, 767 uint64_t value, MemTxAttrs attrs) 768 { 769 /* Our only 64-bit registers are GICD_IROUTER<n> */ 770 int irq; 771 772 switch (offset) { 773 case GICD_IROUTER ... GICD_IROUTER + 0x1fdf: 774 irq = (offset - GICD_IROUTER) / 8; 775 gicd_write_irouter(s, attrs, irq, value); 776 return MEMTX_OK; 777 default: 778 return MEMTX_ERROR; 779 } 780 } 781 782 static MemTxResult gicd_readll(GICv3State *s, hwaddr offset, 783 uint64_t *data, MemTxAttrs attrs) 784 { 785 /* Our only 64-bit registers are GICD_IROUTER<n> */ 786 int irq; 787 788 switch (offset) { 789 case GICD_IROUTER ... GICD_IROUTER + 0x1fdf: 790 irq = (offset - GICD_IROUTER) / 8; 791 *data = gicd_read_irouter(s, attrs, irq); 792 return MEMTX_OK; 793 default: 794 return MEMTX_ERROR; 795 } 796 } 797 798 MemTxResult gicv3_dist_read(void *opaque, hwaddr offset, uint64_t *data, 799 unsigned size, MemTxAttrs attrs) 800 { 801 GICv3State *s = (GICv3State *)opaque; 802 MemTxResult r; 803 804 switch (size) { 805 case 1: 806 r = gicd_readb(s, offset, data, attrs); 807 break; 808 case 2: 809 r = gicd_readw(s, offset, data, attrs); 810 break; 811 case 4: 812 r = gicd_readl(s, offset, data, attrs); 813 break; 814 case 8: 815 r = gicd_readll(s, offset, data, attrs); 816 break; 817 default: 818 r = MEMTX_ERROR; 819 break; 820 } 821 822 if (r == MEMTX_ERROR) { 823 qemu_log_mask(LOG_GUEST_ERROR, 824 "%s: invalid guest read at offset " TARGET_FMT_plx 825 "size %u\n", __func__, offset, size); 826 trace_gicv3_dist_badread(offset, size, attrs.secure); 827 /* The spec requires that reserved registers are RAZ/WI; 828 * so use MEMTX_ERROR returns from leaf functions as a way to 829 * trigger the guest-error logging but don't return it to 830 * the caller, or we'll cause a spurious guest data abort. 831 */ 832 r = MEMTX_OK; 833 *data = 0; 834 } else { 835 trace_gicv3_dist_read(offset, *data, size, attrs.secure); 836 } 837 return r; 838 } 839 840 MemTxResult gicv3_dist_write(void *opaque, hwaddr offset, uint64_t data, 841 unsigned size, MemTxAttrs attrs) 842 { 843 GICv3State *s = (GICv3State *)opaque; 844 MemTxResult r; 845 846 switch (size) { 847 case 1: 848 r = gicd_writeb(s, offset, data, attrs); 849 break; 850 case 2: 851 r = gicd_writew(s, offset, data, attrs); 852 break; 853 case 4: 854 r = gicd_writel(s, offset, data, attrs); 855 break; 856 case 8: 857 r = gicd_writell(s, offset, data, attrs); 858 break; 859 default: 860 r = MEMTX_ERROR; 861 break; 862 } 863 864 if (r == MEMTX_ERROR) { 865 qemu_log_mask(LOG_GUEST_ERROR, 866 "%s: invalid guest write at offset " TARGET_FMT_plx 867 "size %u\n", __func__, offset, size); 868 trace_gicv3_dist_badwrite(offset, data, size, attrs.secure); 869 /* The spec requires that reserved registers are RAZ/WI; 870 * so use MEMTX_ERROR returns from leaf functions as a way to 871 * trigger the guest-error logging but don't return it to 872 * the caller, or we'll cause a spurious guest data abort. 873 */ 874 r = MEMTX_OK; 875 } else { 876 trace_gicv3_dist_write(offset, data, size, attrs.secure); 877 } 878 return r; 879 } 880 881 void gicv3_dist_set_irq(GICv3State *s, int irq, int level) 882 { 883 /* Update distributor state for a change in an external SPI input line */ 884 if (level == gicv3_gicd_level_test(s, irq)) { 885 return; 886 } 887 888 trace_gicv3_dist_set_irq(irq, level); 889 890 gicv3_gicd_level_replace(s, irq, level); 891 892 if (level) { 893 /* 0->1 edges latch the pending bit for edge-triggered interrupts */ 894 if (gicv3_gicd_edge_trigger_test(s, irq)) { 895 gicv3_gicd_pending_set(s, irq); 896 } 897 } 898 899 gicv3_update(s, irq, 1); 900 } 901