1 /* 2 * ARM GICv3 support - common bits of emulated and KVM kernel model 3 * 4 * Copyright (c) 2012 Linaro Limited 5 * Copyright (c) 2015 Huawei. 6 * Copyright (c) 2015 Samsung Electronics Co., Ltd. 7 * Written by Peter Maydell 8 * Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation, either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qom/cpu.h" 27 #include "hw/intc/arm_gicv3_common.h" 28 #include "gicv3_internal.h" 29 #include "hw/arm/linux-boot-if.h" 30 31 static int gicv3_pre_save(void *opaque) 32 { 33 GICv3State *s = (GICv3State *)opaque; 34 ARMGICv3CommonClass *c = ARM_GICV3_COMMON_GET_CLASS(s); 35 36 if (c->pre_save) { 37 c->pre_save(s); 38 } 39 40 return 0; 41 } 42 43 static int gicv3_post_load(void *opaque, int version_id) 44 { 45 GICv3State *s = (GICv3State *)opaque; 46 ARMGICv3CommonClass *c = ARM_GICV3_COMMON_GET_CLASS(s); 47 48 if (c->post_load) { 49 c->post_load(s); 50 } 51 return 0; 52 } 53 54 static bool virt_state_needed(void *opaque) 55 { 56 GICv3CPUState *cs = opaque; 57 58 return cs->num_list_regs != 0; 59 } 60 61 static const VMStateDescription vmstate_gicv3_cpu_virt = { 62 .name = "arm_gicv3_cpu/virt", 63 .version_id = 1, 64 .minimum_version_id = 1, 65 .needed = virt_state_needed, 66 .fields = (VMStateField[]) { 67 VMSTATE_UINT64_2DARRAY(ich_apr, GICv3CPUState, 3, 4), 68 VMSTATE_UINT64(ich_hcr_el2, GICv3CPUState), 69 VMSTATE_UINT64_ARRAY(ich_lr_el2, GICv3CPUState, GICV3_LR_MAX), 70 VMSTATE_UINT64(ich_vmcr_el2, GICv3CPUState), 71 VMSTATE_END_OF_LIST() 72 } 73 }; 74 75 static int icc_sre_el1_reg_pre_load(void *opaque) 76 { 77 GICv3CPUState *cs = opaque; 78 79 /* 80 * If the sre_el1 subsection is not transferred this 81 * means SRE_EL1 is 0x7 (which might not be the same as 82 * our reset value). 83 */ 84 cs->icc_sre_el1 = 0x7; 85 return 0; 86 } 87 88 static bool icc_sre_el1_reg_needed(void *opaque) 89 { 90 GICv3CPUState *cs = opaque; 91 92 return cs->icc_sre_el1 != 7; 93 } 94 95 const VMStateDescription vmstate_gicv3_cpu_sre_el1 = { 96 .name = "arm_gicv3_cpu/sre_el1", 97 .version_id = 1, 98 .minimum_version_id = 1, 99 .pre_load = icc_sre_el1_reg_pre_load, 100 .needed = icc_sre_el1_reg_needed, 101 .fields = (VMStateField[]) { 102 VMSTATE_UINT64(icc_sre_el1, GICv3CPUState), 103 VMSTATE_END_OF_LIST() 104 } 105 }; 106 107 static const VMStateDescription vmstate_gicv3_cpu = { 108 .name = "arm_gicv3_cpu", 109 .version_id = 1, 110 .minimum_version_id = 1, 111 .fields = (VMStateField[]) { 112 VMSTATE_UINT32(level, GICv3CPUState), 113 VMSTATE_UINT32(gicr_ctlr, GICv3CPUState), 114 VMSTATE_UINT32_ARRAY(gicr_statusr, GICv3CPUState, 2), 115 VMSTATE_UINT32(gicr_waker, GICv3CPUState), 116 VMSTATE_UINT64(gicr_propbaser, GICv3CPUState), 117 VMSTATE_UINT64(gicr_pendbaser, GICv3CPUState), 118 VMSTATE_UINT32(gicr_igroupr0, GICv3CPUState), 119 VMSTATE_UINT32(gicr_ienabler0, GICv3CPUState), 120 VMSTATE_UINT32(gicr_ipendr0, GICv3CPUState), 121 VMSTATE_UINT32(gicr_iactiver0, GICv3CPUState), 122 VMSTATE_UINT32(edge_trigger, GICv3CPUState), 123 VMSTATE_UINT32(gicr_igrpmodr0, GICv3CPUState), 124 VMSTATE_UINT32(gicr_nsacr, GICv3CPUState), 125 VMSTATE_UINT8_ARRAY(gicr_ipriorityr, GICv3CPUState, GIC_INTERNAL), 126 VMSTATE_UINT64_ARRAY(icc_ctlr_el1, GICv3CPUState, 2), 127 VMSTATE_UINT64(icc_pmr_el1, GICv3CPUState), 128 VMSTATE_UINT64_ARRAY(icc_bpr, GICv3CPUState, 3), 129 VMSTATE_UINT64_2DARRAY(icc_apr, GICv3CPUState, 3, 4), 130 VMSTATE_UINT64_ARRAY(icc_igrpen, GICv3CPUState, 3), 131 VMSTATE_UINT64(icc_ctlr_el3, GICv3CPUState), 132 VMSTATE_END_OF_LIST() 133 }, 134 .subsections = (const VMStateDescription * []) { 135 &vmstate_gicv3_cpu_virt, 136 NULL 137 }, 138 .subsections = (const VMStateDescription * []) { 139 &vmstate_gicv3_cpu_sre_el1, 140 NULL 141 } 142 }; 143 144 static const VMStateDescription vmstate_gicv3 = { 145 .name = "arm_gicv3", 146 .version_id = 1, 147 .minimum_version_id = 1, 148 .pre_save = gicv3_pre_save, 149 .post_load = gicv3_post_load, 150 .priority = MIG_PRI_GICV3, 151 .fields = (VMStateField[]) { 152 VMSTATE_UINT32(gicd_ctlr, GICv3State), 153 VMSTATE_UINT32_ARRAY(gicd_statusr, GICv3State, 2), 154 VMSTATE_UINT32_ARRAY(group, GICv3State, GICV3_BMP_SIZE), 155 VMSTATE_UINT32_ARRAY(grpmod, GICv3State, GICV3_BMP_SIZE), 156 VMSTATE_UINT32_ARRAY(enabled, GICv3State, GICV3_BMP_SIZE), 157 VMSTATE_UINT32_ARRAY(pending, GICv3State, GICV3_BMP_SIZE), 158 VMSTATE_UINT32_ARRAY(active, GICv3State, GICV3_BMP_SIZE), 159 VMSTATE_UINT32_ARRAY(level, GICv3State, GICV3_BMP_SIZE), 160 VMSTATE_UINT32_ARRAY(edge_trigger, GICv3State, GICV3_BMP_SIZE), 161 VMSTATE_UINT8_ARRAY(gicd_ipriority, GICv3State, GICV3_MAXIRQ), 162 VMSTATE_UINT64_ARRAY(gicd_irouter, GICv3State, GICV3_MAXIRQ), 163 VMSTATE_UINT32_ARRAY(gicd_nsacr, GICv3State, 164 DIV_ROUND_UP(GICV3_MAXIRQ, 16)), 165 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, GICv3State, num_cpu, 166 vmstate_gicv3_cpu, GICv3CPUState), 167 VMSTATE_END_OF_LIST() 168 } 169 }; 170 171 void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler, 172 const MemoryRegionOps *ops) 173 { 174 SysBusDevice *sbd = SYS_BUS_DEVICE(s); 175 int i; 176 177 /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU. 178 * GPIO array layout is thus: 179 * [0..N-1] spi 180 * [N..N+31] PPIs for CPU 0 181 * [N+32..N+63] PPIs for CPU 1 182 * ... 183 */ 184 i = s->num_irq - GIC_INTERNAL + GIC_INTERNAL * s->num_cpu; 185 qdev_init_gpio_in(DEVICE(s), handler, i); 186 187 for (i = 0; i < s->num_cpu; i++) { 188 sysbus_init_irq(sbd, &s->cpu[i].parent_irq); 189 } 190 for (i = 0; i < s->num_cpu; i++) { 191 sysbus_init_irq(sbd, &s->cpu[i].parent_fiq); 192 } 193 for (i = 0; i < s->num_cpu; i++) { 194 sysbus_init_irq(sbd, &s->cpu[i].parent_virq); 195 } 196 for (i = 0; i < s->num_cpu; i++) { 197 sysbus_init_irq(sbd, &s->cpu[i].parent_vfiq); 198 } 199 200 memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s, 201 "gicv3_dist", 0x10000); 202 memory_region_init_io(&s->iomem_redist, OBJECT(s), ops ? &ops[1] : NULL, s, 203 "gicv3_redist", 0x20000 * s->num_cpu); 204 205 sysbus_init_mmio(sbd, &s->iomem_dist); 206 sysbus_init_mmio(sbd, &s->iomem_redist); 207 } 208 209 static void arm_gicv3_common_realize(DeviceState *dev, Error **errp) 210 { 211 GICv3State *s = ARM_GICV3_COMMON(dev); 212 int i; 213 214 /* revision property is actually reserved and currently used only in order 215 * to keep the interface compatible with GICv2 code, avoiding extra 216 * conditions. However, in future it could be used, for example, if we 217 * implement GICv4. 218 */ 219 if (s->revision != 3) { 220 error_setg(errp, "unsupported GIC revision %d", s->revision); 221 return; 222 } 223 224 if (s->num_irq > GICV3_MAXIRQ) { 225 error_setg(errp, 226 "requested %u interrupt lines exceeds GIC maximum %d", 227 s->num_irq, GICV3_MAXIRQ); 228 return; 229 } 230 if (s->num_irq < GIC_INTERNAL) { 231 error_setg(errp, 232 "requested %u interrupt lines is below GIC minimum %d", 233 s->num_irq, GIC_INTERNAL); 234 return; 235 } 236 237 /* ITLinesNumber is represented as (N / 32) - 1, so this is an 238 * implementation imposed restriction, not an architectural one, 239 * so we don't have to deal with bitfields where only some of the 240 * bits in a 32-bit word should be valid. 241 */ 242 if (s->num_irq % 32) { 243 error_setg(errp, 244 "%d interrupt lines unsupported: not divisible by 32", 245 s->num_irq); 246 return; 247 } 248 249 s->cpu = g_new0(GICv3CPUState, s->num_cpu); 250 251 for (i = 0; i < s->num_cpu; i++) { 252 CPUState *cpu = qemu_get_cpu(i); 253 uint64_t cpu_affid; 254 int last; 255 256 s->cpu[i].cpu = cpu; 257 s->cpu[i].gic = s; 258 /* Store GICv3CPUState in CPUARMState gicv3state pointer */ 259 gicv3_set_gicv3state(cpu, &s->cpu[i]); 260 261 /* Pre-construct the GICR_TYPER: 262 * For our implementation: 263 * Top 32 bits are the affinity value of the associated CPU 264 * CommonLPIAff == 01 (redistributors with same Aff3 share LPI table) 265 * Processor_Number == CPU index starting from 0 266 * DPGS == 0 (GICR_CTLR.DPG* not supported) 267 * Last == 1 if this is the last redistributor in a series of 268 * contiguous redistributor pages 269 * DirectLPI == 0 (direct injection of LPIs not supported) 270 * VLPIS == 0 (virtual LPIs not supported) 271 * PLPIS == 0 (physical LPIs not supported) 272 */ 273 cpu_affid = object_property_get_uint(OBJECT(cpu), "mp-affinity", NULL); 274 last = (i == s->num_cpu - 1); 275 276 /* The CPU mp-affinity property is in MPIDR register format; squash 277 * the affinity bytes into 32 bits as the GICR_TYPER has them. 278 */ 279 cpu_affid = ((cpu_affid & 0xFF00000000ULL) >> 8) | 280 (cpu_affid & 0xFFFFFF); 281 s->cpu[i].gicr_typer = (cpu_affid << 32) | 282 (1 << 24) | 283 (i << 8) | 284 (last << 4); 285 } 286 } 287 288 static void arm_gicv3_common_reset(DeviceState *dev) 289 { 290 GICv3State *s = ARM_GICV3_COMMON(dev); 291 int i; 292 293 for (i = 0; i < s->num_cpu; i++) { 294 GICv3CPUState *cs = &s->cpu[i]; 295 296 cs->level = 0; 297 cs->gicr_ctlr = 0; 298 cs->gicr_statusr[GICV3_S] = 0; 299 cs->gicr_statusr[GICV3_NS] = 0; 300 cs->gicr_waker = GICR_WAKER_ProcessorSleep | GICR_WAKER_ChildrenAsleep; 301 cs->gicr_propbaser = 0; 302 cs->gicr_pendbaser = 0; 303 /* If we're resetting a TZ-aware GIC as if secure firmware 304 * had set it up ready to start a kernel in non-secure, we 305 * need to set interrupts to group 1 so the kernel can use them. 306 * Otherwise they reset to group 0 like the hardware. 307 */ 308 if (s->irq_reset_nonsecure) { 309 cs->gicr_igroupr0 = 0xffffffff; 310 } else { 311 cs->gicr_igroupr0 = 0; 312 } 313 314 cs->gicr_ienabler0 = 0; 315 cs->gicr_ipendr0 = 0; 316 cs->gicr_iactiver0 = 0; 317 cs->edge_trigger = 0xffff; 318 cs->gicr_igrpmodr0 = 0; 319 cs->gicr_nsacr = 0; 320 memset(cs->gicr_ipriorityr, 0, sizeof(cs->gicr_ipriorityr)); 321 322 cs->hppi.prio = 0xff; 323 324 /* State in the CPU interface must *not* be reset here, because it 325 * is part of the CPU's reset domain, not the GIC device's. 326 */ 327 } 328 329 /* For our implementation affinity routing is always enabled */ 330 if (s->security_extn) { 331 s->gicd_ctlr = GICD_CTLR_ARE_S | GICD_CTLR_ARE_NS; 332 } else { 333 s->gicd_ctlr = GICD_CTLR_DS | GICD_CTLR_ARE; 334 } 335 336 s->gicd_statusr[GICV3_S] = 0; 337 s->gicd_statusr[GICV3_NS] = 0; 338 339 memset(s->group, 0, sizeof(s->group)); 340 memset(s->grpmod, 0, sizeof(s->grpmod)); 341 memset(s->enabled, 0, sizeof(s->enabled)); 342 memset(s->pending, 0, sizeof(s->pending)); 343 memset(s->active, 0, sizeof(s->active)); 344 memset(s->level, 0, sizeof(s->level)); 345 memset(s->edge_trigger, 0, sizeof(s->edge_trigger)); 346 memset(s->gicd_ipriority, 0, sizeof(s->gicd_ipriority)); 347 memset(s->gicd_irouter, 0, sizeof(s->gicd_irouter)); 348 memset(s->gicd_nsacr, 0, sizeof(s->gicd_nsacr)); 349 /* GICD_IROUTER are UNKNOWN at reset so in theory the guest must 350 * write these to get sane behaviour and we need not populate the 351 * pointer cache here; however having the cache be different for 352 * "happened to be 0 from reset" and "guest wrote 0" would be 353 * too confusing. 354 */ 355 gicv3_cache_all_target_cpustates(s); 356 357 if (s->irq_reset_nonsecure) { 358 /* If we're resetting a TZ-aware GIC as if secure firmware 359 * had set it up ready to start a kernel in non-secure, we 360 * need to set interrupts to group 1 so the kernel can use them. 361 * Otherwise they reset to group 0 like the hardware. 362 */ 363 for (i = GIC_INTERNAL; i < s->num_irq; i++) { 364 gicv3_gicd_group_set(s, i); 365 } 366 } 367 } 368 369 static void arm_gic_common_linux_init(ARMLinuxBootIf *obj, 370 bool secure_boot) 371 { 372 GICv3State *s = ARM_GICV3_COMMON(obj); 373 374 if (s->security_extn && !secure_boot) { 375 /* We're directly booting a kernel into NonSecure. If this GIC 376 * implements the security extensions then we must configure it 377 * to have all the interrupts be NonSecure (this is a job that 378 * is done by the Secure boot firmware in real hardware, and in 379 * this mode QEMU is acting as a minimalist firmware-and-bootloader 380 * equivalent). 381 */ 382 s->irq_reset_nonsecure = true; 383 } 384 } 385 386 static Property arm_gicv3_common_properties[] = { 387 DEFINE_PROP_UINT32("num-cpu", GICv3State, num_cpu, 1), 388 DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32), 389 DEFINE_PROP_UINT32("revision", GICv3State, revision, 3), 390 DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0), 391 DEFINE_PROP_END_OF_LIST(), 392 }; 393 394 static void arm_gicv3_common_class_init(ObjectClass *klass, void *data) 395 { 396 DeviceClass *dc = DEVICE_CLASS(klass); 397 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass); 398 399 dc->reset = arm_gicv3_common_reset; 400 dc->realize = arm_gicv3_common_realize; 401 dc->props = arm_gicv3_common_properties; 402 dc->vmsd = &vmstate_gicv3; 403 albifc->arm_linux_init = arm_gic_common_linux_init; 404 } 405 406 static const TypeInfo arm_gicv3_common_type = { 407 .name = TYPE_ARM_GICV3_COMMON, 408 .parent = TYPE_SYS_BUS_DEVICE, 409 .instance_size = sizeof(GICv3State), 410 .class_size = sizeof(ARMGICv3CommonClass), 411 .class_init = arm_gicv3_common_class_init, 412 .abstract = true, 413 .interfaces = (InterfaceInfo []) { 414 { TYPE_ARM_LINUX_BOOT_IF }, 415 { }, 416 }, 417 }; 418 419 static void register_types(void) 420 { 421 type_register_static(&arm_gicv3_common_type); 422 } 423 424 type_init(register_types) 425