1 /* 2 * ARM GICv3 support - common bits of emulated and KVM kernel model 3 * 4 * Copyright (c) 2012 Linaro Limited 5 * Copyright (c) 2015 Huawei. 6 * Copyright (c) 2015 Samsung Electronics Co., Ltd. 7 * Written by Peter Maydell 8 * Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation, either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qom/cpu.h" 27 #include "hw/intc/arm_gicv3_common.h" 28 #include "gicv3_internal.h" 29 #include "hw/arm/linux-boot-if.h" 30 31 static void gicv3_pre_save(void *opaque) 32 { 33 GICv3State *s = (GICv3State *)opaque; 34 ARMGICv3CommonClass *c = ARM_GICV3_COMMON_GET_CLASS(s); 35 36 if (c->pre_save) { 37 c->pre_save(s); 38 } 39 } 40 41 static int gicv3_post_load(void *opaque, int version_id) 42 { 43 GICv3State *s = (GICv3State *)opaque; 44 ARMGICv3CommonClass *c = ARM_GICV3_COMMON_GET_CLASS(s); 45 46 if (c->post_load) { 47 c->post_load(s); 48 } 49 return 0; 50 } 51 52 static bool virt_state_needed(void *opaque) 53 { 54 GICv3CPUState *cs = opaque; 55 56 return cs->num_list_regs != 0; 57 } 58 59 static const VMStateDescription vmstate_gicv3_cpu_virt = { 60 .name = "arm_gicv3_cpu/virt", 61 .version_id = 1, 62 .minimum_version_id = 1, 63 .needed = virt_state_needed, 64 .fields = (VMStateField[]) { 65 VMSTATE_UINT64_2DARRAY(ich_apr, GICv3CPUState, 3, 4), 66 VMSTATE_UINT64(ich_hcr_el2, GICv3CPUState), 67 VMSTATE_UINT64_ARRAY(ich_lr_el2, GICv3CPUState, GICV3_LR_MAX), 68 VMSTATE_UINT64(ich_vmcr_el2, GICv3CPUState), 69 VMSTATE_END_OF_LIST() 70 } 71 }; 72 73 static const VMStateDescription vmstate_gicv3_cpu = { 74 .name = "arm_gicv3_cpu", 75 .version_id = 1, 76 .minimum_version_id = 1, 77 .fields = (VMStateField[]) { 78 VMSTATE_UINT32(level, GICv3CPUState), 79 VMSTATE_UINT32(gicr_ctlr, GICv3CPUState), 80 VMSTATE_UINT32_ARRAY(gicr_statusr, GICv3CPUState, 2), 81 VMSTATE_UINT32(gicr_waker, GICv3CPUState), 82 VMSTATE_UINT64(gicr_propbaser, GICv3CPUState), 83 VMSTATE_UINT64(gicr_pendbaser, GICv3CPUState), 84 VMSTATE_UINT32(gicr_igroupr0, GICv3CPUState), 85 VMSTATE_UINT32(gicr_ienabler0, GICv3CPUState), 86 VMSTATE_UINT32(gicr_ipendr0, GICv3CPUState), 87 VMSTATE_UINT32(gicr_iactiver0, GICv3CPUState), 88 VMSTATE_UINT32(edge_trigger, GICv3CPUState), 89 VMSTATE_UINT32(gicr_igrpmodr0, GICv3CPUState), 90 VMSTATE_UINT32(gicr_nsacr, GICv3CPUState), 91 VMSTATE_UINT8_ARRAY(gicr_ipriorityr, GICv3CPUState, GIC_INTERNAL), 92 VMSTATE_UINT64_ARRAY(icc_ctlr_el1, GICv3CPUState, 2), 93 VMSTATE_UINT64(icc_pmr_el1, GICv3CPUState), 94 VMSTATE_UINT64_ARRAY(icc_bpr, GICv3CPUState, 3), 95 VMSTATE_UINT64_2DARRAY(icc_apr, GICv3CPUState, 3, 4), 96 VMSTATE_UINT64_ARRAY(icc_igrpen, GICv3CPUState, 3), 97 VMSTATE_UINT64(icc_ctlr_el3, GICv3CPUState), 98 VMSTATE_END_OF_LIST() 99 }, 100 .subsections = (const VMStateDescription * []) { 101 &vmstate_gicv3_cpu_virt, 102 NULL 103 } 104 }; 105 106 static const VMStateDescription vmstate_gicv3 = { 107 .name = "arm_gicv3", 108 .version_id = 1, 109 .minimum_version_id = 1, 110 .pre_save = gicv3_pre_save, 111 .post_load = gicv3_post_load, 112 .fields = (VMStateField[]) { 113 VMSTATE_UINT32(gicd_ctlr, GICv3State), 114 VMSTATE_UINT32_ARRAY(gicd_statusr, GICv3State, 2), 115 VMSTATE_UINT32_ARRAY(group, GICv3State, GICV3_BMP_SIZE), 116 VMSTATE_UINT32_ARRAY(grpmod, GICv3State, GICV3_BMP_SIZE), 117 VMSTATE_UINT32_ARRAY(enabled, GICv3State, GICV3_BMP_SIZE), 118 VMSTATE_UINT32_ARRAY(pending, GICv3State, GICV3_BMP_SIZE), 119 VMSTATE_UINT32_ARRAY(active, GICv3State, GICV3_BMP_SIZE), 120 VMSTATE_UINT32_ARRAY(level, GICv3State, GICV3_BMP_SIZE), 121 VMSTATE_UINT32_ARRAY(edge_trigger, GICv3State, GICV3_BMP_SIZE), 122 VMSTATE_UINT8_ARRAY(gicd_ipriority, GICv3State, GICV3_MAXIRQ), 123 VMSTATE_UINT64_ARRAY(gicd_irouter, GICv3State, GICV3_MAXIRQ), 124 VMSTATE_UINT32_ARRAY(gicd_nsacr, GICv3State, 125 DIV_ROUND_UP(GICV3_MAXIRQ, 16)), 126 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, GICv3State, num_cpu, 127 vmstate_gicv3_cpu, GICv3CPUState), 128 VMSTATE_END_OF_LIST() 129 } 130 }; 131 132 void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler, 133 const MemoryRegionOps *ops) 134 { 135 SysBusDevice *sbd = SYS_BUS_DEVICE(s); 136 int i; 137 138 /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU. 139 * GPIO array layout is thus: 140 * [0..N-1] spi 141 * [N..N+31] PPIs for CPU 0 142 * [N+32..N+63] PPIs for CPU 1 143 * ... 144 */ 145 i = s->num_irq - GIC_INTERNAL + GIC_INTERNAL * s->num_cpu; 146 qdev_init_gpio_in(DEVICE(s), handler, i); 147 148 for (i = 0; i < s->num_cpu; i++) { 149 sysbus_init_irq(sbd, &s->cpu[i].parent_irq); 150 } 151 for (i = 0; i < s->num_cpu; i++) { 152 sysbus_init_irq(sbd, &s->cpu[i].parent_fiq); 153 } 154 for (i = 0; i < s->num_cpu; i++) { 155 sysbus_init_irq(sbd, &s->cpu[i].parent_virq); 156 } 157 for (i = 0; i < s->num_cpu; i++) { 158 sysbus_init_irq(sbd, &s->cpu[i].parent_vfiq); 159 } 160 161 memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s, 162 "gicv3_dist", 0x10000); 163 memory_region_init_io(&s->iomem_redist, OBJECT(s), ops ? &ops[1] : NULL, s, 164 "gicv3_redist", 0x20000 * s->num_cpu); 165 166 sysbus_init_mmio(sbd, &s->iomem_dist); 167 sysbus_init_mmio(sbd, &s->iomem_redist); 168 } 169 170 static void arm_gicv3_common_realize(DeviceState *dev, Error **errp) 171 { 172 GICv3State *s = ARM_GICV3_COMMON(dev); 173 int i; 174 175 /* revision property is actually reserved and currently used only in order 176 * to keep the interface compatible with GICv2 code, avoiding extra 177 * conditions. However, in future it could be used, for example, if we 178 * implement GICv4. 179 */ 180 if (s->revision != 3) { 181 error_setg(errp, "unsupported GIC revision %d", s->revision); 182 return; 183 } 184 185 if (s->num_irq > GICV3_MAXIRQ) { 186 error_setg(errp, 187 "requested %u interrupt lines exceeds GIC maximum %d", 188 s->num_irq, GICV3_MAXIRQ); 189 return; 190 } 191 if (s->num_irq < GIC_INTERNAL) { 192 error_setg(errp, 193 "requested %u interrupt lines is below GIC minimum %d", 194 s->num_irq, GIC_INTERNAL); 195 return; 196 } 197 198 /* ITLinesNumber is represented as (N / 32) - 1, so this is an 199 * implementation imposed restriction, not an architectural one, 200 * so we don't have to deal with bitfields where only some of the 201 * bits in a 32-bit word should be valid. 202 */ 203 if (s->num_irq % 32) { 204 error_setg(errp, 205 "%d interrupt lines unsupported: not divisible by 32", 206 s->num_irq); 207 return; 208 } 209 210 s->cpu = g_new0(GICv3CPUState, s->num_cpu); 211 212 for (i = 0; i < s->num_cpu; i++) { 213 CPUState *cpu = qemu_get_cpu(i); 214 uint64_t cpu_affid; 215 int last; 216 217 s->cpu[i].cpu = cpu; 218 s->cpu[i].gic = s; 219 220 /* Pre-construct the GICR_TYPER: 221 * For our implementation: 222 * Top 32 bits are the affinity value of the associated CPU 223 * CommonLPIAff == 01 (redistributors with same Aff3 share LPI table) 224 * Processor_Number == CPU index starting from 0 225 * DPGS == 0 (GICR_CTLR.DPG* not supported) 226 * Last == 1 if this is the last redistributor in a series of 227 * contiguous redistributor pages 228 * DirectLPI == 0 (direct injection of LPIs not supported) 229 * VLPIS == 0 (virtual LPIs not supported) 230 * PLPIS == 0 (physical LPIs not supported) 231 */ 232 cpu_affid = object_property_get_int(OBJECT(cpu), "mp-affinity", NULL); 233 last = (i == s->num_cpu - 1); 234 235 /* The CPU mp-affinity property is in MPIDR register format; squash 236 * the affinity bytes into 32 bits as the GICR_TYPER has them. 237 */ 238 cpu_affid = ((cpu_affid & 0xFF00000000ULL) >> 8) | 239 (cpu_affid & 0xFFFFFF); 240 s->cpu[i].gicr_typer = (cpu_affid << 32) | 241 (1 << 24) | 242 (i << 8) | 243 (last << 4); 244 } 245 } 246 247 static void arm_gicv3_common_reset(DeviceState *dev) 248 { 249 GICv3State *s = ARM_GICV3_COMMON(dev); 250 int i; 251 252 for (i = 0; i < s->num_cpu; i++) { 253 GICv3CPUState *cs = &s->cpu[i]; 254 255 cs->level = 0; 256 cs->gicr_ctlr = 0; 257 cs->gicr_statusr[GICV3_S] = 0; 258 cs->gicr_statusr[GICV3_NS] = 0; 259 cs->gicr_waker = GICR_WAKER_ProcessorSleep | GICR_WAKER_ChildrenAsleep; 260 cs->gicr_propbaser = 0; 261 cs->gicr_pendbaser = 0; 262 /* If we're resetting a TZ-aware GIC as if secure firmware 263 * had set it up ready to start a kernel in non-secure, we 264 * need to set interrupts to group 1 so the kernel can use them. 265 * Otherwise they reset to group 0 like the hardware. 266 */ 267 if (s->irq_reset_nonsecure) { 268 cs->gicr_igroupr0 = 0xffffffff; 269 } else { 270 cs->gicr_igroupr0 = 0; 271 } 272 273 cs->gicr_ienabler0 = 0; 274 cs->gicr_ipendr0 = 0; 275 cs->gicr_iactiver0 = 0; 276 cs->edge_trigger = 0xffff; 277 cs->gicr_igrpmodr0 = 0; 278 cs->gicr_nsacr = 0; 279 memset(cs->gicr_ipriorityr, 0, sizeof(cs->gicr_ipriorityr)); 280 281 cs->hppi.prio = 0xff; 282 283 /* State in the CPU interface must *not* be reset here, because it 284 * is part of the CPU's reset domain, not the GIC device's. 285 */ 286 } 287 288 /* For our implementation affinity routing is always enabled */ 289 if (s->security_extn) { 290 s->gicd_ctlr = GICD_CTLR_ARE_S | GICD_CTLR_ARE_NS; 291 } else { 292 s->gicd_ctlr = GICD_CTLR_DS | GICD_CTLR_ARE; 293 } 294 295 s->gicd_statusr[GICV3_S] = 0; 296 s->gicd_statusr[GICV3_NS] = 0; 297 298 memset(s->group, 0, sizeof(s->group)); 299 memset(s->grpmod, 0, sizeof(s->grpmod)); 300 memset(s->enabled, 0, sizeof(s->enabled)); 301 memset(s->pending, 0, sizeof(s->pending)); 302 memset(s->active, 0, sizeof(s->active)); 303 memset(s->level, 0, sizeof(s->level)); 304 memset(s->edge_trigger, 0, sizeof(s->edge_trigger)); 305 memset(s->gicd_ipriority, 0, sizeof(s->gicd_ipriority)); 306 memset(s->gicd_irouter, 0, sizeof(s->gicd_irouter)); 307 memset(s->gicd_nsacr, 0, sizeof(s->gicd_nsacr)); 308 /* GICD_IROUTER are UNKNOWN at reset so in theory the guest must 309 * write these to get sane behaviour and we need not populate the 310 * pointer cache here; however having the cache be different for 311 * "happened to be 0 from reset" and "guest wrote 0" would be 312 * too confusing. 313 */ 314 gicv3_cache_all_target_cpustates(s); 315 316 if (s->irq_reset_nonsecure) { 317 /* If we're resetting a TZ-aware GIC as if secure firmware 318 * had set it up ready to start a kernel in non-secure, we 319 * need to set interrupts to group 1 so the kernel can use them. 320 * Otherwise they reset to group 0 like the hardware. 321 */ 322 for (i = GIC_INTERNAL; i < s->num_irq; i++) { 323 gicv3_gicd_group_set(s, i); 324 } 325 } 326 } 327 328 static void arm_gic_common_linux_init(ARMLinuxBootIf *obj, 329 bool secure_boot) 330 { 331 GICv3State *s = ARM_GICV3_COMMON(obj); 332 333 if (s->security_extn && !secure_boot) { 334 /* We're directly booting a kernel into NonSecure. If this GIC 335 * implements the security extensions then we must configure it 336 * to have all the interrupts be NonSecure (this is a job that 337 * is done by the Secure boot firmware in real hardware, and in 338 * this mode QEMU is acting as a minimalist firmware-and-bootloader 339 * equivalent). 340 */ 341 s->irq_reset_nonsecure = true; 342 } 343 } 344 345 static Property arm_gicv3_common_properties[] = { 346 DEFINE_PROP_UINT32("num-cpu", GICv3State, num_cpu, 1), 347 DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32), 348 DEFINE_PROP_UINT32("revision", GICv3State, revision, 3), 349 DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0), 350 DEFINE_PROP_END_OF_LIST(), 351 }; 352 353 static void arm_gicv3_common_class_init(ObjectClass *klass, void *data) 354 { 355 DeviceClass *dc = DEVICE_CLASS(klass); 356 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass); 357 358 dc->reset = arm_gicv3_common_reset; 359 dc->realize = arm_gicv3_common_realize; 360 dc->props = arm_gicv3_common_properties; 361 dc->vmsd = &vmstate_gicv3; 362 albifc->arm_linux_init = arm_gic_common_linux_init; 363 } 364 365 static const TypeInfo arm_gicv3_common_type = { 366 .name = TYPE_ARM_GICV3_COMMON, 367 .parent = TYPE_SYS_BUS_DEVICE, 368 .instance_size = sizeof(GICv3State), 369 .class_size = sizeof(ARMGICv3CommonClass), 370 .class_init = arm_gicv3_common_class_init, 371 .abstract = true, 372 .interfaces = (InterfaceInfo []) { 373 { TYPE_ARM_LINUX_BOOT_IF }, 374 { }, 375 }, 376 }; 377 378 static void register_types(void) 379 { 380 type_register_static(&arm_gicv3_common_type); 381 } 382 383 type_init(register_types) 384