1 /* 2 * ARM Generic Interrupt Controller v3 3 * 4 * Copyright (c) 2015 Huawei. 5 * Copyright (c) 2016 Linaro Limited 6 * Written by Shlomo Pongratz, Peter Maydell 7 * 8 * This code is licensed under the GPL, version 2 or (at your option) 9 * any later version. 10 */ 11 12 /* This file contains implementation code for an interrupt controller 13 * which implements the GICv3 architecture. Specifically this is where 14 * the device class itself and the functions for handling interrupts 15 * coming in and going out live. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qapi/error.h" 20 #include "hw/sysbus.h" 21 #include "hw/intc/arm_gicv3.h" 22 #include "gicv3_internal.h" 23 24 /* Process a change in an external IRQ input. */ 25 static void gicv3_set_irq(void *opaque, int irq, int level) 26 { 27 /* Meaning of the 'irq' parameter: 28 * [0..N-1] : external interrupts 29 * [N..N+31] : PPI (internal) interrupts for CPU 0 30 * [N+32..N+63] : PPI (internal interrupts for CPU 1 31 * ... 32 */ 33 /* Do nothing for now */ 34 } 35 36 static void arm_gic_realize(DeviceState *dev, Error **errp) 37 { 38 /* Device instance realize function for the GIC sysbus device */ 39 GICv3State *s = ARM_GICV3(dev); 40 ARMGICv3Class *agc = ARM_GICV3_GET_CLASS(s); 41 Error *local_err = NULL; 42 43 agc->parent_realize(dev, &local_err); 44 if (local_err) { 45 error_propagate(errp, local_err); 46 return; 47 } 48 49 gicv3_init_irqs_and_mmio(s, gicv3_set_irq, NULL); 50 } 51 52 static void arm_gicv3_class_init(ObjectClass *klass, void *data) 53 { 54 DeviceClass *dc = DEVICE_CLASS(klass); 55 ARMGICv3Class *agc = ARM_GICV3_CLASS(klass); 56 57 agc->parent_realize = dc->realize; 58 dc->realize = arm_gic_realize; 59 } 60 61 static const TypeInfo arm_gicv3_info = { 62 .name = TYPE_ARM_GICV3, 63 .parent = TYPE_ARM_GICV3_COMMON, 64 .instance_size = sizeof(GICv3State), 65 .class_init = arm_gicv3_class_init, 66 .class_size = sizeof(ARMGICv3Class), 67 }; 68 69 static void arm_gicv3_register_types(void) 70 { 71 type_register_static(&arm_gicv3_info); 72 } 73 74 type_init(arm_gicv3_register_types) 75