1 /* 2 * GICv2m extension for MSI/MSI-x support with a GICv2-based system 3 * 4 * Copyright (C) 2015 Linaro, All rights reserved. 5 * 6 * Author: Christoffer Dall <christoffer.dall@linaro.org> 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 /* This file implements an emulated GICv2m widget as described in the ARM 23 * Server Base System Architecture (SBSA) specification Version 2.2 24 * (ARM-DEN-0029 v2.2) pages 35-39 without any optional implementation defined 25 * identification registers and with a single non-secure MSI register frame. 26 */ 27 28 #include "hw/sysbus.h" 29 #include "hw/pci/msi.h" 30 31 #define TYPE_ARM_GICV2M "arm-gicv2m" 32 #define ARM_GICV2M(obj) OBJECT_CHECK(ARMGICv2mState, (obj), TYPE_ARM_GICV2M) 33 34 #define GICV2M_NUM_SPI_MAX 128 35 36 #define V2M_MSI_TYPER 0x008 37 #define V2M_MSI_SETSPI_NS 0x040 38 #define V2M_MSI_IIDR 0xFCC 39 #define V2M_IIDR0 0xFD0 40 #define V2M_IIDR11 0xFFC 41 42 #define PRODUCT_ID_QEMU 0x51 /* ASCII code Q */ 43 44 typedef struct ARMGICv2mState { 45 SysBusDevice parent_obj; 46 47 MemoryRegion iomem; 48 qemu_irq spi[GICV2M_NUM_SPI_MAX]; 49 50 uint32_t base_spi; 51 uint32_t num_spi; 52 } ARMGICv2mState; 53 54 static void gicv2m_set_irq(void *opaque, int irq) 55 { 56 ARMGICv2mState *s = (ARMGICv2mState *)opaque; 57 58 qemu_irq_pulse(s->spi[irq]); 59 } 60 61 static uint64_t gicv2m_read(void *opaque, hwaddr offset, 62 unsigned size) 63 { 64 ARMGICv2mState *s = (ARMGICv2mState *)opaque; 65 uint32_t val; 66 67 if (size != 4) { 68 qemu_log_mask(LOG_GUEST_ERROR, "gicv2m_read: bad size %u\n", size); 69 return 0; 70 } 71 72 switch (offset) { 73 case V2M_MSI_TYPER: 74 val = (s->base_spi + 32) << 16; 75 val |= s->num_spi; 76 return val; 77 case V2M_MSI_IIDR: 78 /* We don't have any valid implementor so we leave that field as zero 79 * and we return 0 in the arch revision as per the spec. 80 */ 81 return (PRODUCT_ID_QEMU << 20); 82 case V2M_IIDR0 ... V2M_IIDR11: 83 /* We do not implement any optional identification registers and the 84 * mandatory MSI_PIDR2 register reads as 0x0, so we capture all 85 * implementation defined registers here. 86 */ 87 return 0; 88 default: 89 qemu_log_mask(LOG_GUEST_ERROR, 90 "gicv2m_read: Bad offset %x\n", (int)offset); 91 return 0; 92 } 93 } 94 95 static void gicv2m_write(void *opaque, hwaddr offset, 96 uint64_t value, unsigned size) 97 { 98 ARMGICv2mState *s = (ARMGICv2mState *)opaque; 99 100 if (size != 2 && size != 4) { 101 qemu_log_mask(LOG_GUEST_ERROR, "gicv2m_write: bad size %u\n", size); 102 return; 103 } 104 105 switch (offset) { 106 case V2M_MSI_SETSPI_NS: { 107 int spi; 108 109 spi = (value & 0x3ff) - (s->base_spi + 32); 110 if (spi >= 0 && spi < s->num_spi) { 111 gicv2m_set_irq(s, spi); 112 } 113 return; 114 } 115 default: 116 qemu_log_mask(LOG_GUEST_ERROR, 117 "gicv2m_write: Bad offset %x\n", (int)offset); 118 } 119 } 120 121 static const MemoryRegionOps gicv2m_ops = { 122 .read = gicv2m_read, 123 .write = gicv2m_write, 124 .endianness = DEVICE_LITTLE_ENDIAN, 125 }; 126 127 static void gicv2m_realize(DeviceState *dev, Error **errp) 128 { 129 ARMGICv2mState *s = ARM_GICV2M(dev); 130 int i; 131 132 if (s->num_spi > GICV2M_NUM_SPI_MAX) { 133 error_setg(errp, 134 "requested %u SPIs exceeds GICv2m frame maximum %d", 135 s->num_spi, GICV2M_NUM_SPI_MAX); 136 return; 137 } 138 139 if (s->base_spi + 32 > 1020 - s->num_spi) { 140 error_setg(errp, 141 "requested base SPI %u+%u exceeds max. number 1020", 142 s->base_spi + 32, s->num_spi); 143 return; 144 } 145 146 for (i = 0; i < s->num_spi; i++) { 147 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->spi[i]); 148 } 149 150 msi_supported = true; 151 kvm_gsi_direct_mapping = true; 152 kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled(); 153 } 154 155 static void gicv2m_init(Object *obj) 156 { 157 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 158 ARMGICv2mState *s = ARM_GICV2M(obj); 159 160 memory_region_init_io(&s->iomem, OBJECT(s), &gicv2m_ops, s, 161 "gicv2m", 0x1000); 162 sysbus_init_mmio(sbd, &s->iomem); 163 } 164 165 static Property gicv2m_properties[] = { 166 DEFINE_PROP_UINT32("base-spi", ARMGICv2mState, base_spi, 0), 167 DEFINE_PROP_UINT32("num-spi", ARMGICv2mState, num_spi, 64), 168 DEFINE_PROP_END_OF_LIST(), 169 }; 170 171 static void gicv2m_class_init(ObjectClass *klass, void *data) 172 { 173 DeviceClass *dc = DEVICE_CLASS(klass); 174 175 dc->props = gicv2m_properties; 176 dc->realize = gicv2m_realize; 177 } 178 179 static const TypeInfo gicv2m_info = { 180 .name = TYPE_ARM_GICV2M, 181 .parent = TYPE_SYS_BUS_DEVICE, 182 .instance_size = sizeof(ARMGICv2mState), 183 .instance_init = gicv2m_init, 184 .class_init = gicv2m_class_init, 185 }; 186 187 static void gicv2m_register_types(void) 188 { 189 type_register_static(&gicv2m_info); 190 } 191 192 type_init(gicv2m_register_types) 193