1 /* 2 * GICv2m extension for MSI/MSI-x support with a GICv2-based system 3 * 4 * Copyright (C) 2015 Linaro, All rights reserved. 5 * 6 * Author: Christoffer Dall <christoffer.dall@linaro.org> 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 /* This file implements an emulated GICv2m widget as described in the ARM 23 * Server Base System Architecture (SBSA) specification Version 2.2 24 * (ARM-DEN-0029 v2.2) pages 35-39 without any optional implementation defined 25 * identification registers and with a single non-secure MSI register frame. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qapi/error.h" 30 #include "hw/sysbus.h" 31 #include "hw/pci/msi.h" 32 33 #define TYPE_ARM_GICV2M "arm-gicv2m" 34 #define ARM_GICV2M(obj) OBJECT_CHECK(ARMGICv2mState, (obj), TYPE_ARM_GICV2M) 35 36 #define GICV2M_NUM_SPI_MAX 128 37 38 #define V2M_MSI_TYPER 0x008 39 #define V2M_MSI_SETSPI_NS 0x040 40 #define V2M_MSI_IIDR 0xFCC 41 #define V2M_IIDR0 0xFD0 42 #define V2M_IIDR11 0xFFC 43 44 #define PRODUCT_ID_QEMU 0x51 /* ASCII code Q */ 45 46 typedef struct ARMGICv2mState { 47 SysBusDevice parent_obj; 48 49 MemoryRegion iomem; 50 qemu_irq spi[GICV2M_NUM_SPI_MAX]; 51 52 uint32_t base_spi; 53 uint32_t num_spi; 54 } ARMGICv2mState; 55 56 static void gicv2m_set_irq(void *opaque, int irq) 57 { 58 ARMGICv2mState *s = (ARMGICv2mState *)opaque; 59 60 qemu_irq_pulse(s->spi[irq]); 61 } 62 63 static uint64_t gicv2m_read(void *opaque, hwaddr offset, 64 unsigned size) 65 { 66 ARMGICv2mState *s = (ARMGICv2mState *)opaque; 67 uint32_t val; 68 69 if (size != 4) { 70 qemu_log_mask(LOG_GUEST_ERROR, "gicv2m_read: bad size %u\n", size); 71 return 0; 72 } 73 74 switch (offset) { 75 case V2M_MSI_TYPER: 76 val = (s->base_spi + 32) << 16; 77 val |= s->num_spi; 78 return val; 79 case V2M_MSI_IIDR: 80 /* We don't have any valid implementor so we leave that field as zero 81 * and we return 0 in the arch revision as per the spec. 82 */ 83 return (PRODUCT_ID_QEMU << 20); 84 case V2M_IIDR0 ... V2M_IIDR11: 85 /* We do not implement any optional identification registers and the 86 * mandatory MSI_PIDR2 register reads as 0x0, so we capture all 87 * implementation defined registers here. 88 */ 89 return 0; 90 default: 91 qemu_log_mask(LOG_GUEST_ERROR, 92 "gicv2m_read: Bad offset %x\n", (int)offset); 93 return 0; 94 } 95 } 96 97 static void gicv2m_write(void *opaque, hwaddr offset, 98 uint64_t value, unsigned size) 99 { 100 ARMGICv2mState *s = (ARMGICv2mState *)opaque; 101 102 if (size != 2 && size != 4) { 103 qemu_log_mask(LOG_GUEST_ERROR, "gicv2m_write: bad size %u\n", size); 104 return; 105 } 106 107 switch (offset) { 108 case V2M_MSI_SETSPI_NS: { 109 int spi; 110 111 spi = (value & 0x3ff) - (s->base_spi + 32); 112 if (spi >= 0 && spi < s->num_spi) { 113 gicv2m_set_irq(s, spi); 114 } 115 return; 116 } 117 default: 118 qemu_log_mask(LOG_GUEST_ERROR, 119 "gicv2m_write: Bad offset %x\n", (int)offset); 120 } 121 } 122 123 static const MemoryRegionOps gicv2m_ops = { 124 .read = gicv2m_read, 125 .write = gicv2m_write, 126 .endianness = DEVICE_LITTLE_ENDIAN, 127 }; 128 129 static void gicv2m_realize(DeviceState *dev, Error **errp) 130 { 131 ARMGICv2mState *s = ARM_GICV2M(dev); 132 int i; 133 134 if (s->num_spi > GICV2M_NUM_SPI_MAX) { 135 error_setg(errp, 136 "requested %u SPIs exceeds GICv2m frame maximum %d", 137 s->num_spi, GICV2M_NUM_SPI_MAX); 138 return; 139 } 140 141 if (s->base_spi + 32 > 1020 - s->num_spi) { 142 error_setg(errp, 143 "requested base SPI %u+%u exceeds max. number 1020", 144 s->base_spi + 32, s->num_spi); 145 return; 146 } 147 148 for (i = 0; i < s->num_spi; i++) { 149 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->spi[i]); 150 } 151 152 msi_nonbroken = true; 153 kvm_gsi_direct_mapping = true; 154 kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled(); 155 } 156 157 static void gicv2m_init(Object *obj) 158 { 159 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 160 ARMGICv2mState *s = ARM_GICV2M(obj); 161 162 memory_region_init_io(&s->iomem, OBJECT(s), &gicv2m_ops, s, 163 "gicv2m", 0x1000); 164 sysbus_init_mmio(sbd, &s->iomem); 165 } 166 167 static Property gicv2m_properties[] = { 168 DEFINE_PROP_UINT32("base-spi", ARMGICv2mState, base_spi, 0), 169 DEFINE_PROP_UINT32("num-spi", ARMGICv2mState, num_spi, 64), 170 DEFINE_PROP_END_OF_LIST(), 171 }; 172 173 static void gicv2m_class_init(ObjectClass *klass, void *data) 174 { 175 DeviceClass *dc = DEVICE_CLASS(klass); 176 177 dc->props = gicv2m_properties; 178 dc->realize = gicv2m_realize; 179 } 180 181 static const TypeInfo gicv2m_info = { 182 .name = TYPE_ARM_GICV2M, 183 .parent = TYPE_SYS_BUS_DEVICE, 184 .instance_size = sizeof(ARMGICv2mState), 185 .instance_init = gicv2m_init, 186 .class_init = gicv2m_class_init, 187 }; 188 189 static void gicv2m_register_types(void) 190 { 191 type_register_static(&gicv2m_info); 192 } 193 194 type_init(gicv2m_register_types) 195