xref: /openbmc/qemu/hw/intc/arm_gic_common.c (revision db725815985654007ade0fd53590d613fd657208)
1 /*
2  * ARM GIC support - common bits of emulated and KVM kernel model
3  *
4  * Copyright (c) 2012 Linaro Limited
5  * Written by Peter Maydell
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation, either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License along
18  * with this program; if not, see <http://www.gnu.org/licenses/>.
19  */
20 
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "qemu/module.h"
24 #include "gic_internal.h"
25 #include "hw/arm/linux-boot-if.h"
26 #include "migration/vmstate.h"
27 
28 static int gic_pre_save(void *opaque)
29 {
30     GICState *s = (GICState *)opaque;
31     ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s);
32 
33     if (c->pre_save) {
34         c->pre_save(s);
35     }
36 
37     return 0;
38 }
39 
40 static int gic_post_load(void *opaque, int version_id)
41 {
42     GICState *s = (GICState *)opaque;
43     ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s);
44 
45     if (c->post_load) {
46         c->post_load(s);
47     }
48     return 0;
49 }
50 
51 static bool gic_virt_state_needed(void *opaque)
52 {
53     GICState *s = (GICState *)opaque;
54 
55     return s->virt_extn;
56 }
57 
58 static const VMStateDescription vmstate_gic_irq_state = {
59     .name = "arm_gic_irq_state",
60     .version_id = 1,
61     .minimum_version_id = 1,
62     .fields = (VMStateField[]) {
63         VMSTATE_UINT8(enabled, gic_irq_state),
64         VMSTATE_UINT8(pending, gic_irq_state),
65         VMSTATE_UINT8(active, gic_irq_state),
66         VMSTATE_UINT8(level, gic_irq_state),
67         VMSTATE_BOOL(model, gic_irq_state),
68         VMSTATE_BOOL(edge_trigger, gic_irq_state),
69         VMSTATE_UINT8(group, gic_irq_state),
70         VMSTATE_END_OF_LIST()
71     }
72 };
73 
74 static const VMStateDescription vmstate_gic_virt_state = {
75     .name = "arm_gic_virt_state",
76     .version_id = 1,
77     .minimum_version_id = 1,
78     .needed = gic_virt_state_needed,
79     .fields = (VMStateField[]) {
80         /* Virtual interface */
81         VMSTATE_UINT32_ARRAY(h_hcr, GICState, GIC_NCPU),
82         VMSTATE_UINT32_ARRAY(h_misr, GICState, GIC_NCPU),
83         VMSTATE_UINT32_2DARRAY(h_lr, GICState, GIC_MAX_LR, GIC_NCPU),
84         VMSTATE_UINT32_ARRAY(h_apr, GICState, GIC_NCPU),
85 
86         /* Virtual CPU interfaces */
87         VMSTATE_UINT32_SUB_ARRAY(cpu_ctlr, GICState, GIC_NCPU, GIC_NCPU),
88         VMSTATE_UINT16_SUB_ARRAY(priority_mask, GICState, GIC_NCPU, GIC_NCPU),
89         VMSTATE_UINT16_SUB_ARRAY(running_priority, GICState, GIC_NCPU, GIC_NCPU),
90         VMSTATE_UINT16_SUB_ARRAY(current_pending, GICState, GIC_NCPU, GIC_NCPU),
91         VMSTATE_UINT8_SUB_ARRAY(bpr, GICState, GIC_NCPU, GIC_NCPU),
92         VMSTATE_UINT8_SUB_ARRAY(abpr, GICState, GIC_NCPU, GIC_NCPU),
93 
94         VMSTATE_END_OF_LIST()
95     }
96 };
97 
98 static const VMStateDescription vmstate_gic = {
99     .name = "arm_gic",
100     .version_id = 12,
101     .minimum_version_id = 12,
102     .pre_save = gic_pre_save,
103     .post_load = gic_post_load,
104     .fields = (VMStateField[]) {
105         VMSTATE_UINT32(ctlr, GICState),
106         VMSTATE_UINT32_SUB_ARRAY(cpu_ctlr, GICState, 0, GIC_NCPU),
107         VMSTATE_STRUCT_ARRAY(irq_state, GICState, GIC_MAXIRQ, 1,
108                              vmstate_gic_irq_state, gic_irq_state),
109         VMSTATE_UINT8_ARRAY(irq_target, GICState, GIC_MAXIRQ),
110         VMSTATE_UINT8_2DARRAY(priority1, GICState, GIC_INTERNAL, GIC_NCPU),
111         VMSTATE_UINT8_ARRAY(priority2, GICState, GIC_MAXIRQ - GIC_INTERNAL),
112         VMSTATE_UINT8_2DARRAY(sgi_pending, GICState, GIC_NR_SGIS, GIC_NCPU),
113         VMSTATE_UINT16_SUB_ARRAY(priority_mask, GICState, 0, GIC_NCPU),
114         VMSTATE_UINT16_SUB_ARRAY(running_priority, GICState, 0, GIC_NCPU),
115         VMSTATE_UINT16_SUB_ARRAY(current_pending, GICState, 0, GIC_NCPU),
116         VMSTATE_UINT8_SUB_ARRAY(bpr, GICState, 0, GIC_NCPU),
117         VMSTATE_UINT8_SUB_ARRAY(abpr, GICState, 0, GIC_NCPU),
118         VMSTATE_UINT32_2DARRAY(apr, GICState, GIC_NR_APRS, GIC_NCPU),
119         VMSTATE_UINT32_2DARRAY(nsapr, GICState, GIC_NR_APRS, GIC_NCPU),
120         VMSTATE_END_OF_LIST()
121     },
122     .subsections = (const VMStateDescription * []) {
123         &vmstate_gic_virt_state,
124         NULL
125     }
126 };
127 
128 void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler,
129                             const MemoryRegionOps *ops,
130                             const MemoryRegionOps *virt_ops)
131 {
132     SysBusDevice *sbd = SYS_BUS_DEVICE(s);
133     int i = s->num_irq - GIC_INTERNAL;
134 
135     /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
136      * GPIO array layout is thus:
137      *  [0..N-1] SPIs
138      *  [N..N+31] PPIs for CPU 0
139      *  [N+32..N+63] PPIs for CPU 1
140      *   ...
141      */
142     i += (GIC_INTERNAL * s->num_cpu);
143     qdev_init_gpio_in(DEVICE(s), handler, i);
144 
145     for (i = 0; i < s->num_cpu; i++) {
146         sysbus_init_irq(sbd, &s->parent_irq[i]);
147     }
148     for (i = 0; i < s->num_cpu; i++) {
149         sysbus_init_irq(sbd, &s->parent_fiq[i]);
150     }
151     for (i = 0; i < s->num_cpu; i++) {
152         sysbus_init_irq(sbd, &s->parent_virq[i]);
153     }
154     for (i = 0; i < s->num_cpu; i++) {
155         sysbus_init_irq(sbd, &s->parent_vfiq[i]);
156     }
157     if (s->virt_extn) {
158         for (i = 0; i < s->num_cpu; i++) {
159             sysbus_init_irq(sbd, &s->maintenance_irq[i]);
160         }
161     }
162 
163     /* Distributor */
164     memory_region_init_io(&s->iomem, OBJECT(s), ops, s, "gic_dist", 0x1000);
165     sysbus_init_mmio(sbd, &s->iomem);
166 
167     /* This is the main CPU interface "for this core". It is always
168      * present because it is required by both software emulation and KVM.
169      */
170     memory_region_init_io(&s->cpuiomem[0], OBJECT(s), ops ? &ops[1] : NULL,
171                           s, "gic_cpu", s->revision == 2 ? 0x2000 : 0x100);
172     sysbus_init_mmio(sbd, &s->cpuiomem[0]);
173 
174     if (s->virt_extn) {
175         memory_region_init_io(&s->vifaceiomem[0], OBJECT(s), virt_ops,
176                               s, "gic_viface", 0x1000);
177         sysbus_init_mmio(sbd, &s->vifaceiomem[0]);
178 
179         memory_region_init_io(&s->vcpuiomem, OBJECT(s),
180                               virt_ops ? &virt_ops[1] : NULL,
181                               s, "gic_vcpu", 0x2000);
182         sysbus_init_mmio(sbd, &s->vcpuiomem);
183     }
184 }
185 
186 static void arm_gic_common_realize(DeviceState *dev, Error **errp)
187 {
188     GICState *s = ARM_GIC_COMMON(dev);
189     int num_irq = s->num_irq;
190 
191     if (s->num_cpu > GIC_NCPU) {
192         error_setg(errp, "requested %u CPUs exceeds GIC maximum %d",
193                    s->num_cpu, GIC_NCPU);
194         return;
195     }
196     if (s->num_irq > GIC_MAXIRQ) {
197         error_setg(errp,
198                    "requested %u interrupt lines exceeds GIC maximum %d",
199                    num_irq, GIC_MAXIRQ);
200         return;
201     }
202     /* ITLinesNumber is represented as (N / 32) - 1 (see
203      * gic_dist_readb) so this is an implementation imposed
204      * restriction, not an architectural one:
205      */
206     if (s->num_irq < 32 || (s->num_irq % 32)) {
207         error_setg(errp,
208                    "%d interrupt lines unsupported: not divisible by 32",
209                    num_irq);
210         return;
211     }
212 
213     if (s->security_extn &&
214         (s->revision == REV_11MPCORE)) {
215         error_setg(errp, "this GIC revision does not implement "
216                    "the security extensions");
217         return;
218     }
219 
220     if (s->virt_extn) {
221         if (s->revision != 2) {
222             error_setg(errp, "GIC virtualization extensions are only "
223                        "supported by revision 2");
224             return;
225         }
226 
227         /* For now, set the number of implemented LRs to 4, as found in most
228          * real GICv2. This could be promoted as a QOM property if we need to
229          * emulate a variant with another num_lrs.
230          */
231         s->num_lrs = 4;
232     }
233 }
234 
235 static inline void arm_gic_common_reset_irq_state(GICState *s, int first_cpu,
236                                                   int resetprio)
237 {
238     int i, j;
239 
240     for (i = first_cpu; i < first_cpu + s->num_cpu; i++) {
241         if (s->revision == REV_11MPCORE) {
242             s->priority_mask[i] = 0xf0;
243         } else {
244             s->priority_mask[i] = resetprio;
245         }
246         s->current_pending[i] = 1023;
247         s->running_priority[i] = 0x100;
248         s->cpu_ctlr[i] = 0;
249         s->bpr[i] = gic_is_vcpu(i) ? GIC_VIRT_MIN_BPR : GIC_MIN_BPR;
250         s->abpr[i] = gic_is_vcpu(i) ? GIC_VIRT_MIN_ABPR : GIC_MIN_ABPR;
251 
252         if (!gic_is_vcpu(i)) {
253             for (j = 0; j < GIC_INTERNAL; j++) {
254                 s->priority1[j][i] = resetprio;
255             }
256             for (j = 0; j < GIC_NR_SGIS; j++) {
257                 s->sgi_pending[j][i] = 0;
258             }
259         }
260     }
261 }
262 
263 static void arm_gic_common_reset(DeviceState *dev)
264 {
265     GICState *s = ARM_GIC_COMMON(dev);
266     int i, j;
267     int resetprio;
268 
269     /* If we're resetting a TZ-aware GIC as if secure firmware
270      * had set it up ready to start a kernel in non-secure,
271      * we need to set interrupt priorities to a "zero for the
272      * NS view" value. This is particularly critical for the
273      * priority_mask[] values, because if they are zero then NS
274      * code cannot ever rewrite the priority to anything else.
275      */
276     if (s->security_extn && s->irq_reset_nonsecure) {
277         resetprio = 0x80;
278     } else {
279         resetprio = 0;
280     }
281 
282     memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state));
283     arm_gic_common_reset_irq_state(s, 0, resetprio);
284 
285     if (s->virt_extn) {
286         /* vCPU states are stored at indexes GIC_NCPU .. GIC_NCPU+num_cpu.
287          * The exposed vCPU interface does not have security extensions.
288          */
289         arm_gic_common_reset_irq_state(s, GIC_NCPU, 0);
290     }
291 
292     for (i = 0; i < GIC_NR_SGIS; i++) {
293         GIC_DIST_SET_ENABLED(i, ALL_CPU_MASK);
294         GIC_DIST_SET_EDGE_TRIGGER(i);
295     }
296 
297     for (i = 0; i < ARRAY_SIZE(s->priority2); i++) {
298         s->priority2[i] = resetprio;
299     }
300 
301     for (i = 0; i < GIC_MAXIRQ; i++) {
302         /* For uniprocessor GICs all interrupts always target the sole CPU */
303         if (s->num_cpu == 1) {
304             s->irq_target[i] = 1;
305         } else {
306             s->irq_target[i] = 0;
307         }
308     }
309     if (s->security_extn && s->irq_reset_nonsecure) {
310         for (i = 0; i < GIC_MAXIRQ; i++) {
311             GIC_DIST_SET_GROUP(i, ALL_CPU_MASK);
312         }
313     }
314 
315     if (s->virt_extn) {
316         for (i = 0; i < s->num_lrs; i++) {
317             for (j = 0; j < s->num_cpu; j++) {
318                 s->h_lr[i][j] = 0;
319             }
320         }
321 
322         for (i = 0; i < s->num_cpu; i++) {
323             s->h_hcr[i] = 0;
324             s->h_misr[i] = 0;
325         }
326     }
327 
328     s->ctlr = 0;
329 }
330 
331 static void arm_gic_common_linux_init(ARMLinuxBootIf *obj,
332                                       bool secure_boot)
333 {
334     GICState *s = ARM_GIC_COMMON(obj);
335 
336     if (s->security_extn && !secure_boot) {
337         /* We're directly booting a kernel into NonSecure. If this GIC
338          * implements the security extensions then we must configure it
339          * to have all the interrupts be NonSecure (this is a job that
340          * is done by the Secure boot firmware in real hardware, and in
341          * this mode QEMU is acting as a minimalist firmware-and-bootloader
342          * equivalent).
343          */
344         s->irq_reset_nonsecure = true;
345     }
346 }
347 
348 static Property arm_gic_common_properties[] = {
349     DEFINE_PROP_UINT32("num-cpu", GICState, num_cpu, 1),
350     DEFINE_PROP_UINT32("num-irq", GICState, num_irq, 32),
351     /* Revision can be 1 or 2 for GIC architecture specification
352      * versions 1 or 2, or 0 to indicate the legacy 11MPCore GIC.
353      */
354     DEFINE_PROP_UINT32("revision", GICState, revision, 1),
355     /* True if the GIC should implement the security extensions */
356     DEFINE_PROP_BOOL("has-security-extensions", GICState, security_extn, 0),
357     /* True if the GIC should implement the virtualization extensions */
358     DEFINE_PROP_BOOL("has-virtualization-extensions", GICState, virt_extn, 0),
359     DEFINE_PROP_END_OF_LIST(),
360 };
361 
362 static void arm_gic_common_class_init(ObjectClass *klass, void *data)
363 {
364     DeviceClass *dc = DEVICE_CLASS(klass);
365     ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass);
366 
367     dc->reset = arm_gic_common_reset;
368     dc->realize = arm_gic_common_realize;
369     dc->props = arm_gic_common_properties;
370     dc->vmsd = &vmstate_gic;
371     albifc->arm_linux_init = arm_gic_common_linux_init;
372 }
373 
374 static const TypeInfo arm_gic_common_type = {
375     .name = TYPE_ARM_GIC_COMMON,
376     .parent = TYPE_SYS_BUS_DEVICE,
377     .instance_size = sizeof(GICState),
378     .class_size = sizeof(ARMGICCommonClass),
379     .class_init = arm_gic_common_class_init,
380     .abstract = true,
381     .interfaces = (InterfaceInfo []) {
382         { TYPE_ARM_LINUX_BOOT_IF },
383         { },
384     },
385 };
386 
387 static void register_types(void)
388 {
389     type_register_static(&arm_gic_common_type);
390 }
391 
392 type_init(register_types)
393