1 /* 2 * ARM GIC support - common bits of emulated and KVM kernel model 3 * 4 * Copyright (c) 2012 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation, either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "gic_internal.h" 22 23 static void gic_pre_save(void *opaque) 24 { 25 GICState *s = (GICState *)opaque; 26 ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s); 27 28 if (c->pre_save) { 29 c->pre_save(s); 30 } 31 } 32 33 static int gic_post_load(void *opaque, int version_id) 34 { 35 GICState *s = (GICState *)opaque; 36 ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s); 37 38 if (c->post_load) { 39 c->post_load(s); 40 } 41 return 0; 42 } 43 44 static const VMStateDescription vmstate_gic_irq_state = { 45 .name = "arm_gic_irq_state", 46 .version_id = 1, 47 .minimum_version_id = 1, 48 .fields = (VMStateField[]) { 49 VMSTATE_UINT8(enabled, gic_irq_state), 50 VMSTATE_UINT8(pending, gic_irq_state), 51 VMSTATE_UINT8(active, gic_irq_state), 52 VMSTATE_UINT8(level, gic_irq_state), 53 VMSTATE_BOOL(model, gic_irq_state), 54 VMSTATE_BOOL(edge_trigger, gic_irq_state), 55 VMSTATE_END_OF_LIST() 56 } 57 }; 58 59 static const VMStateDescription vmstate_gic = { 60 .name = "arm_gic", 61 .version_id = 4, 62 .minimum_version_id = 4, 63 .pre_save = gic_pre_save, 64 .post_load = gic_post_load, 65 .fields = (VMStateField[]) { 66 VMSTATE_BOOL(enabled, GICState), 67 VMSTATE_BOOL_ARRAY(cpu_enabled, GICState, GIC_NCPU), 68 VMSTATE_STRUCT_ARRAY(irq_state, GICState, GIC_MAXIRQ, 1, 69 vmstate_gic_irq_state, gic_irq_state), 70 VMSTATE_UINT8_ARRAY(irq_target, GICState, GIC_MAXIRQ), 71 VMSTATE_UINT8_2DARRAY(priority1, GICState, GIC_INTERNAL, GIC_NCPU), 72 VMSTATE_UINT8_ARRAY(priority2, GICState, GIC_MAXIRQ - GIC_INTERNAL), 73 VMSTATE_UINT16_2DARRAY(last_active, GICState, GIC_MAXIRQ, GIC_NCPU), 74 VMSTATE_UINT16_ARRAY(priority_mask, GICState, GIC_NCPU), 75 VMSTATE_UINT16_ARRAY(running_irq, GICState, GIC_NCPU), 76 VMSTATE_UINT16_ARRAY(running_priority, GICState, GIC_NCPU), 77 VMSTATE_UINT16_ARRAY(current_pending, GICState, GIC_NCPU), 78 VMSTATE_END_OF_LIST() 79 } 80 }; 81 82 static void arm_gic_common_realize(DeviceState *dev, Error **errp) 83 { 84 GICState *s = ARM_GIC_COMMON(dev); 85 int num_irq = s->num_irq; 86 87 if (s->num_cpu > GIC_NCPU) { 88 error_setg(errp, "requested %u CPUs exceeds GIC maximum %d", 89 s->num_cpu, GIC_NCPU); 90 return; 91 } 92 s->num_irq += GIC_BASE_IRQ; 93 if (s->num_irq > GIC_MAXIRQ) { 94 error_setg(errp, 95 "requested %u interrupt lines exceeds GIC maximum %d", 96 num_irq, GIC_MAXIRQ); 97 return; 98 } 99 /* ITLinesNumber is represented as (N / 32) - 1 (see 100 * gic_dist_readb) so this is an implementation imposed 101 * restriction, not an architectural one: 102 */ 103 if (s->num_irq < 32 || (s->num_irq % 32)) { 104 error_setg(errp, 105 "%d interrupt lines unsupported: not divisible by 32", 106 num_irq); 107 return; 108 } 109 } 110 111 static void arm_gic_common_reset(DeviceState *dev) 112 { 113 GICState *s = ARM_GIC_COMMON(dev); 114 int i; 115 memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state)); 116 for (i = 0 ; i < s->num_cpu; i++) { 117 if (s->revision == REV_11MPCORE) { 118 s->priority_mask[i] = 0xf0; 119 } else { 120 s->priority_mask[i] = 0; 121 } 122 s->current_pending[i] = 1023; 123 s->running_irq[i] = 1023; 124 s->running_priority[i] = 0x100; 125 s->cpu_enabled[i] = false; 126 } 127 for (i = 0; i < 16; i++) { 128 GIC_SET_ENABLED(i, ALL_CPU_MASK); 129 GIC_SET_EDGE_TRIGGER(i); 130 } 131 if (s->num_cpu == 1) { 132 /* For uniprocessor GICs all interrupts always target the sole CPU */ 133 for (i = 0; i < GIC_MAXIRQ; i++) { 134 s->irq_target[i] = 1; 135 } 136 } 137 s->enabled = false; 138 } 139 140 static Property arm_gic_common_properties[] = { 141 DEFINE_PROP_UINT32("num-cpu", GICState, num_cpu, 1), 142 DEFINE_PROP_UINT32("num-irq", GICState, num_irq, 32), 143 /* Revision can be 1 or 2 for GIC architecture specification 144 * versions 1 or 2, or 0 to indicate the legacy 11MPCore GIC. 145 * (Internally, 0xffffffff also indicates "not a GIC but an NVIC".) 146 */ 147 DEFINE_PROP_UINT32("revision", GICState, revision, 1), 148 DEFINE_PROP_END_OF_LIST(), 149 }; 150 151 static void arm_gic_common_class_init(ObjectClass *klass, void *data) 152 { 153 DeviceClass *dc = DEVICE_CLASS(klass); 154 155 dc->reset = arm_gic_common_reset; 156 dc->realize = arm_gic_common_realize; 157 dc->props = arm_gic_common_properties; 158 dc->vmsd = &vmstate_gic; 159 } 160 161 static const TypeInfo arm_gic_common_type = { 162 .name = TYPE_ARM_GIC_COMMON, 163 .parent = TYPE_SYS_BUS_DEVICE, 164 .instance_size = sizeof(GICState), 165 .class_size = sizeof(ARMGICCommonClass), 166 .class_init = arm_gic_common_class_init, 167 .abstract = true, 168 }; 169 170 static void register_types(void) 171 { 172 type_register_static(&arm_gic_common_type); 173 } 174 175 type_init(register_types) 176