xref: /openbmc/qemu/hw/intc/arm_gic_common.c (revision 9d49b1c9edf829e571093088ddff0b73db3110c6)
1  /*
2   * ARM GIC support - common bits of emulated and KVM kernel model
3   *
4   * Copyright (c) 2012 Linaro Limited
5   * Written by Peter Maydell
6   *
7   * This program is free software; you can redistribute it and/or modify
8   * it under the terms of the GNU General Public License as published by
9   * the Free Software Foundation, either version 2 of the License, or
10   * (at your option) any later version.
11   *
12   * This program is distributed in the hope that it will be useful,
13   * but WITHOUT ANY WARRANTY; without even the implied warranty of
14   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15   * GNU General Public License for more details.
16   *
17   * You should have received a copy of the GNU General Public License along
18   * with this program; if not, see <http://www.gnu.org/licenses/>.
19   */
20  
21  #include "qemu/osdep.h"
22  #include "qapi/error.h"
23  #include "qemu/module.h"
24  #include "qemu/error-report.h"
25  #include "gic_internal.h"
26  #include "hw/arm/linux-boot-if.h"
27  #include "hw/qdev-properties.h"
28  #include "migration/vmstate.h"
29  #include "sysemu/kvm.h"
30  
31  static int gic_pre_save(void *opaque)
32  {
33      GICState *s = (GICState *)opaque;
34      ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s);
35  
36      if (c->pre_save) {
37          c->pre_save(s);
38      }
39  
40      return 0;
41  }
42  
43  static int gic_post_load(void *opaque, int version_id)
44  {
45      GICState *s = (GICState *)opaque;
46      ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s);
47  
48      if (c->post_load) {
49          c->post_load(s);
50      }
51      return 0;
52  }
53  
54  static bool gic_virt_state_needed(void *opaque)
55  {
56      GICState *s = (GICState *)opaque;
57  
58      return s->virt_extn;
59  }
60  
61  static const VMStateDescription vmstate_gic_irq_state = {
62      .name = "arm_gic_irq_state",
63      .version_id = 1,
64      .minimum_version_id = 1,
65      .fields = (const VMStateField[]) {
66          VMSTATE_UINT8(enabled, gic_irq_state),
67          VMSTATE_UINT8(pending, gic_irq_state),
68          VMSTATE_UINT8(active, gic_irq_state),
69          VMSTATE_UINT8(level, gic_irq_state),
70          VMSTATE_BOOL(model, gic_irq_state),
71          VMSTATE_BOOL(edge_trigger, gic_irq_state),
72          VMSTATE_UINT8(group, gic_irq_state),
73          VMSTATE_END_OF_LIST()
74      }
75  };
76  
77  static const VMStateDescription vmstate_gic_virt_state = {
78      .name = "arm_gic_virt_state",
79      .version_id = 1,
80      .minimum_version_id = 1,
81      .needed = gic_virt_state_needed,
82      .fields = (const VMStateField[]) {
83          /* Virtual interface */
84          VMSTATE_UINT32_ARRAY(h_hcr, GICState, GIC_NCPU),
85          VMSTATE_UINT32_ARRAY(h_misr, GICState, GIC_NCPU),
86          VMSTATE_UINT32_2DARRAY(h_lr, GICState, GIC_MAX_LR, GIC_NCPU),
87          VMSTATE_UINT32_ARRAY(h_apr, GICState, GIC_NCPU),
88  
89          /* Virtual CPU interfaces */
90          VMSTATE_UINT32_SUB_ARRAY(cpu_ctlr, GICState, GIC_NCPU, GIC_NCPU),
91          VMSTATE_UINT16_SUB_ARRAY(priority_mask, GICState, GIC_NCPU, GIC_NCPU),
92          VMSTATE_UINT16_SUB_ARRAY(running_priority, GICState, GIC_NCPU, GIC_NCPU),
93          VMSTATE_UINT16_SUB_ARRAY(current_pending, GICState, GIC_NCPU, GIC_NCPU),
94          VMSTATE_UINT8_SUB_ARRAY(bpr, GICState, GIC_NCPU, GIC_NCPU),
95          VMSTATE_UINT8_SUB_ARRAY(abpr, GICState, GIC_NCPU, GIC_NCPU),
96  
97          VMSTATE_END_OF_LIST()
98      }
99  };
100  
101  static const VMStateDescription vmstate_gic = {
102      .name = "arm_gic",
103      .version_id = 12,
104      .minimum_version_id = 12,
105      .pre_save = gic_pre_save,
106      .post_load = gic_post_load,
107      .fields = (const VMStateField[]) {
108          VMSTATE_UINT32(ctlr, GICState),
109          VMSTATE_UINT32_SUB_ARRAY(cpu_ctlr, GICState, 0, GIC_NCPU),
110          VMSTATE_STRUCT_ARRAY(irq_state, GICState, GIC_MAXIRQ, 1,
111                               vmstate_gic_irq_state, gic_irq_state),
112          VMSTATE_UINT8_ARRAY(irq_target, GICState, GIC_MAXIRQ),
113          VMSTATE_UINT8_2DARRAY(priority1, GICState, GIC_INTERNAL, GIC_NCPU),
114          VMSTATE_UINT8_ARRAY(priority2, GICState, GIC_MAXIRQ - GIC_INTERNAL),
115          VMSTATE_UINT8_2DARRAY(sgi_pending, GICState, GIC_NR_SGIS, GIC_NCPU),
116          VMSTATE_UINT16_SUB_ARRAY(priority_mask, GICState, 0, GIC_NCPU),
117          VMSTATE_UINT16_SUB_ARRAY(running_priority, GICState, 0, GIC_NCPU),
118          VMSTATE_UINT16_SUB_ARRAY(current_pending, GICState, 0, GIC_NCPU),
119          VMSTATE_UINT8_SUB_ARRAY(bpr, GICState, 0, GIC_NCPU),
120          VMSTATE_UINT8_SUB_ARRAY(abpr, GICState, 0, GIC_NCPU),
121          VMSTATE_UINT32_2DARRAY(apr, GICState, GIC_NR_APRS, GIC_NCPU),
122          VMSTATE_UINT32_2DARRAY(nsapr, GICState, GIC_NR_APRS, GIC_NCPU),
123          VMSTATE_END_OF_LIST()
124      },
125      .subsections = (const VMStateDescription * const []) {
126          &vmstate_gic_virt_state,
127          NULL
128      }
129  };
130  
131  void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler,
132                              const MemoryRegionOps *ops,
133                              const MemoryRegionOps *virt_ops)
134  {
135      SysBusDevice *sbd = SYS_BUS_DEVICE(s);
136      int i = s->num_irq - GIC_INTERNAL;
137  
138      /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
139       * GPIO array layout is thus:
140       *  [0..N-1] SPIs
141       *  [N..N+31] PPIs for CPU 0
142       *  [N+32..N+63] PPIs for CPU 1
143       *   ...
144       */
145      i += (GIC_INTERNAL * s->num_cpu);
146      qdev_init_gpio_in(DEVICE(s), handler, i);
147  
148      for (i = 0; i < s->num_cpu; i++) {
149          sysbus_init_irq(sbd, &s->parent_irq[i]);
150      }
151      for (i = 0; i < s->num_cpu; i++) {
152          sysbus_init_irq(sbd, &s->parent_fiq[i]);
153      }
154      for (i = 0; i < s->num_cpu; i++) {
155          sysbus_init_irq(sbd, &s->parent_virq[i]);
156      }
157      for (i = 0; i < s->num_cpu; i++) {
158          sysbus_init_irq(sbd, &s->parent_vfiq[i]);
159      }
160      if (s->virt_extn) {
161          for (i = 0; i < s->num_cpu; i++) {
162              sysbus_init_irq(sbd, &s->maintenance_irq[i]);
163          }
164      }
165  
166      /* Distributor */
167      memory_region_init_io(&s->iomem, OBJECT(s), ops, s, "gic_dist", 0x1000);
168      sysbus_init_mmio(sbd, &s->iomem);
169  
170      /* This is the main CPU interface "for this core". It is always
171       * present because it is required by both software emulation and KVM.
172       */
173      memory_region_init_io(&s->cpuiomem[0], OBJECT(s), ops ? &ops[1] : NULL,
174                            s, "gic_cpu", s->revision == 2 ? 0x2000 : 0x100);
175      sysbus_init_mmio(sbd, &s->cpuiomem[0]);
176  
177      if (s->virt_extn) {
178          memory_region_init_io(&s->vifaceiomem[0], OBJECT(s), virt_ops,
179                                s, "gic_viface", 0x1000);
180          sysbus_init_mmio(sbd, &s->vifaceiomem[0]);
181  
182          memory_region_init_io(&s->vcpuiomem, OBJECT(s),
183                                virt_ops ? &virt_ops[1] : NULL,
184                                s, "gic_vcpu", 0x2000);
185          sysbus_init_mmio(sbd, &s->vcpuiomem);
186      }
187  }
188  
189  static void arm_gic_common_realize(DeviceState *dev, Error **errp)
190  {
191      GICState *s = ARM_GIC_COMMON(dev);
192      int num_irq = s->num_irq;
193  
194      if (s->num_cpu > GIC_NCPU) {
195          error_setg(errp, "requested %u CPUs exceeds GIC maximum %d",
196                     s->num_cpu, GIC_NCPU);
197          return;
198      }
199      if (s->num_irq > GIC_MAXIRQ) {
200          error_setg(errp,
201                     "requested %u interrupt lines exceeds GIC maximum %d",
202                     num_irq, GIC_MAXIRQ);
203          return;
204      }
205      /* ITLinesNumber is represented as (N / 32) - 1 (see
206       * gic_dist_readb) so this is an implementation imposed
207       * restriction, not an architectural one:
208       */
209      if (s->num_irq < 32 || (s->num_irq % 32)) {
210          error_setg(errp,
211                     "%d interrupt lines unsupported: not divisible by 32",
212                     num_irq);
213          return;
214      }
215  
216      if (s->security_extn &&
217          (s->revision == REV_11MPCORE)) {
218          error_setg(errp, "this GIC revision does not implement "
219                     "the security extensions");
220          return;
221      }
222  
223      if (s->virt_extn) {
224          if (s->revision != 2) {
225              error_setg(errp, "GIC virtualization extensions are only "
226                         "supported by revision 2");
227              return;
228          }
229  
230          /* For now, set the number of implemented LRs to 4, as found in most
231           * real GICv2. This could be promoted as a QOM property if we need to
232           * emulate a variant with another num_lrs.
233           */
234          s->num_lrs = 4;
235      }
236  }
237  
238  static inline void arm_gic_common_reset_irq_state(GICState *s, int cidx,
239                                                    int resetprio)
240  {
241      int i, j;
242  
243      for (i = cidx; i < cidx + s->num_cpu; i++) {
244          if (s->revision == REV_11MPCORE) {
245              s->priority_mask[i] = 0xf0;
246          } else {
247              s->priority_mask[i] = resetprio;
248          }
249          s->current_pending[i] = 1023;
250          s->running_priority[i] = 0x100;
251          s->cpu_ctlr[i] = 0;
252          s->bpr[i] = gic_is_vcpu(i) ? GIC_VIRT_MIN_BPR : GIC_MIN_BPR;
253          s->abpr[i] = gic_is_vcpu(i) ? GIC_VIRT_MIN_ABPR : GIC_MIN_ABPR;
254  
255          if (!gic_is_vcpu(i)) {
256              for (j = 0; j < GIC_INTERNAL; j++) {
257                  s->priority1[j][i] = resetprio;
258              }
259              for (j = 0; j < GIC_NR_SGIS; j++) {
260                  s->sgi_pending[j][i] = 0;
261              }
262          }
263      }
264  }
265  
266  static void arm_gic_common_reset_hold(Object *obj, ResetType type)
267  {
268      GICState *s = ARM_GIC_COMMON(obj);
269      int i, j;
270      int resetprio;
271  
272      /* If we're resetting a TZ-aware GIC as if secure firmware
273       * had set it up ready to start a kernel in non-secure,
274       * we need to set interrupt priorities to a "zero for the
275       * NS view" value. This is particularly critical for the
276       * priority_mask[] values, because if they are zero then NS
277       * code cannot ever rewrite the priority to anything else.
278       */
279      if (s->security_extn && s->irq_reset_nonsecure) {
280          resetprio = 0x80;
281      } else {
282          resetprio = 0;
283      }
284  
285      memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state));
286      arm_gic_common_reset_irq_state(s, 0, resetprio);
287  
288      if (s->virt_extn) {
289          /* vCPU states are stored at indexes GIC_NCPU .. GIC_NCPU+num_cpu.
290           * The exposed vCPU interface does not have security extensions.
291           */
292          arm_gic_common_reset_irq_state(s, GIC_NCPU, 0);
293      }
294  
295      for (i = 0; i < GIC_NR_SGIS; i++) {
296          GIC_DIST_SET_ENABLED(i, ALL_CPU_MASK);
297          GIC_DIST_SET_EDGE_TRIGGER(i);
298      }
299  
300      for (i = 0; i < ARRAY_SIZE(s->priority2); i++) {
301          s->priority2[i] = resetprio;
302      }
303  
304      for (i = 0; i < GIC_MAXIRQ; i++) {
305          /* For uniprocessor GICs all interrupts always target the sole CPU */
306          if (s->num_cpu == 1) {
307              s->irq_target[i] = 1;
308          } else {
309              s->irq_target[i] = 0;
310          }
311      }
312      if (s->security_extn && s->irq_reset_nonsecure) {
313          for (i = 0; i < GIC_MAXIRQ; i++) {
314              GIC_DIST_SET_GROUP(i, ALL_CPU_MASK);
315          }
316      }
317  
318      if (s->virt_extn) {
319          for (i = 0; i < s->num_lrs; i++) {
320              for (j = 0; j < s->num_cpu; j++) {
321                  s->h_lr[i][j] = 0;
322              }
323          }
324  
325          for (i = 0; i < s->num_cpu; i++) {
326              s->h_hcr[i] = 0;
327              s->h_misr[i] = 0;
328          }
329      }
330  
331      s->ctlr = 0;
332  }
333  
334  static void arm_gic_common_linux_init(ARMLinuxBootIf *obj,
335                                        bool secure_boot)
336  {
337      GICState *s = ARM_GIC_COMMON(obj);
338  
339      if (s->security_extn && !secure_boot) {
340          /* We're directly booting a kernel into NonSecure. If this GIC
341           * implements the security extensions then we must configure it
342           * to have all the interrupts be NonSecure (this is a job that
343           * is done by the Secure boot firmware in real hardware, and in
344           * this mode QEMU is acting as a minimalist firmware-and-bootloader
345           * equivalent).
346           */
347          s->irq_reset_nonsecure = true;
348      }
349  }
350  
351  static Property arm_gic_common_properties[] = {
352      DEFINE_PROP_UINT32("num-cpu", GICState, num_cpu, 1),
353      DEFINE_PROP_UINT32("num-irq", GICState, num_irq, 32),
354      /* Revision can be 1 or 2 for GIC architecture specification
355       * versions 1 or 2, or 0 to indicate the legacy 11MPCore GIC.
356       */
357      DEFINE_PROP_UINT32("revision", GICState, revision, 1),
358      /* True if the GIC should implement the security extensions */
359      DEFINE_PROP_BOOL("has-security-extensions", GICState, security_extn, 0),
360      /* True if the GIC should implement the virtualization extensions */
361      DEFINE_PROP_BOOL("has-virtualization-extensions", GICState, virt_extn, 0),
362      DEFINE_PROP_UINT32("num-priority-bits", GICState, n_prio_bits, 8),
363      DEFINE_PROP_END_OF_LIST(),
364  };
365  
366  static void arm_gic_common_class_init(ObjectClass *klass, void *data)
367  {
368      DeviceClass *dc = DEVICE_CLASS(klass);
369      ResettableClass *rc = RESETTABLE_CLASS(klass);
370      ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass);
371  
372      rc->phases.hold = arm_gic_common_reset_hold;
373      dc->realize = arm_gic_common_realize;
374      device_class_set_props(dc, arm_gic_common_properties);
375      dc->vmsd = &vmstate_gic;
376      albifc->arm_linux_init = arm_gic_common_linux_init;
377  }
378  
379  static const TypeInfo arm_gic_common_type = {
380      .name = TYPE_ARM_GIC_COMMON,
381      .parent = TYPE_SYS_BUS_DEVICE,
382      .instance_size = sizeof(GICState),
383      .class_size = sizeof(ARMGICCommonClass),
384      .class_init = arm_gic_common_class_init,
385      .abstract = true,
386      .interfaces = (InterfaceInfo []) {
387          { TYPE_ARM_LINUX_BOOT_IF },
388          { },
389      },
390  };
391  
392  static void register_types(void)
393  {
394      type_register_static(&arm_gic_common_type);
395  }
396  
397  type_init(register_types)
398  
399  const char *gic_class_name(void)
400  {
401      return kvm_irqchip_in_kernel() ? "kvm-arm-gic" : "arm_gic";
402  }
403