1 /* 2 * ARM GIC support - common bits of emulated and KVM kernel model 3 * 4 * Copyright (c) 2012 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation, either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "gic_internal.h" 22 23 static void gic_pre_save(void *opaque) 24 { 25 GICState *s = (GICState *)opaque; 26 ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s); 27 28 if (c->pre_save) { 29 c->pre_save(s); 30 } 31 } 32 33 static int gic_post_load(void *opaque, int version_id) 34 { 35 GICState *s = (GICState *)opaque; 36 ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s); 37 38 if (c->post_load) { 39 c->post_load(s); 40 } 41 return 0; 42 } 43 44 static const VMStateDescription vmstate_gic_irq_state = { 45 .name = "arm_gic_irq_state", 46 .version_id = 1, 47 .minimum_version_id = 1, 48 .fields = (VMStateField[]) { 49 VMSTATE_UINT8(enabled, gic_irq_state), 50 VMSTATE_UINT8(pending, gic_irq_state), 51 VMSTATE_UINT8(active, gic_irq_state), 52 VMSTATE_UINT8(level, gic_irq_state), 53 VMSTATE_BOOL(model, gic_irq_state), 54 VMSTATE_BOOL(edge_trigger, gic_irq_state), 55 VMSTATE_UINT8(group, gic_irq_state), 56 VMSTATE_END_OF_LIST() 57 } 58 }; 59 60 static const VMStateDescription vmstate_gic = { 61 .name = "arm_gic", 62 .version_id = 11, 63 .minimum_version_id = 11, 64 .pre_save = gic_pre_save, 65 .post_load = gic_post_load, 66 .fields = (VMStateField[]) { 67 VMSTATE_UINT32(ctlr, GICState), 68 VMSTATE_UINT32_ARRAY(cpu_ctlr, GICState, GIC_NCPU), 69 VMSTATE_STRUCT_ARRAY(irq_state, GICState, GIC_MAXIRQ, 1, 70 vmstate_gic_irq_state, gic_irq_state), 71 VMSTATE_UINT8_ARRAY(irq_target, GICState, GIC_MAXIRQ), 72 VMSTATE_UINT8_2DARRAY(priority1, GICState, GIC_INTERNAL, GIC_NCPU), 73 VMSTATE_UINT8_ARRAY(priority2, GICState, GIC_MAXIRQ - GIC_INTERNAL), 74 VMSTATE_UINT16_2DARRAY(last_active, GICState, GIC_MAXIRQ, GIC_NCPU), 75 VMSTATE_UINT8_2DARRAY(sgi_pending, GICState, GIC_NR_SGIS, GIC_NCPU), 76 VMSTATE_UINT16_ARRAY(priority_mask, GICState, GIC_NCPU), 77 VMSTATE_UINT16_ARRAY(running_irq, GICState, GIC_NCPU), 78 VMSTATE_UINT16_ARRAY(running_priority, GICState, GIC_NCPU), 79 VMSTATE_UINT16_ARRAY(current_pending, GICState, GIC_NCPU), 80 VMSTATE_UINT8_ARRAY(bpr, GICState, GIC_NCPU), 81 VMSTATE_UINT8_ARRAY(abpr, GICState, GIC_NCPU), 82 VMSTATE_UINT32_2DARRAY(apr, GICState, GIC_NR_APRS, GIC_NCPU), 83 VMSTATE_UINT32_2DARRAY(nsapr, GICState, GIC_NR_APRS, GIC_NCPU), 84 VMSTATE_END_OF_LIST() 85 } 86 }; 87 88 void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler, 89 const MemoryRegionOps *ops) 90 { 91 SysBusDevice *sbd = SYS_BUS_DEVICE(s); 92 int i = s->num_irq - GIC_INTERNAL; 93 94 /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU. 95 * GPIO array layout is thus: 96 * [0..N-1] SPIs 97 * [N..N+31] PPIs for CPU 0 98 * [N+32..N+63] PPIs for CPU 1 99 * ... 100 */ 101 if (s->revision != REV_NVIC) { 102 i += (GIC_INTERNAL * s->num_cpu); 103 } 104 qdev_init_gpio_in(DEVICE(s), handler, i); 105 106 for (i = 0; i < s->num_cpu; i++) { 107 sysbus_init_irq(sbd, &s->parent_irq[i]); 108 } 109 for (i = 0; i < s->num_cpu; i++) { 110 sysbus_init_irq(sbd, &s->parent_fiq[i]); 111 } 112 113 /* Distributor */ 114 memory_region_init_io(&s->iomem, OBJECT(s), ops, s, "gic_dist", 0x1000); 115 sysbus_init_mmio(sbd, &s->iomem); 116 117 if (s->revision != REV_NVIC) { 118 /* This is the main CPU interface "for this core". It is always 119 * present because it is required by both software emulation and KVM. 120 * NVIC is not handled here because its CPU interface is different, 121 * neither it can use KVM. 122 */ 123 memory_region_init_io(&s->cpuiomem[0], OBJECT(s), ops ? &ops[1] : NULL, 124 s, "gic_cpu", s->revision == 2 ? 0x1000 : 0x100); 125 sysbus_init_mmio(sbd, &s->cpuiomem[0]); 126 } 127 } 128 129 static void arm_gic_common_realize(DeviceState *dev, Error **errp) 130 { 131 GICState *s = ARM_GIC_COMMON(dev); 132 int num_irq = s->num_irq; 133 134 if (s->num_cpu > GIC_NCPU) { 135 error_setg(errp, "requested %u CPUs exceeds GIC maximum %d", 136 s->num_cpu, GIC_NCPU); 137 return; 138 } 139 s->num_irq += GIC_BASE_IRQ; 140 if (s->num_irq > GIC_MAXIRQ) { 141 error_setg(errp, 142 "requested %u interrupt lines exceeds GIC maximum %d", 143 num_irq, GIC_MAXIRQ); 144 return; 145 } 146 /* ITLinesNumber is represented as (N / 32) - 1 (see 147 * gic_dist_readb) so this is an implementation imposed 148 * restriction, not an architectural one: 149 */ 150 if (s->num_irq < 32 || (s->num_irq % 32)) { 151 error_setg(errp, 152 "%d interrupt lines unsupported: not divisible by 32", 153 num_irq); 154 return; 155 } 156 157 if (s->security_extn && 158 (s->revision == REV_11MPCORE || s->revision == REV_NVIC)) { 159 error_setg(errp, "this GIC revision does not implement " 160 "the security extensions"); 161 return; 162 } 163 } 164 165 static void arm_gic_common_reset(DeviceState *dev) 166 { 167 GICState *s = ARM_GIC_COMMON(dev); 168 int i, j; 169 memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state)); 170 for (i = 0 ; i < s->num_cpu; i++) { 171 if (s->revision == REV_11MPCORE) { 172 s->priority_mask[i] = 0xf0; 173 } else { 174 s->priority_mask[i] = 0; 175 } 176 s->current_pending[i] = 1023; 177 s->running_irq[i] = 1023; 178 s->running_priority[i] = 0x100; 179 s->cpu_ctlr[i] = 0; 180 s->bpr[i] = GIC_MIN_BPR; 181 s->abpr[i] = GIC_MIN_ABPR; 182 for (j = 0; j < GIC_INTERNAL; j++) { 183 s->priority1[j][i] = 0; 184 } 185 for (j = 0; j < GIC_NR_SGIS; j++) { 186 s->sgi_pending[j][i] = 0; 187 } 188 } 189 for (i = 0; i < GIC_NR_SGIS; i++) { 190 GIC_SET_ENABLED(i, ALL_CPU_MASK); 191 GIC_SET_EDGE_TRIGGER(i); 192 } 193 194 for (i = 0; i < ARRAY_SIZE(s->priority2); i++) { 195 s->priority2[i] = 0; 196 } 197 198 for (i = 0; i < GIC_MAXIRQ; i++) { 199 /* For uniprocessor GICs all interrupts always target the sole CPU */ 200 if (s->num_cpu == 1) { 201 s->irq_target[i] = 1; 202 } else { 203 s->irq_target[i] = 0; 204 } 205 } 206 s->ctlr = 0; 207 } 208 209 static Property arm_gic_common_properties[] = { 210 DEFINE_PROP_UINT32("num-cpu", GICState, num_cpu, 1), 211 DEFINE_PROP_UINT32("num-irq", GICState, num_irq, 32), 212 /* Revision can be 1 or 2 for GIC architecture specification 213 * versions 1 or 2, or 0 to indicate the legacy 11MPCore GIC. 214 * (Internally, 0xffffffff also indicates "not a GIC but an NVIC".) 215 */ 216 DEFINE_PROP_UINT32("revision", GICState, revision, 1), 217 /* True if the GIC should implement the security extensions */ 218 DEFINE_PROP_BOOL("has-security-extensions", GICState, security_extn, 0), 219 DEFINE_PROP_END_OF_LIST(), 220 }; 221 222 static void arm_gic_common_class_init(ObjectClass *klass, void *data) 223 { 224 DeviceClass *dc = DEVICE_CLASS(klass); 225 226 dc->reset = arm_gic_common_reset; 227 dc->realize = arm_gic_common_realize; 228 dc->props = arm_gic_common_properties; 229 dc->vmsd = &vmstate_gic; 230 } 231 232 static const TypeInfo arm_gic_common_type = { 233 .name = TYPE_ARM_GIC_COMMON, 234 .parent = TYPE_SYS_BUS_DEVICE, 235 .instance_size = sizeof(GICState), 236 .class_size = sizeof(ARMGICCommonClass), 237 .class_init = arm_gic_common_class_init, 238 .abstract = true, 239 }; 240 241 static void register_types(void) 242 { 243 type_register_static(&arm_gic_common_type); 244 } 245 246 type_init(register_types) 247