1 /* 2 * ARM Generic/Distributed Interrupt Controller 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 /* This file contains implementation code for the RealView EB interrupt 11 * controller, MPCore distributed interrupt controller and ARMv7-M 12 * Nested Vectored Interrupt Controller. 13 * It is compiled in two ways: 14 * (1) as a standalone file to produce a sysbus device which is a GIC 15 * that can be used on the realview board and as one of the builtin 16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc) 17 * (2) by being directly #included into armv7m_nvic.c to produce the 18 * armv7m_nvic device. 19 */ 20 21 #include "hw/sysbus.h" 22 #include "gic_internal.h" 23 #include "qom/cpu.h" 24 25 //#define DEBUG_GIC 26 27 #ifdef DEBUG_GIC 28 #define DPRINTF(fmt, ...) \ 29 do { fprintf(stderr, "arm_gic: " fmt , ## __VA_ARGS__); } while (0) 30 #else 31 #define DPRINTF(fmt, ...) do {} while(0) 32 #endif 33 34 static const uint8_t gic_id[] = { 35 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 36 }; 37 38 #define NUM_CPU(s) ((s)->num_cpu) 39 40 static inline int gic_get_current_cpu(GICState *s) 41 { 42 if (s->num_cpu > 1) { 43 return current_cpu->cpu_index; 44 } 45 return 0; 46 } 47 48 /* Return true if this GIC config has interrupt groups, which is 49 * true if we're a GICv2, or a GICv1 with the security extensions. 50 */ 51 static inline bool gic_has_groups(GICState *s) 52 { 53 return s->revision == 2 || s->security_extn; 54 } 55 56 /* TODO: Many places that call this routine could be optimized. */ 57 /* Update interrupt status after enabled or pending bits have been changed. */ 58 void gic_update(GICState *s) 59 { 60 int best_irq; 61 int best_prio; 62 int irq; 63 int level; 64 int cpu; 65 int cm; 66 67 for (cpu = 0; cpu < NUM_CPU(s); cpu++) { 68 cm = 1 << cpu; 69 s->current_pending[cpu] = 1023; 70 if (!(s->ctlr & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1)) 71 || !(s->cpu_ctlr[cpu] & (GICC_CTLR_EN_GRP0 | GICC_CTLR_EN_GRP1))) { 72 qemu_irq_lower(s->parent_irq[cpu]); 73 return; 74 } 75 best_prio = 0x100; 76 best_irq = 1023; 77 for (irq = 0; irq < s->num_irq; irq++) { 78 if (GIC_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm) && 79 (irq < GIC_INTERNAL || GIC_TARGET(irq) & cm)) { 80 if (GIC_GET_PRIORITY(irq, cpu) < best_prio) { 81 best_prio = GIC_GET_PRIORITY(irq, cpu); 82 best_irq = irq; 83 } 84 } 85 } 86 level = 0; 87 if (best_prio < s->priority_mask[cpu]) { 88 s->current_pending[cpu] = best_irq; 89 if (best_prio < s->running_priority[cpu]) { 90 DPRINTF("Raised pending IRQ %d (cpu %d)\n", best_irq, cpu); 91 level = 1; 92 } 93 } 94 qemu_set_irq(s->parent_irq[cpu], level); 95 } 96 } 97 98 void gic_set_pending_private(GICState *s, int cpu, int irq) 99 { 100 int cm = 1 << cpu; 101 102 if (gic_test_pending(s, irq, cm)) { 103 return; 104 } 105 106 DPRINTF("Set %d pending cpu %d\n", irq, cpu); 107 GIC_SET_PENDING(irq, cm); 108 gic_update(s); 109 } 110 111 static void gic_set_irq_11mpcore(GICState *s, int irq, int level, 112 int cm, int target) 113 { 114 if (level) { 115 GIC_SET_LEVEL(irq, cm); 116 if (GIC_TEST_EDGE_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) { 117 DPRINTF("Set %d pending mask %x\n", irq, target); 118 GIC_SET_PENDING(irq, target); 119 } 120 } else { 121 GIC_CLEAR_LEVEL(irq, cm); 122 } 123 } 124 125 static void gic_set_irq_generic(GICState *s, int irq, int level, 126 int cm, int target) 127 { 128 if (level) { 129 GIC_SET_LEVEL(irq, cm); 130 DPRINTF("Set %d pending mask %x\n", irq, target); 131 if (GIC_TEST_EDGE_TRIGGER(irq)) { 132 GIC_SET_PENDING(irq, target); 133 } 134 } else { 135 GIC_CLEAR_LEVEL(irq, cm); 136 } 137 } 138 139 /* Process a change in an external IRQ input. */ 140 static void gic_set_irq(void *opaque, int irq, int level) 141 { 142 /* Meaning of the 'irq' parameter: 143 * [0..N-1] : external interrupts 144 * [N..N+31] : PPI (internal) interrupts for CPU 0 145 * [N+32..N+63] : PPI (internal interrupts for CPU 1 146 * ... 147 */ 148 GICState *s = (GICState *)opaque; 149 int cm, target; 150 if (irq < (s->num_irq - GIC_INTERNAL)) { 151 /* The first external input line is internal interrupt 32. */ 152 cm = ALL_CPU_MASK; 153 irq += GIC_INTERNAL; 154 target = GIC_TARGET(irq); 155 } else { 156 int cpu; 157 irq -= (s->num_irq - GIC_INTERNAL); 158 cpu = irq / GIC_INTERNAL; 159 irq %= GIC_INTERNAL; 160 cm = 1 << cpu; 161 target = cm; 162 } 163 164 assert(irq >= GIC_NR_SGIS); 165 166 if (level == GIC_TEST_LEVEL(irq, cm)) { 167 return; 168 } 169 170 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 171 gic_set_irq_11mpcore(s, irq, level, cm, target); 172 } else { 173 gic_set_irq_generic(s, irq, level, cm, target); 174 } 175 176 gic_update(s); 177 } 178 179 static uint16_t gic_get_current_pending_irq(GICState *s, int cpu, 180 MemTxAttrs attrs) 181 { 182 uint16_t pending_irq = s->current_pending[cpu]; 183 184 if (pending_irq < GIC_MAXIRQ && gic_has_groups(s)) { 185 int group = GIC_TEST_GROUP(pending_irq, (1 << cpu)); 186 /* On a GIC without the security extensions, reading this register 187 * behaves in the same way as a secure access to a GIC with them. 188 */ 189 bool secure = !s->security_extn || attrs.secure; 190 191 if (group == 0 && !secure) { 192 /* Group0 interrupts hidden from Non-secure access */ 193 return 1023; 194 } 195 if (group == 1 && secure && !(s->cpu_ctlr[cpu] & GICC_CTLR_ACK_CTL)) { 196 /* Group1 interrupts only seen by Secure access if 197 * AckCtl bit set. 198 */ 199 return 1022; 200 } 201 } 202 return pending_irq; 203 } 204 205 static void gic_set_running_irq(GICState *s, int cpu, int irq) 206 { 207 s->running_irq[cpu] = irq; 208 if (irq == 1023) { 209 s->running_priority[cpu] = 0x100; 210 } else { 211 s->running_priority[cpu] = GIC_GET_PRIORITY(irq, cpu); 212 } 213 gic_update(s); 214 } 215 216 uint32_t gic_acknowledge_irq(GICState *s, int cpu) 217 { 218 int ret, irq, src; 219 int cm = 1 << cpu; 220 irq = s->current_pending[cpu]; 221 if (irq == 1023 222 || GIC_GET_PRIORITY(irq, cpu) >= s->running_priority[cpu]) { 223 DPRINTF("ACK no pending IRQ\n"); 224 return 1023; 225 } 226 s->last_active[irq][cpu] = s->running_irq[cpu]; 227 228 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 229 /* Clear pending flags for both level and edge triggered interrupts. 230 * Level triggered IRQs will be reasserted once they become inactive. 231 */ 232 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 233 ret = irq; 234 } else { 235 if (irq < GIC_NR_SGIS) { 236 /* Lookup the source CPU for the SGI and clear this in the 237 * sgi_pending map. Return the src and clear the overall pending 238 * state on this CPU if the SGI is not pending from any CPUs. 239 */ 240 assert(s->sgi_pending[irq][cpu] != 0); 241 src = ctz32(s->sgi_pending[irq][cpu]); 242 s->sgi_pending[irq][cpu] &= ~(1 << src); 243 if (s->sgi_pending[irq][cpu] == 0) { 244 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 245 } 246 ret = irq | ((src & 0x7) << 10); 247 } else { 248 /* Clear pending state for both level and edge triggered 249 * interrupts. (level triggered interrupts with an active line 250 * remain pending, see gic_test_pending) 251 */ 252 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 253 ret = irq; 254 } 255 } 256 257 gic_set_running_irq(s, cpu, irq); 258 DPRINTF("ACK %d\n", irq); 259 return ret; 260 } 261 262 void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val, 263 MemTxAttrs attrs) 264 { 265 if (s->security_extn && !attrs.secure) { 266 if (!GIC_TEST_GROUP(irq, (1 << cpu))) { 267 return; /* Ignore Non-secure access of Group0 IRQ */ 268 } 269 val = 0x80 | (val >> 1); /* Non-secure view */ 270 } 271 272 if (irq < GIC_INTERNAL) { 273 s->priority1[irq][cpu] = val; 274 } else { 275 s->priority2[(irq) - GIC_INTERNAL] = val; 276 } 277 } 278 279 static uint32_t gic_get_priority(GICState *s, int cpu, int irq, 280 MemTxAttrs attrs) 281 { 282 uint32_t prio = GIC_GET_PRIORITY(irq, cpu); 283 284 if (s->security_extn && !attrs.secure) { 285 if (!GIC_TEST_GROUP(irq, (1 << cpu))) { 286 return 0; /* Non-secure access cannot read priority of Group0 IRQ */ 287 } 288 prio = (prio << 1) & 0xff; /* Non-secure view */ 289 } 290 return prio; 291 } 292 293 static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, 294 MemTxAttrs attrs) 295 { 296 if (s->security_extn && !attrs.secure) { 297 if (s->priority_mask[cpu] & 0x80) { 298 /* Priority Mask in upper half */ 299 pmask = 0x80 | (pmask >> 1); 300 } else { 301 /* Non-secure write ignored if priority mask is in lower half */ 302 return; 303 } 304 } 305 s->priority_mask[cpu] = pmask; 306 } 307 308 static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs) 309 { 310 uint32_t pmask = s->priority_mask[cpu]; 311 312 if (s->security_extn && !attrs.secure) { 313 if (pmask & 0x80) { 314 /* Priority Mask in upper half, return Non-secure view */ 315 pmask = (pmask << 1) & 0xff; 316 } else { 317 /* Priority Mask in lower half, RAZ */ 318 pmask = 0; 319 } 320 } 321 return pmask; 322 } 323 324 static uint32_t gic_get_cpu_control(GICState *s, int cpu, MemTxAttrs attrs) 325 { 326 uint32_t ret = s->cpu_ctlr[cpu]; 327 328 if (s->security_extn && !attrs.secure) { 329 /* Construct the NS banked view of GICC_CTLR from the correct 330 * bits of the S banked view. We don't need to move the bypass 331 * control bits because we don't implement that (IMPDEF) part 332 * of the GIC architecture. 333 */ 334 ret = (ret & (GICC_CTLR_EN_GRP1 | GICC_CTLR_EOIMODE_NS)) >> 1; 335 } 336 return ret; 337 } 338 339 static void gic_set_cpu_control(GICState *s, int cpu, uint32_t value, 340 MemTxAttrs attrs) 341 { 342 uint32_t mask; 343 344 if (s->security_extn && !attrs.secure) { 345 /* The NS view can only write certain bits in the register; 346 * the rest are unchanged 347 */ 348 mask = GICC_CTLR_EN_GRP1; 349 if (s->revision == 2) { 350 mask |= GICC_CTLR_EOIMODE_NS; 351 } 352 s->cpu_ctlr[cpu] &= ~mask; 353 s->cpu_ctlr[cpu] |= (value << 1) & mask; 354 } else { 355 if (s->revision == 2) { 356 mask = s->security_extn ? GICC_CTLR_V2_S_MASK : GICC_CTLR_V2_MASK; 357 } else { 358 mask = s->security_extn ? GICC_CTLR_V1_S_MASK : GICC_CTLR_V1_MASK; 359 } 360 s->cpu_ctlr[cpu] = value & mask; 361 } 362 DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, " 363 "Group1 Interrupts %sabled\n", cpu, 364 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP0) ? "En" : "Dis", 365 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP1) ? "En" : "Dis"); 366 } 367 368 static uint8_t gic_get_running_priority(GICState *s, int cpu, MemTxAttrs attrs) 369 { 370 if (s->security_extn && !attrs.secure) { 371 if (s->running_priority[cpu] & 0x80) { 372 /* Running priority in upper half of range: return the Non-secure 373 * view of the priority. 374 */ 375 return s->running_priority[cpu] << 1; 376 } else { 377 /* Running priority in lower half of range: RAZ */ 378 return 0; 379 } 380 } else { 381 return s->running_priority[cpu]; 382 } 383 } 384 385 void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) 386 { 387 int update = 0; 388 int cm = 1 << cpu; 389 DPRINTF("EOI %d\n", irq); 390 if (irq >= s->num_irq) { 391 /* This handles two cases: 392 * 1. If software writes the ID of a spurious interrupt [ie 1023] 393 * to the GICC_EOIR, the GIC ignores that write. 394 * 2. If software writes the number of a non-existent interrupt 395 * this must be a subcase of "value written does not match the last 396 * valid interrupt value read from the Interrupt Acknowledge 397 * register" and so this is UNPREDICTABLE. We choose to ignore it. 398 */ 399 return; 400 } 401 if (s->running_irq[cpu] == 1023) 402 return; /* No active IRQ. */ 403 404 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 405 /* Mark level triggered interrupts as pending if they are still 406 raised. */ 407 if (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm) 408 && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) { 409 DPRINTF("Set %d pending mask %x\n", irq, cm); 410 GIC_SET_PENDING(irq, cm); 411 update = 1; 412 } 413 } 414 415 if (s->security_extn && !attrs.secure && !GIC_TEST_GROUP(irq, cm)) { 416 DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq); 417 return; 418 } 419 420 /* Secure EOI with GICC_CTLR.AckCtl == 0 when the IRQ is a Group 1 421 * interrupt is UNPREDICTABLE. We choose to handle it as if AckCtl == 1, 422 * i.e. go ahead and complete the irq anyway. 423 */ 424 425 if (irq != s->running_irq[cpu]) { 426 /* Complete an IRQ that is not currently running. */ 427 int tmp = s->running_irq[cpu]; 428 while (s->last_active[tmp][cpu] != 1023) { 429 if (s->last_active[tmp][cpu] == irq) { 430 s->last_active[tmp][cpu] = s->last_active[irq][cpu]; 431 break; 432 } 433 tmp = s->last_active[tmp][cpu]; 434 } 435 if (update) { 436 gic_update(s); 437 } 438 } else { 439 /* Complete the current running IRQ. */ 440 gic_set_running_irq(s, cpu, s->last_active[s->running_irq[cpu]][cpu]); 441 } 442 } 443 444 static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) 445 { 446 GICState *s = (GICState *)opaque; 447 uint32_t res; 448 int irq; 449 int i; 450 int cpu; 451 int cm; 452 int mask; 453 454 cpu = gic_get_current_cpu(s); 455 cm = 1 << cpu; 456 if (offset < 0x100) { 457 if (offset == 0) { /* GICD_CTLR */ 458 if (s->security_extn && !attrs.secure) { 459 /* The NS bank of this register is just an alias of the 460 * EnableGrp1 bit in the S bank version. 461 */ 462 return extract32(s->ctlr, 1, 1); 463 } else { 464 return s->ctlr; 465 } 466 } 467 if (offset == 4) 468 /* Interrupt Controller Type Register */ 469 return ((s->num_irq / 32) - 1) 470 | ((NUM_CPU(s) - 1) << 5) 471 | (s->security_extn << 10); 472 if (offset < 0x08) 473 return 0; 474 if (offset >= 0x80) { 475 /* Interrupt Group Registers: these RAZ/WI if this is an NS 476 * access to a GIC with the security extensions, or if the GIC 477 * doesn't have groups at all. 478 */ 479 res = 0; 480 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 481 /* Every byte offset holds 8 group status bits */ 482 irq = (offset - 0x080) * 8 + GIC_BASE_IRQ; 483 if (irq >= s->num_irq) { 484 goto bad_reg; 485 } 486 for (i = 0; i < 8; i++) { 487 if (GIC_TEST_GROUP(irq + i, cm)) { 488 res |= (1 << i); 489 } 490 } 491 } 492 return res; 493 } 494 goto bad_reg; 495 } else if (offset < 0x200) { 496 /* Interrupt Set/Clear Enable. */ 497 if (offset < 0x180) 498 irq = (offset - 0x100) * 8; 499 else 500 irq = (offset - 0x180) * 8; 501 irq += GIC_BASE_IRQ; 502 if (irq >= s->num_irq) 503 goto bad_reg; 504 res = 0; 505 for (i = 0; i < 8; i++) { 506 if (GIC_TEST_ENABLED(irq + i, cm)) { 507 res |= (1 << i); 508 } 509 } 510 } else if (offset < 0x300) { 511 /* Interrupt Set/Clear Pending. */ 512 if (offset < 0x280) 513 irq = (offset - 0x200) * 8; 514 else 515 irq = (offset - 0x280) * 8; 516 irq += GIC_BASE_IRQ; 517 if (irq >= s->num_irq) 518 goto bad_reg; 519 res = 0; 520 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 521 for (i = 0; i < 8; i++) { 522 if (gic_test_pending(s, irq + i, mask)) { 523 res |= (1 << i); 524 } 525 } 526 } else if (offset < 0x400) { 527 /* Interrupt Active. */ 528 irq = (offset - 0x300) * 8 + GIC_BASE_IRQ; 529 if (irq >= s->num_irq) 530 goto bad_reg; 531 res = 0; 532 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 533 for (i = 0; i < 8; i++) { 534 if (GIC_TEST_ACTIVE(irq + i, mask)) { 535 res |= (1 << i); 536 } 537 } 538 } else if (offset < 0x800) { 539 /* Interrupt Priority. */ 540 irq = (offset - 0x400) + GIC_BASE_IRQ; 541 if (irq >= s->num_irq) 542 goto bad_reg; 543 res = gic_get_priority(s, cpu, irq, attrs); 544 } else if (offset < 0xc00) { 545 /* Interrupt CPU Target. */ 546 if (s->num_cpu == 1 && s->revision != REV_11MPCORE) { 547 /* For uniprocessor GICs these RAZ/WI */ 548 res = 0; 549 } else { 550 irq = (offset - 0x800) + GIC_BASE_IRQ; 551 if (irq >= s->num_irq) { 552 goto bad_reg; 553 } 554 if (irq >= 29 && irq <= 31) { 555 res = cm; 556 } else { 557 res = GIC_TARGET(irq); 558 } 559 } 560 } else if (offset < 0xf00) { 561 /* Interrupt Configuration. */ 562 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 563 if (irq >= s->num_irq) 564 goto bad_reg; 565 res = 0; 566 for (i = 0; i < 4; i++) { 567 if (GIC_TEST_MODEL(irq + i)) 568 res |= (1 << (i * 2)); 569 if (GIC_TEST_EDGE_TRIGGER(irq + i)) 570 res |= (2 << (i * 2)); 571 } 572 } else if (offset < 0xf10) { 573 goto bad_reg; 574 } else if (offset < 0xf30) { 575 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 576 goto bad_reg; 577 } 578 579 if (offset < 0xf20) { 580 /* GICD_CPENDSGIRn */ 581 irq = (offset - 0xf10); 582 } else { 583 irq = (offset - 0xf20); 584 /* GICD_SPENDSGIRn */ 585 } 586 587 res = s->sgi_pending[irq][cpu]; 588 } else if (offset < 0xfe0) { 589 goto bad_reg; 590 } else /* offset >= 0xfe0 */ { 591 if (offset & 3) { 592 res = 0; 593 } else { 594 res = gic_id[(offset - 0xfe0) >> 2]; 595 } 596 } 597 return res; 598 bad_reg: 599 qemu_log_mask(LOG_GUEST_ERROR, 600 "gic_dist_readb: Bad offset %x\n", (int)offset); 601 return 0; 602 } 603 604 static MemTxResult gic_dist_read(void *opaque, hwaddr offset, uint64_t *data, 605 unsigned size, MemTxAttrs attrs) 606 { 607 switch (size) { 608 case 1: 609 *data = gic_dist_readb(opaque, offset, attrs); 610 return MEMTX_OK; 611 case 2: 612 *data = gic_dist_readb(opaque, offset, attrs); 613 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 614 return MEMTX_OK; 615 case 4: 616 *data = gic_dist_readb(opaque, offset, attrs); 617 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 618 *data |= gic_dist_readb(opaque, offset + 2, attrs) << 16; 619 *data |= gic_dist_readb(opaque, offset + 3, attrs) << 24; 620 return MEMTX_OK; 621 default: 622 return MEMTX_ERROR; 623 } 624 } 625 626 static void gic_dist_writeb(void *opaque, hwaddr offset, 627 uint32_t value, MemTxAttrs attrs) 628 { 629 GICState *s = (GICState *)opaque; 630 int irq; 631 int i; 632 int cpu; 633 634 cpu = gic_get_current_cpu(s); 635 if (offset < 0x100) { 636 if (offset == 0) { 637 if (s->security_extn && !attrs.secure) { 638 /* NS version is just an alias of the S version's bit 1 */ 639 s->ctlr = deposit32(s->ctlr, 1, 1, value); 640 } else if (gic_has_groups(s)) { 641 s->ctlr = value & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1); 642 } else { 643 s->ctlr = value & GICD_CTLR_EN_GRP0; 644 } 645 DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n", 646 s->ctlr & GICD_CTLR_EN_GRP0 ? "En" : "Dis", 647 s->ctlr & GICD_CTLR_EN_GRP1 ? "En" : "Dis"); 648 } else if (offset < 4) { 649 /* ignored. */ 650 } else if (offset >= 0x80) { 651 /* Interrupt Group Registers: RAZ/WI for NS access to secure 652 * GIC, or for GICs without groups. 653 */ 654 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 655 /* Every byte offset holds 8 group status bits */ 656 irq = (offset - 0x80) * 8 + GIC_BASE_IRQ; 657 if (irq >= s->num_irq) { 658 goto bad_reg; 659 } 660 for (i = 0; i < 8; i++) { 661 /* Group bits are banked for private interrupts */ 662 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 663 if (value & (1 << i)) { 664 /* Group1 (Non-secure) */ 665 GIC_SET_GROUP(irq + i, cm); 666 } else { 667 /* Group0 (Secure) */ 668 GIC_CLEAR_GROUP(irq + i, cm); 669 } 670 } 671 } 672 } else { 673 goto bad_reg; 674 } 675 } else if (offset < 0x180) { 676 /* Interrupt Set Enable. */ 677 irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; 678 if (irq >= s->num_irq) 679 goto bad_reg; 680 if (irq < GIC_NR_SGIS) { 681 value = 0xff; 682 } 683 684 for (i = 0; i < 8; i++) { 685 if (value & (1 << i)) { 686 int mask = 687 (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq + i); 688 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 689 690 if (!GIC_TEST_ENABLED(irq + i, cm)) { 691 DPRINTF("Enabled IRQ %d\n", irq + i); 692 } 693 GIC_SET_ENABLED(irq + i, cm); 694 /* If a raised level triggered IRQ enabled then mark 695 is as pending. */ 696 if (GIC_TEST_LEVEL(irq + i, mask) 697 && !GIC_TEST_EDGE_TRIGGER(irq + i)) { 698 DPRINTF("Set %d pending mask %x\n", irq + i, mask); 699 GIC_SET_PENDING(irq + i, mask); 700 } 701 } 702 } 703 } else if (offset < 0x200) { 704 /* Interrupt Clear Enable. */ 705 irq = (offset - 0x180) * 8 + GIC_BASE_IRQ; 706 if (irq >= s->num_irq) 707 goto bad_reg; 708 if (irq < GIC_NR_SGIS) { 709 value = 0; 710 } 711 712 for (i = 0; i < 8; i++) { 713 if (value & (1 << i)) { 714 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 715 716 if (GIC_TEST_ENABLED(irq + i, cm)) { 717 DPRINTF("Disabled IRQ %d\n", irq + i); 718 } 719 GIC_CLEAR_ENABLED(irq + i, cm); 720 } 721 } 722 } else if (offset < 0x280) { 723 /* Interrupt Set Pending. */ 724 irq = (offset - 0x200) * 8 + GIC_BASE_IRQ; 725 if (irq >= s->num_irq) 726 goto bad_reg; 727 if (irq < GIC_NR_SGIS) { 728 value = 0; 729 } 730 731 for (i = 0; i < 8; i++) { 732 if (value & (1 << i)) { 733 GIC_SET_PENDING(irq + i, GIC_TARGET(irq + i)); 734 } 735 } 736 } else if (offset < 0x300) { 737 /* Interrupt Clear Pending. */ 738 irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; 739 if (irq >= s->num_irq) 740 goto bad_reg; 741 if (irq < GIC_NR_SGIS) { 742 value = 0; 743 } 744 745 for (i = 0; i < 8; i++) { 746 /* ??? This currently clears the pending bit for all CPUs, even 747 for per-CPU interrupts. It's unclear whether this is the 748 corect behavior. */ 749 if (value & (1 << i)) { 750 GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK); 751 } 752 } 753 } else if (offset < 0x400) { 754 /* Interrupt Active. */ 755 goto bad_reg; 756 } else if (offset < 0x800) { 757 /* Interrupt Priority. */ 758 irq = (offset - 0x400) + GIC_BASE_IRQ; 759 if (irq >= s->num_irq) 760 goto bad_reg; 761 gic_set_priority(s, cpu, irq, value, attrs); 762 } else if (offset < 0xc00) { 763 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the 764 * annoying exception of the 11MPCore's GIC. 765 */ 766 if (s->num_cpu != 1 || s->revision == REV_11MPCORE) { 767 irq = (offset - 0x800) + GIC_BASE_IRQ; 768 if (irq >= s->num_irq) { 769 goto bad_reg; 770 } 771 if (irq < 29) { 772 value = 0; 773 } else if (irq < GIC_INTERNAL) { 774 value = ALL_CPU_MASK; 775 } 776 s->irq_target[irq] = value & ALL_CPU_MASK; 777 } 778 } else if (offset < 0xf00) { 779 /* Interrupt Configuration. */ 780 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 781 if (irq >= s->num_irq) 782 goto bad_reg; 783 if (irq < GIC_NR_SGIS) 784 value |= 0xaa; 785 for (i = 0; i < 4; i++) { 786 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 787 if (value & (1 << (i * 2))) { 788 GIC_SET_MODEL(irq + i); 789 } else { 790 GIC_CLEAR_MODEL(irq + i); 791 } 792 } 793 if (value & (2 << (i * 2))) { 794 GIC_SET_EDGE_TRIGGER(irq + i); 795 } else { 796 GIC_CLEAR_EDGE_TRIGGER(irq + i); 797 } 798 } 799 } else if (offset < 0xf10) { 800 /* 0xf00 is only handled for 32-bit writes. */ 801 goto bad_reg; 802 } else if (offset < 0xf20) { 803 /* GICD_CPENDSGIRn */ 804 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 805 goto bad_reg; 806 } 807 irq = (offset - 0xf10); 808 809 s->sgi_pending[irq][cpu] &= ~value; 810 if (s->sgi_pending[irq][cpu] == 0) { 811 GIC_CLEAR_PENDING(irq, 1 << cpu); 812 } 813 } else if (offset < 0xf30) { 814 /* GICD_SPENDSGIRn */ 815 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 816 goto bad_reg; 817 } 818 irq = (offset - 0xf20); 819 820 GIC_SET_PENDING(irq, 1 << cpu); 821 s->sgi_pending[irq][cpu] |= value; 822 } else { 823 goto bad_reg; 824 } 825 gic_update(s); 826 return; 827 bad_reg: 828 qemu_log_mask(LOG_GUEST_ERROR, 829 "gic_dist_writeb: Bad offset %x\n", (int)offset); 830 } 831 832 static void gic_dist_writew(void *opaque, hwaddr offset, 833 uint32_t value, MemTxAttrs attrs) 834 { 835 gic_dist_writeb(opaque, offset, value & 0xff, attrs); 836 gic_dist_writeb(opaque, offset + 1, value >> 8, attrs); 837 } 838 839 static void gic_dist_writel(void *opaque, hwaddr offset, 840 uint32_t value, MemTxAttrs attrs) 841 { 842 GICState *s = (GICState *)opaque; 843 if (offset == 0xf00) { 844 int cpu; 845 int irq; 846 int mask; 847 int target_cpu; 848 849 cpu = gic_get_current_cpu(s); 850 irq = value & 0x3ff; 851 switch ((value >> 24) & 3) { 852 case 0: 853 mask = (value >> 16) & ALL_CPU_MASK; 854 break; 855 case 1: 856 mask = ALL_CPU_MASK ^ (1 << cpu); 857 break; 858 case 2: 859 mask = 1 << cpu; 860 break; 861 default: 862 DPRINTF("Bad Soft Int target filter\n"); 863 mask = ALL_CPU_MASK; 864 break; 865 } 866 GIC_SET_PENDING(irq, mask); 867 target_cpu = ctz32(mask); 868 while (target_cpu < GIC_NCPU) { 869 s->sgi_pending[irq][target_cpu] |= (1 << cpu); 870 mask &= ~(1 << target_cpu); 871 target_cpu = ctz32(mask); 872 } 873 gic_update(s); 874 return; 875 } 876 gic_dist_writew(opaque, offset, value & 0xffff, attrs); 877 gic_dist_writew(opaque, offset + 2, value >> 16, attrs); 878 } 879 880 static MemTxResult gic_dist_write(void *opaque, hwaddr offset, uint64_t data, 881 unsigned size, MemTxAttrs attrs) 882 { 883 switch (size) { 884 case 1: 885 gic_dist_writeb(opaque, offset, data, attrs); 886 return MEMTX_OK; 887 case 2: 888 gic_dist_writew(opaque, offset, data, attrs); 889 return MEMTX_OK; 890 case 4: 891 gic_dist_writel(opaque, offset, data, attrs); 892 return MEMTX_OK; 893 default: 894 return MEMTX_ERROR; 895 } 896 } 897 898 static const MemoryRegionOps gic_dist_ops = { 899 .read_with_attrs = gic_dist_read, 900 .write_with_attrs = gic_dist_write, 901 .endianness = DEVICE_NATIVE_ENDIAN, 902 }; 903 904 static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset, 905 uint64_t *data, MemTxAttrs attrs) 906 { 907 switch (offset) { 908 case 0x00: /* Control */ 909 *data = gic_get_cpu_control(s, cpu, attrs); 910 break; 911 case 0x04: /* Priority mask */ 912 *data = gic_get_priority_mask(s, cpu, attrs); 913 break; 914 case 0x08: /* Binary Point */ 915 if (s->security_extn && !attrs.secure) { 916 /* BPR is banked. Non-secure copy stored in ABPR. */ 917 *data = s->abpr[cpu]; 918 } else { 919 *data = s->bpr[cpu]; 920 } 921 break; 922 case 0x0c: /* Acknowledge */ 923 *data = gic_acknowledge_irq(s, cpu); 924 break; 925 case 0x14: /* Running Priority */ 926 *data = gic_get_running_priority(s, cpu, attrs); 927 break; 928 case 0x18: /* Highest Pending Interrupt */ 929 *data = gic_get_current_pending_irq(s, cpu, attrs); 930 break; 931 case 0x1c: /* Aliased Binary Point */ 932 /* GIC v2, no security: ABPR 933 * GIC v1, no security: not implemented (RAZ/WI) 934 * With security extensions, secure access: ABPR (alias of NS BPR) 935 * With security extensions, nonsecure access: RAZ/WI 936 */ 937 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 938 *data = 0; 939 } else { 940 *data = s->abpr[cpu]; 941 } 942 break; 943 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 944 *data = s->apr[(offset - 0xd0) / 4][cpu]; 945 break; 946 default: 947 qemu_log_mask(LOG_GUEST_ERROR, 948 "gic_cpu_read: Bad offset %x\n", (int)offset); 949 return MEMTX_ERROR; 950 } 951 return MEMTX_OK; 952 } 953 954 static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset, 955 uint32_t value, MemTxAttrs attrs) 956 { 957 switch (offset) { 958 case 0x00: /* Control */ 959 gic_set_cpu_control(s, cpu, value, attrs); 960 break; 961 case 0x04: /* Priority mask */ 962 gic_set_priority_mask(s, cpu, value, attrs); 963 break; 964 case 0x08: /* Binary Point */ 965 if (s->security_extn && !attrs.secure) { 966 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 967 } else { 968 s->bpr[cpu] = MAX(value & 0x7, GIC_MIN_BPR); 969 } 970 break; 971 case 0x10: /* End Of Interrupt */ 972 gic_complete_irq(s, cpu, value & 0x3ff, attrs); 973 return MEMTX_OK; 974 case 0x1c: /* Aliased Binary Point */ 975 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 976 /* unimplemented, or NS access: RAZ/WI */ 977 return MEMTX_OK; 978 } else { 979 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 980 } 981 break; 982 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 983 qemu_log_mask(LOG_UNIMP, "Writing APR not implemented\n"); 984 break; 985 default: 986 qemu_log_mask(LOG_GUEST_ERROR, 987 "gic_cpu_write: Bad offset %x\n", (int)offset); 988 return MEMTX_ERROR; 989 } 990 gic_update(s); 991 return MEMTX_OK; 992 } 993 994 /* Wrappers to read/write the GIC CPU interface for the current CPU */ 995 static MemTxResult gic_thiscpu_read(void *opaque, hwaddr addr, uint64_t *data, 996 unsigned size, MemTxAttrs attrs) 997 { 998 GICState *s = (GICState *)opaque; 999 return gic_cpu_read(s, gic_get_current_cpu(s), addr, data, attrs); 1000 } 1001 1002 static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, 1003 uint64_t value, unsigned size, 1004 MemTxAttrs attrs) 1005 { 1006 GICState *s = (GICState *)opaque; 1007 return gic_cpu_write(s, gic_get_current_cpu(s), addr, value, attrs); 1008 } 1009 1010 /* Wrappers to read/write the GIC CPU interface for a specific CPU. 1011 * These just decode the opaque pointer into GICState* + cpu id. 1012 */ 1013 static MemTxResult gic_do_cpu_read(void *opaque, hwaddr addr, uint64_t *data, 1014 unsigned size, MemTxAttrs attrs) 1015 { 1016 GICState **backref = (GICState **)opaque; 1017 GICState *s = *backref; 1018 int id = (backref - s->backref); 1019 return gic_cpu_read(s, id, addr, data, attrs); 1020 } 1021 1022 static MemTxResult gic_do_cpu_write(void *opaque, hwaddr addr, 1023 uint64_t value, unsigned size, 1024 MemTxAttrs attrs) 1025 { 1026 GICState **backref = (GICState **)opaque; 1027 GICState *s = *backref; 1028 int id = (backref - s->backref); 1029 return gic_cpu_write(s, id, addr, value, attrs); 1030 } 1031 1032 static const MemoryRegionOps gic_thiscpu_ops = { 1033 .read_with_attrs = gic_thiscpu_read, 1034 .write_with_attrs = gic_thiscpu_write, 1035 .endianness = DEVICE_NATIVE_ENDIAN, 1036 }; 1037 1038 static const MemoryRegionOps gic_cpu_ops = { 1039 .read_with_attrs = gic_do_cpu_read, 1040 .write_with_attrs = gic_do_cpu_write, 1041 .endianness = DEVICE_NATIVE_ENDIAN, 1042 }; 1043 1044 void gic_init_irqs_and_distributor(GICState *s) 1045 { 1046 SysBusDevice *sbd = SYS_BUS_DEVICE(s); 1047 int i; 1048 1049 i = s->num_irq - GIC_INTERNAL; 1050 /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU. 1051 * GPIO array layout is thus: 1052 * [0..N-1] SPIs 1053 * [N..N+31] PPIs for CPU 0 1054 * [N+32..N+63] PPIs for CPU 1 1055 * ... 1056 */ 1057 if (s->revision != REV_NVIC) { 1058 i += (GIC_INTERNAL * s->num_cpu); 1059 } 1060 qdev_init_gpio_in(DEVICE(s), gic_set_irq, i); 1061 for (i = 0; i < NUM_CPU(s); i++) { 1062 sysbus_init_irq(sbd, &s->parent_irq[i]); 1063 } 1064 for (i = 0; i < NUM_CPU(s); i++) { 1065 sysbus_init_irq(sbd, &s->parent_fiq[i]); 1066 } 1067 memory_region_init_io(&s->iomem, OBJECT(s), &gic_dist_ops, s, 1068 "gic_dist", 0x1000); 1069 } 1070 1071 static void arm_gic_realize(DeviceState *dev, Error **errp) 1072 { 1073 /* Device instance realize function for the GIC sysbus device */ 1074 int i; 1075 GICState *s = ARM_GIC(dev); 1076 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1077 ARMGICClass *agc = ARM_GIC_GET_CLASS(s); 1078 Error *local_err = NULL; 1079 1080 agc->parent_realize(dev, &local_err); 1081 if (local_err) { 1082 error_propagate(errp, local_err); 1083 return; 1084 } 1085 1086 gic_init_irqs_and_distributor(s); 1087 1088 /* Memory regions for the CPU interfaces (NVIC doesn't have these): 1089 * a region for "CPU interface for this core", then a region for 1090 * "CPU interface for core 0", "for core 1", ... 1091 * NB that the memory region size of 0x100 applies for the 11MPCore 1092 * and also cores following the GIC v1 spec (ie A9). 1093 * GIC v2 defines a larger memory region (0x1000) so this will need 1094 * to be extended when we implement A15. 1095 */ 1096 memory_region_init_io(&s->cpuiomem[0], OBJECT(s), &gic_thiscpu_ops, s, 1097 "gic_cpu", 0x100); 1098 for (i = 0; i < NUM_CPU(s); i++) { 1099 s->backref[i] = s; 1100 memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops, 1101 &s->backref[i], "gic_cpu", 0x100); 1102 } 1103 /* Distributor */ 1104 sysbus_init_mmio(sbd, &s->iomem); 1105 /* cpu interfaces (one for "current cpu" plus one per cpu) */ 1106 for (i = 0; i <= NUM_CPU(s); i++) { 1107 sysbus_init_mmio(sbd, &s->cpuiomem[i]); 1108 } 1109 } 1110 1111 static void arm_gic_class_init(ObjectClass *klass, void *data) 1112 { 1113 DeviceClass *dc = DEVICE_CLASS(klass); 1114 ARMGICClass *agc = ARM_GIC_CLASS(klass); 1115 1116 agc->parent_realize = dc->realize; 1117 dc->realize = arm_gic_realize; 1118 } 1119 1120 static const TypeInfo arm_gic_info = { 1121 .name = TYPE_ARM_GIC, 1122 .parent = TYPE_ARM_GIC_COMMON, 1123 .instance_size = sizeof(GICState), 1124 .class_init = arm_gic_class_init, 1125 .class_size = sizeof(ARMGICClass), 1126 }; 1127 1128 static void arm_gic_register_types(void) 1129 { 1130 type_register_static(&arm_gic_info); 1131 } 1132 1133 type_init(arm_gic_register_types) 1134