1 /* 2 * ARM Generic/Distributed Interrupt Controller 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 /* This file contains implementation code for the RealView EB interrupt 11 * controller, MPCore distributed interrupt controller and ARMv7-M 12 * Nested Vectored Interrupt Controller. 13 * It is compiled in two ways: 14 * (1) as a standalone file to produce a sysbus device which is a GIC 15 * that can be used on the realview board and as one of the builtin 16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc) 17 * (2) by being directly #included into armv7m_nvic.c to produce the 18 * armv7m_nvic device. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/sysbus.h" 23 #include "gic_internal.h" 24 #include "qapi/error.h" 25 #include "qom/cpu.h" 26 #include "qemu/log.h" 27 #include "trace.h" 28 #include "sysemu/kvm.h" 29 30 /* #define DEBUG_GIC */ 31 32 #ifdef DEBUG_GIC 33 #define DEBUG_GIC_GATE 1 34 #else 35 #define DEBUG_GIC_GATE 0 36 #endif 37 38 #define DPRINTF(fmt, ...) do { \ 39 if (DEBUG_GIC_GATE) { \ 40 fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \ 41 } \ 42 } while (0) 43 44 static const uint8_t gic_id_11mpcore[] = { 45 0x00, 0x00, 0x00, 0x00, 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 46 }; 47 48 static const uint8_t gic_id_gicv1[] = { 49 0x04, 0x00, 0x00, 0x00, 0x90, 0xb3, 0x1b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 50 }; 51 52 static const uint8_t gic_id_gicv2[] = { 53 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 54 }; 55 56 static inline int gic_get_current_cpu(GICState *s) 57 { 58 if (s->num_cpu > 1) { 59 return current_cpu->cpu_index; 60 } 61 return 0; 62 } 63 64 /* Return true if this GIC config has interrupt groups, which is 65 * true if we're a GICv2, or a GICv1 with the security extensions. 66 */ 67 static inline bool gic_has_groups(GICState *s) 68 { 69 return s->revision == 2 || s->security_extn; 70 } 71 72 /* TODO: Many places that call this routine could be optimized. */ 73 /* Update interrupt status after enabled or pending bits have been changed. */ 74 void gic_update(GICState *s) 75 { 76 int best_irq; 77 int best_prio; 78 int irq; 79 int irq_level, fiq_level; 80 int cpu; 81 int cm; 82 83 for (cpu = 0; cpu < s->num_cpu; cpu++) { 84 cm = 1 << cpu; 85 s->current_pending[cpu] = 1023; 86 if (!(s->ctlr & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1)) 87 || !(s->cpu_ctlr[cpu] & (GICC_CTLR_EN_GRP0 | GICC_CTLR_EN_GRP1))) { 88 qemu_irq_lower(s->parent_irq[cpu]); 89 qemu_irq_lower(s->parent_fiq[cpu]); 90 continue; 91 } 92 best_prio = 0x100; 93 best_irq = 1023; 94 for (irq = 0; irq < s->num_irq; irq++) { 95 if (GIC_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm) && 96 (!GIC_TEST_ACTIVE(irq, cm)) && 97 (irq < GIC_INTERNAL || GIC_TARGET(irq) & cm)) { 98 if (GIC_GET_PRIORITY(irq, cpu) < best_prio) { 99 best_prio = GIC_GET_PRIORITY(irq, cpu); 100 best_irq = irq; 101 } 102 } 103 } 104 105 if (best_irq != 1023) { 106 trace_gic_update_bestirq(cpu, best_irq, best_prio, 107 s->priority_mask[cpu], s->running_priority[cpu]); 108 } 109 110 irq_level = fiq_level = 0; 111 112 if (best_prio < s->priority_mask[cpu]) { 113 s->current_pending[cpu] = best_irq; 114 if (best_prio < s->running_priority[cpu]) { 115 int group = GIC_TEST_GROUP(best_irq, cm); 116 117 if (extract32(s->ctlr, group, 1) && 118 extract32(s->cpu_ctlr[cpu], group, 1)) { 119 if (group == 0 && s->cpu_ctlr[cpu] & GICC_CTLR_FIQ_EN) { 120 DPRINTF("Raised pending FIQ %d (cpu %d)\n", 121 best_irq, cpu); 122 fiq_level = 1; 123 trace_gic_update_set_irq(cpu, "fiq", fiq_level); 124 } else { 125 DPRINTF("Raised pending IRQ %d (cpu %d)\n", 126 best_irq, cpu); 127 irq_level = 1; 128 trace_gic_update_set_irq(cpu, "irq", irq_level); 129 } 130 } 131 } 132 } 133 134 qemu_set_irq(s->parent_irq[cpu], irq_level); 135 qemu_set_irq(s->parent_fiq[cpu], fiq_level); 136 } 137 } 138 139 void gic_set_pending_private(GICState *s, int cpu, int irq) 140 { 141 int cm = 1 << cpu; 142 143 if (gic_test_pending(s, irq, cm)) { 144 return; 145 } 146 147 DPRINTF("Set %d pending cpu %d\n", irq, cpu); 148 GIC_SET_PENDING(irq, cm); 149 gic_update(s); 150 } 151 152 static void gic_set_irq_11mpcore(GICState *s, int irq, int level, 153 int cm, int target) 154 { 155 if (level) { 156 GIC_SET_LEVEL(irq, cm); 157 if (GIC_TEST_EDGE_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) { 158 DPRINTF("Set %d pending mask %x\n", irq, target); 159 GIC_SET_PENDING(irq, target); 160 } 161 } else { 162 GIC_CLEAR_LEVEL(irq, cm); 163 } 164 } 165 166 static void gic_set_irq_generic(GICState *s, int irq, int level, 167 int cm, int target) 168 { 169 if (level) { 170 GIC_SET_LEVEL(irq, cm); 171 DPRINTF("Set %d pending mask %x\n", irq, target); 172 if (GIC_TEST_EDGE_TRIGGER(irq)) { 173 GIC_SET_PENDING(irq, target); 174 } 175 } else { 176 GIC_CLEAR_LEVEL(irq, cm); 177 } 178 } 179 180 /* Process a change in an external IRQ input. */ 181 static void gic_set_irq(void *opaque, int irq, int level) 182 { 183 /* Meaning of the 'irq' parameter: 184 * [0..N-1] : external interrupts 185 * [N..N+31] : PPI (internal) interrupts for CPU 0 186 * [N+32..N+63] : PPI (internal interrupts for CPU 1 187 * ... 188 */ 189 GICState *s = (GICState *)opaque; 190 int cm, target; 191 if (irq < (s->num_irq - GIC_INTERNAL)) { 192 /* The first external input line is internal interrupt 32. */ 193 cm = ALL_CPU_MASK; 194 irq += GIC_INTERNAL; 195 target = GIC_TARGET(irq); 196 } else { 197 int cpu; 198 irq -= (s->num_irq - GIC_INTERNAL); 199 cpu = irq / GIC_INTERNAL; 200 irq %= GIC_INTERNAL; 201 cm = 1 << cpu; 202 target = cm; 203 } 204 205 assert(irq >= GIC_NR_SGIS); 206 207 if (level == GIC_TEST_LEVEL(irq, cm)) { 208 return; 209 } 210 211 if (s->revision == REV_11MPCORE) { 212 gic_set_irq_11mpcore(s, irq, level, cm, target); 213 } else { 214 gic_set_irq_generic(s, irq, level, cm, target); 215 } 216 trace_gic_set_irq(irq, level, cm, target); 217 218 gic_update(s); 219 } 220 221 static uint16_t gic_get_current_pending_irq(GICState *s, int cpu, 222 MemTxAttrs attrs) 223 { 224 uint16_t pending_irq = s->current_pending[cpu]; 225 226 if (pending_irq < GIC_MAXIRQ && gic_has_groups(s)) { 227 int group = GIC_TEST_GROUP(pending_irq, (1 << cpu)); 228 /* On a GIC without the security extensions, reading this register 229 * behaves in the same way as a secure access to a GIC with them. 230 */ 231 bool secure = !s->security_extn || attrs.secure; 232 233 if (group == 0 && !secure) { 234 /* Group0 interrupts hidden from Non-secure access */ 235 return 1023; 236 } 237 if (group == 1 && secure && !(s->cpu_ctlr[cpu] & GICC_CTLR_ACK_CTL)) { 238 /* Group1 interrupts only seen by Secure access if 239 * AckCtl bit set. 240 */ 241 return 1022; 242 } 243 } 244 return pending_irq; 245 } 246 247 static int gic_get_group_priority(GICState *s, int cpu, int irq) 248 { 249 /* Return the group priority of the specified interrupt 250 * (which is the top bits of its priority, with the number 251 * of bits masked determined by the applicable binary point register). 252 */ 253 int bpr; 254 uint32_t mask; 255 256 if (gic_has_groups(s) && 257 !(s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) && 258 GIC_TEST_GROUP(irq, (1 << cpu))) { 259 bpr = s->abpr[cpu] - 1; 260 assert(bpr >= 0); 261 } else { 262 bpr = s->bpr[cpu]; 263 } 264 265 /* a BPR of 0 means the group priority bits are [7:1]; 266 * a BPR of 1 means they are [7:2], and so on down to 267 * a BPR of 7 meaning no group priority bits at all. 268 */ 269 mask = ~0U << ((bpr & 7) + 1); 270 271 return GIC_GET_PRIORITY(irq, cpu) & mask; 272 } 273 274 static void gic_activate_irq(GICState *s, int cpu, int irq) 275 { 276 /* Set the appropriate Active Priority Register bit for this IRQ, 277 * and update the running priority. 278 */ 279 int prio = gic_get_group_priority(s, cpu, irq); 280 int preemption_level = prio >> (GIC_MIN_BPR + 1); 281 int regno = preemption_level / 32; 282 int bitno = preemption_level % 32; 283 284 if (gic_has_groups(s) && GIC_TEST_GROUP(irq, (1 << cpu))) { 285 s->nsapr[regno][cpu] |= (1 << bitno); 286 } else { 287 s->apr[regno][cpu] |= (1 << bitno); 288 } 289 290 s->running_priority[cpu] = prio; 291 GIC_SET_ACTIVE(irq, 1 << cpu); 292 } 293 294 static int gic_get_prio_from_apr_bits(GICState *s, int cpu) 295 { 296 /* Recalculate the current running priority for this CPU based 297 * on the set bits in the Active Priority Registers. 298 */ 299 int i; 300 for (i = 0; i < GIC_NR_APRS; i++) { 301 uint32_t apr = s->apr[i][cpu] | s->nsapr[i][cpu]; 302 if (!apr) { 303 continue; 304 } 305 return (i * 32 + ctz32(apr)) << (GIC_MIN_BPR + 1); 306 } 307 return 0x100; 308 } 309 310 static void gic_drop_prio(GICState *s, int cpu, int group) 311 { 312 /* Drop the priority of the currently active interrupt in the 313 * specified group. 314 * 315 * Note that we can guarantee (because of the requirement to nest 316 * GICC_IAR reads [which activate an interrupt and raise priority] 317 * with GICC_EOIR writes [which drop the priority for the interrupt]) 318 * that the interrupt we're being called for is the highest priority 319 * active interrupt, meaning that it has the lowest set bit in the 320 * APR registers. 321 * 322 * If the guest does not honour the ordering constraints then the 323 * behaviour of the GIC is UNPREDICTABLE, which for us means that 324 * the values of the APR registers might become incorrect and the 325 * running priority will be wrong, so interrupts that should preempt 326 * might not do so, and interrupts that should not preempt might do so. 327 */ 328 int i; 329 330 for (i = 0; i < GIC_NR_APRS; i++) { 331 uint32_t *papr = group ? &s->nsapr[i][cpu] : &s->apr[i][cpu]; 332 if (!*papr) { 333 continue; 334 } 335 /* Clear lowest set bit */ 336 *papr &= *papr - 1; 337 break; 338 } 339 340 s->running_priority[cpu] = gic_get_prio_from_apr_bits(s, cpu); 341 } 342 343 uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs) 344 { 345 int ret, irq, src; 346 int cm = 1 << cpu; 347 348 /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately 349 * for the case where this GIC supports grouping and the pending interrupt 350 * is in the wrong group. 351 */ 352 irq = gic_get_current_pending_irq(s, cpu, attrs); 353 trace_gic_acknowledge_irq(cpu, irq); 354 355 if (irq >= GIC_MAXIRQ) { 356 DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq); 357 return irq; 358 } 359 360 if (GIC_GET_PRIORITY(irq, cpu) >= s->running_priority[cpu]) { 361 DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq); 362 return 1023; 363 } 364 365 if (s->revision == REV_11MPCORE) { 366 /* Clear pending flags for both level and edge triggered interrupts. 367 * Level triggered IRQs will be reasserted once they become inactive. 368 */ 369 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 370 ret = irq; 371 } else { 372 if (irq < GIC_NR_SGIS) { 373 /* Lookup the source CPU for the SGI and clear this in the 374 * sgi_pending map. Return the src and clear the overall pending 375 * state on this CPU if the SGI is not pending from any CPUs. 376 */ 377 assert(s->sgi_pending[irq][cpu] != 0); 378 src = ctz32(s->sgi_pending[irq][cpu]); 379 s->sgi_pending[irq][cpu] &= ~(1 << src); 380 if (s->sgi_pending[irq][cpu] == 0) { 381 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 382 } 383 ret = irq | ((src & 0x7) << 10); 384 } else { 385 /* Clear pending state for both level and edge triggered 386 * interrupts. (level triggered interrupts with an active line 387 * remain pending, see gic_test_pending) 388 */ 389 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 390 ret = irq; 391 } 392 } 393 394 gic_activate_irq(s, cpu, irq); 395 gic_update(s); 396 DPRINTF("ACK %d\n", irq); 397 return ret; 398 } 399 400 void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val, 401 MemTxAttrs attrs) 402 { 403 if (s->security_extn && !attrs.secure) { 404 if (!GIC_TEST_GROUP(irq, (1 << cpu))) { 405 return; /* Ignore Non-secure access of Group0 IRQ */ 406 } 407 val = 0x80 | (val >> 1); /* Non-secure view */ 408 } 409 410 if (irq < GIC_INTERNAL) { 411 s->priority1[irq][cpu] = val; 412 } else { 413 s->priority2[(irq) - GIC_INTERNAL] = val; 414 } 415 } 416 417 static uint32_t gic_get_priority(GICState *s, int cpu, int irq, 418 MemTxAttrs attrs) 419 { 420 uint32_t prio = GIC_GET_PRIORITY(irq, cpu); 421 422 if (s->security_extn && !attrs.secure) { 423 if (!GIC_TEST_GROUP(irq, (1 << cpu))) { 424 return 0; /* Non-secure access cannot read priority of Group0 IRQ */ 425 } 426 prio = (prio << 1) & 0xff; /* Non-secure view */ 427 } 428 return prio; 429 } 430 431 static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, 432 MemTxAttrs attrs) 433 { 434 if (s->security_extn && !attrs.secure) { 435 if (s->priority_mask[cpu] & 0x80) { 436 /* Priority Mask in upper half */ 437 pmask = 0x80 | (pmask >> 1); 438 } else { 439 /* Non-secure write ignored if priority mask is in lower half */ 440 return; 441 } 442 } 443 s->priority_mask[cpu] = pmask; 444 } 445 446 static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs) 447 { 448 uint32_t pmask = s->priority_mask[cpu]; 449 450 if (s->security_extn && !attrs.secure) { 451 if (pmask & 0x80) { 452 /* Priority Mask in upper half, return Non-secure view */ 453 pmask = (pmask << 1) & 0xff; 454 } else { 455 /* Priority Mask in lower half, RAZ */ 456 pmask = 0; 457 } 458 } 459 return pmask; 460 } 461 462 static uint32_t gic_get_cpu_control(GICState *s, int cpu, MemTxAttrs attrs) 463 { 464 uint32_t ret = s->cpu_ctlr[cpu]; 465 466 if (s->security_extn && !attrs.secure) { 467 /* Construct the NS banked view of GICC_CTLR from the correct 468 * bits of the S banked view. We don't need to move the bypass 469 * control bits because we don't implement that (IMPDEF) part 470 * of the GIC architecture. 471 */ 472 ret = (ret & (GICC_CTLR_EN_GRP1 | GICC_CTLR_EOIMODE_NS)) >> 1; 473 } 474 return ret; 475 } 476 477 static void gic_set_cpu_control(GICState *s, int cpu, uint32_t value, 478 MemTxAttrs attrs) 479 { 480 uint32_t mask; 481 482 if (s->security_extn && !attrs.secure) { 483 /* The NS view can only write certain bits in the register; 484 * the rest are unchanged 485 */ 486 mask = GICC_CTLR_EN_GRP1; 487 if (s->revision == 2) { 488 mask |= GICC_CTLR_EOIMODE_NS; 489 } 490 s->cpu_ctlr[cpu] &= ~mask; 491 s->cpu_ctlr[cpu] |= (value << 1) & mask; 492 } else { 493 if (s->revision == 2) { 494 mask = s->security_extn ? GICC_CTLR_V2_S_MASK : GICC_CTLR_V2_MASK; 495 } else { 496 mask = s->security_extn ? GICC_CTLR_V1_S_MASK : GICC_CTLR_V1_MASK; 497 } 498 s->cpu_ctlr[cpu] = value & mask; 499 } 500 DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, " 501 "Group1 Interrupts %sabled\n", cpu, 502 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP0) ? "En" : "Dis", 503 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP1) ? "En" : "Dis"); 504 } 505 506 static uint8_t gic_get_running_priority(GICState *s, int cpu, MemTxAttrs attrs) 507 { 508 if ((s->revision != REV_11MPCORE) && (s->running_priority[cpu] > 0xff)) { 509 /* Idle priority */ 510 return 0xff; 511 } 512 513 if (s->security_extn && !attrs.secure) { 514 if (s->running_priority[cpu] & 0x80) { 515 /* Running priority in upper half of range: return the Non-secure 516 * view of the priority. 517 */ 518 return s->running_priority[cpu] << 1; 519 } else { 520 /* Running priority in lower half of range: RAZ */ 521 return 0; 522 } 523 } else { 524 return s->running_priority[cpu]; 525 } 526 } 527 528 /* Return true if we should split priority drop and interrupt deactivation, 529 * ie whether the relevant EOIMode bit is set. 530 */ 531 static bool gic_eoi_split(GICState *s, int cpu, MemTxAttrs attrs) 532 { 533 if (s->revision != 2) { 534 /* Before GICv2 prio-drop and deactivate are not separable */ 535 return false; 536 } 537 if (s->security_extn && !attrs.secure) { 538 return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE_NS; 539 } 540 return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE; 541 } 542 543 static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) 544 { 545 int cm = 1 << cpu; 546 int group; 547 548 if (irq >= s->num_irq) { 549 /* 550 * This handles two cases: 551 * 1. If software writes the ID of a spurious interrupt [ie 1023] 552 * to the GICC_DIR, the GIC ignores that write. 553 * 2. If software writes the number of a non-existent interrupt 554 * this must be a subcase of "value written is not an active interrupt" 555 * and so this is UNPREDICTABLE. We choose to ignore it. 556 */ 557 return; 558 } 559 560 group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm); 561 562 if (!gic_eoi_split(s, cpu, attrs)) { 563 /* This is UNPREDICTABLE; we choose to ignore it */ 564 qemu_log_mask(LOG_GUEST_ERROR, 565 "gic_deactivate_irq: GICC_DIR write when EOIMode clear"); 566 return; 567 } 568 569 if (s->security_extn && !attrs.secure && !group) { 570 DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq); 571 return; 572 } 573 574 GIC_CLEAR_ACTIVE(irq, cm); 575 } 576 577 void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) 578 { 579 int cm = 1 << cpu; 580 int group; 581 582 DPRINTF("EOI %d\n", irq); 583 if (irq >= s->num_irq) { 584 /* This handles two cases: 585 * 1. If software writes the ID of a spurious interrupt [ie 1023] 586 * to the GICC_EOIR, the GIC ignores that write. 587 * 2. If software writes the number of a non-existent interrupt 588 * this must be a subcase of "value written does not match the last 589 * valid interrupt value read from the Interrupt Acknowledge 590 * register" and so this is UNPREDICTABLE. We choose to ignore it. 591 */ 592 return; 593 } 594 if (s->running_priority[cpu] == 0x100) { 595 return; /* No active IRQ. */ 596 } 597 598 if (s->revision == REV_11MPCORE) { 599 /* Mark level triggered interrupts as pending if they are still 600 raised. */ 601 if (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm) 602 && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) { 603 DPRINTF("Set %d pending mask %x\n", irq, cm); 604 GIC_SET_PENDING(irq, cm); 605 } 606 } 607 608 group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm); 609 610 if (s->security_extn && !attrs.secure && !group) { 611 DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq); 612 return; 613 } 614 615 /* Secure EOI with GICC_CTLR.AckCtl == 0 when the IRQ is a Group 1 616 * interrupt is UNPREDICTABLE. We choose to handle it as if AckCtl == 1, 617 * i.e. go ahead and complete the irq anyway. 618 */ 619 620 gic_drop_prio(s, cpu, group); 621 622 /* In GICv2 the guest can choose to split priority-drop and deactivate */ 623 if (!gic_eoi_split(s, cpu, attrs)) { 624 GIC_CLEAR_ACTIVE(irq, cm); 625 } 626 gic_update(s); 627 } 628 629 static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) 630 { 631 GICState *s = (GICState *)opaque; 632 uint32_t res; 633 int irq; 634 int i; 635 int cpu; 636 int cm; 637 int mask; 638 639 cpu = gic_get_current_cpu(s); 640 cm = 1 << cpu; 641 if (offset < 0x100) { 642 if (offset == 0) { /* GICD_CTLR */ 643 if (s->security_extn && !attrs.secure) { 644 /* The NS bank of this register is just an alias of the 645 * EnableGrp1 bit in the S bank version. 646 */ 647 return extract32(s->ctlr, 1, 1); 648 } else { 649 return s->ctlr; 650 } 651 } 652 if (offset == 4) 653 /* Interrupt Controller Type Register */ 654 return ((s->num_irq / 32) - 1) 655 | ((s->num_cpu - 1) << 5) 656 | (s->security_extn << 10); 657 if (offset < 0x08) 658 return 0; 659 if (offset >= 0x80) { 660 /* Interrupt Group Registers: these RAZ/WI if this is an NS 661 * access to a GIC with the security extensions, or if the GIC 662 * doesn't have groups at all. 663 */ 664 res = 0; 665 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 666 /* Every byte offset holds 8 group status bits */ 667 irq = (offset - 0x080) * 8 + GIC_BASE_IRQ; 668 if (irq >= s->num_irq) { 669 goto bad_reg; 670 } 671 for (i = 0; i < 8; i++) { 672 if (GIC_TEST_GROUP(irq + i, cm)) { 673 res |= (1 << i); 674 } 675 } 676 } 677 return res; 678 } 679 goto bad_reg; 680 } else if (offset < 0x200) { 681 /* Interrupt Set/Clear Enable. */ 682 if (offset < 0x180) 683 irq = (offset - 0x100) * 8; 684 else 685 irq = (offset - 0x180) * 8; 686 irq += GIC_BASE_IRQ; 687 if (irq >= s->num_irq) 688 goto bad_reg; 689 res = 0; 690 for (i = 0; i < 8; i++) { 691 if (s->security_extn && !attrs.secure && 692 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 693 continue; /* Ignore Non-secure access of Group0 IRQ */ 694 } 695 696 if (GIC_TEST_ENABLED(irq + i, cm)) { 697 res |= (1 << i); 698 } 699 } 700 } else if (offset < 0x300) { 701 /* Interrupt Set/Clear Pending. */ 702 if (offset < 0x280) 703 irq = (offset - 0x200) * 8; 704 else 705 irq = (offset - 0x280) * 8; 706 irq += GIC_BASE_IRQ; 707 if (irq >= s->num_irq) 708 goto bad_reg; 709 res = 0; 710 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 711 for (i = 0; i < 8; i++) { 712 if (s->security_extn && !attrs.secure && 713 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 714 continue; /* Ignore Non-secure access of Group0 IRQ */ 715 } 716 717 if (gic_test_pending(s, irq + i, mask)) { 718 res |= (1 << i); 719 } 720 } 721 } else if (offset < 0x400) { 722 /* Interrupt Active. */ 723 irq = (offset - 0x300) * 8 + GIC_BASE_IRQ; 724 if (irq >= s->num_irq) 725 goto bad_reg; 726 res = 0; 727 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 728 for (i = 0; i < 8; i++) { 729 if (s->security_extn && !attrs.secure && 730 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 731 continue; /* Ignore Non-secure access of Group0 IRQ */ 732 } 733 734 if (GIC_TEST_ACTIVE(irq + i, mask)) { 735 res |= (1 << i); 736 } 737 } 738 } else if (offset < 0x800) { 739 /* Interrupt Priority. */ 740 irq = (offset - 0x400) + GIC_BASE_IRQ; 741 if (irq >= s->num_irq) 742 goto bad_reg; 743 res = gic_get_priority(s, cpu, irq, attrs); 744 } else if (offset < 0xc00) { 745 /* Interrupt CPU Target. */ 746 if (s->num_cpu == 1 && s->revision != REV_11MPCORE) { 747 /* For uniprocessor GICs these RAZ/WI */ 748 res = 0; 749 } else { 750 irq = (offset - 0x800) + GIC_BASE_IRQ; 751 if (irq >= s->num_irq) { 752 goto bad_reg; 753 } 754 if (irq >= 29 && irq <= 31) { 755 res = cm; 756 } else { 757 res = GIC_TARGET(irq); 758 } 759 } 760 } else if (offset < 0xf00) { 761 /* Interrupt Configuration. */ 762 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 763 if (irq >= s->num_irq) 764 goto bad_reg; 765 res = 0; 766 for (i = 0; i < 4; i++) { 767 if (s->security_extn && !attrs.secure && 768 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 769 continue; /* Ignore Non-secure access of Group0 IRQ */ 770 } 771 772 if (GIC_TEST_MODEL(irq + i)) 773 res |= (1 << (i * 2)); 774 if (GIC_TEST_EDGE_TRIGGER(irq + i)) 775 res |= (2 << (i * 2)); 776 } 777 } else if (offset < 0xf10) { 778 goto bad_reg; 779 } else if (offset < 0xf30) { 780 if (s->revision == REV_11MPCORE) { 781 goto bad_reg; 782 } 783 784 if (offset < 0xf20) { 785 /* GICD_CPENDSGIRn */ 786 irq = (offset - 0xf10); 787 } else { 788 irq = (offset - 0xf20); 789 /* GICD_SPENDSGIRn */ 790 } 791 792 if (s->security_extn && !attrs.secure && 793 !GIC_TEST_GROUP(irq, 1 << cpu)) { 794 res = 0; /* Ignore Non-secure access of Group0 IRQ */ 795 } else { 796 res = s->sgi_pending[irq][cpu]; 797 } 798 } else if (offset < 0xfd0) { 799 goto bad_reg; 800 } else if (offset < 0x1000) { 801 if (offset & 3) { 802 res = 0; 803 } else { 804 switch (s->revision) { 805 case REV_11MPCORE: 806 res = gic_id_11mpcore[(offset - 0xfd0) >> 2]; 807 break; 808 case 1: 809 res = gic_id_gicv1[(offset - 0xfd0) >> 2]; 810 break; 811 case 2: 812 res = gic_id_gicv2[(offset - 0xfd0) >> 2]; 813 break; 814 default: 815 res = 0; 816 } 817 } 818 } else { 819 g_assert_not_reached(); 820 } 821 return res; 822 bad_reg: 823 qemu_log_mask(LOG_GUEST_ERROR, 824 "gic_dist_readb: Bad offset %x\n", (int)offset); 825 return 0; 826 } 827 828 static MemTxResult gic_dist_read(void *opaque, hwaddr offset, uint64_t *data, 829 unsigned size, MemTxAttrs attrs) 830 { 831 switch (size) { 832 case 1: 833 *data = gic_dist_readb(opaque, offset, attrs); 834 return MEMTX_OK; 835 case 2: 836 *data = gic_dist_readb(opaque, offset, attrs); 837 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 838 return MEMTX_OK; 839 case 4: 840 *data = gic_dist_readb(opaque, offset, attrs); 841 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 842 *data |= gic_dist_readb(opaque, offset + 2, attrs) << 16; 843 *data |= gic_dist_readb(opaque, offset + 3, attrs) << 24; 844 return MEMTX_OK; 845 default: 846 return MEMTX_ERROR; 847 } 848 } 849 850 static void gic_dist_writeb(void *opaque, hwaddr offset, 851 uint32_t value, MemTxAttrs attrs) 852 { 853 GICState *s = (GICState *)opaque; 854 int irq; 855 int i; 856 int cpu; 857 858 cpu = gic_get_current_cpu(s); 859 if (offset < 0x100) { 860 if (offset == 0) { 861 if (s->security_extn && !attrs.secure) { 862 /* NS version is just an alias of the S version's bit 1 */ 863 s->ctlr = deposit32(s->ctlr, 1, 1, value); 864 } else if (gic_has_groups(s)) { 865 s->ctlr = value & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1); 866 } else { 867 s->ctlr = value & GICD_CTLR_EN_GRP0; 868 } 869 DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n", 870 s->ctlr & GICD_CTLR_EN_GRP0 ? "En" : "Dis", 871 s->ctlr & GICD_CTLR_EN_GRP1 ? "En" : "Dis"); 872 } else if (offset < 4) { 873 /* ignored. */ 874 } else if (offset >= 0x80) { 875 /* Interrupt Group Registers: RAZ/WI for NS access to secure 876 * GIC, or for GICs without groups. 877 */ 878 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 879 /* Every byte offset holds 8 group status bits */ 880 irq = (offset - 0x80) * 8 + GIC_BASE_IRQ; 881 if (irq >= s->num_irq) { 882 goto bad_reg; 883 } 884 for (i = 0; i < 8; i++) { 885 /* Group bits are banked for private interrupts */ 886 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 887 if (value & (1 << i)) { 888 /* Group1 (Non-secure) */ 889 GIC_SET_GROUP(irq + i, cm); 890 } else { 891 /* Group0 (Secure) */ 892 GIC_CLEAR_GROUP(irq + i, cm); 893 } 894 } 895 } 896 } else { 897 goto bad_reg; 898 } 899 } else if (offset < 0x180) { 900 /* Interrupt Set Enable. */ 901 irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; 902 if (irq >= s->num_irq) 903 goto bad_reg; 904 if (irq < GIC_NR_SGIS) { 905 value = 0xff; 906 } 907 908 for (i = 0; i < 8; i++) { 909 if (value & (1 << i)) { 910 int mask = 911 (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq + i); 912 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 913 914 if (s->security_extn && !attrs.secure && 915 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 916 continue; /* Ignore Non-secure access of Group0 IRQ */ 917 } 918 919 if (!GIC_TEST_ENABLED(irq + i, cm)) { 920 DPRINTF("Enabled IRQ %d\n", irq + i); 921 trace_gic_enable_irq(irq + i); 922 } 923 GIC_SET_ENABLED(irq + i, cm); 924 /* If a raised level triggered IRQ enabled then mark 925 is as pending. */ 926 if (GIC_TEST_LEVEL(irq + i, mask) 927 && !GIC_TEST_EDGE_TRIGGER(irq + i)) { 928 DPRINTF("Set %d pending mask %x\n", irq + i, mask); 929 GIC_SET_PENDING(irq + i, mask); 930 } 931 } 932 } 933 } else if (offset < 0x200) { 934 /* Interrupt Clear Enable. */ 935 irq = (offset - 0x180) * 8 + GIC_BASE_IRQ; 936 if (irq >= s->num_irq) 937 goto bad_reg; 938 if (irq < GIC_NR_SGIS) { 939 value = 0; 940 } 941 942 for (i = 0; i < 8; i++) { 943 if (value & (1 << i)) { 944 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 945 946 if (s->security_extn && !attrs.secure && 947 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 948 continue; /* Ignore Non-secure access of Group0 IRQ */ 949 } 950 951 if (GIC_TEST_ENABLED(irq + i, cm)) { 952 DPRINTF("Disabled IRQ %d\n", irq + i); 953 trace_gic_disable_irq(irq + i); 954 } 955 GIC_CLEAR_ENABLED(irq + i, cm); 956 } 957 } 958 } else if (offset < 0x280) { 959 /* Interrupt Set Pending. */ 960 irq = (offset - 0x200) * 8 + GIC_BASE_IRQ; 961 if (irq >= s->num_irq) 962 goto bad_reg; 963 if (irq < GIC_NR_SGIS) { 964 value = 0; 965 } 966 967 for (i = 0; i < 8; i++) { 968 if (value & (1 << i)) { 969 if (s->security_extn && !attrs.secure && 970 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 971 continue; /* Ignore Non-secure access of Group0 IRQ */ 972 } 973 974 GIC_SET_PENDING(irq + i, GIC_TARGET(irq + i)); 975 } 976 } 977 } else if (offset < 0x300) { 978 /* Interrupt Clear Pending. */ 979 irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; 980 if (irq >= s->num_irq) 981 goto bad_reg; 982 if (irq < GIC_NR_SGIS) { 983 value = 0; 984 } 985 986 for (i = 0; i < 8; i++) { 987 if (s->security_extn && !attrs.secure && 988 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 989 continue; /* Ignore Non-secure access of Group0 IRQ */ 990 } 991 992 /* ??? This currently clears the pending bit for all CPUs, even 993 for per-CPU interrupts. It's unclear whether this is the 994 corect behavior. */ 995 if (value & (1 << i)) { 996 GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK); 997 } 998 } 999 } else if (offset < 0x400) { 1000 /* Interrupt Active. */ 1001 goto bad_reg; 1002 } else if (offset < 0x800) { 1003 /* Interrupt Priority. */ 1004 irq = (offset - 0x400) + GIC_BASE_IRQ; 1005 if (irq >= s->num_irq) 1006 goto bad_reg; 1007 gic_set_priority(s, cpu, irq, value, attrs); 1008 } else if (offset < 0xc00) { 1009 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the 1010 * annoying exception of the 11MPCore's GIC. 1011 */ 1012 if (s->num_cpu != 1 || s->revision == REV_11MPCORE) { 1013 irq = (offset - 0x800) + GIC_BASE_IRQ; 1014 if (irq >= s->num_irq) { 1015 goto bad_reg; 1016 } 1017 if (irq < 29) { 1018 value = 0; 1019 } else if (irq < GIC_INTERNAL) { 1020 value = ALL_CPU_MASK; 1021 } 1022 s->irq_target[irq] = value & ALL_CPU_MASK; 1023 } 1024 } else if (offset < 0xf00) { 1025 /* Interrupt Configuration. */ 1026 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 1027 if (irq >= s->num_irq) 1028 goto bad_reg; 1029 if (irq < GIC_NR_SGIS) 1030 value |= 0xaa; 1031 for (i = 0; i < 4; i++) { 1032 if (s->security_extn && !attrs.secure && 1033 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 1034 continue; /* Ignore Non-secure access of Group0 IRQ */ 1035 } 1036 1037 if (s->revision == REV_11MPCORE) { 1038 if (value & (1 << (i * 2))) { 1039 GIC_SET_MODEL(irq + i); 1040 } else { 1041 GIC_CLEAR_MODEL(irq + i); 1042 } 1043 } 1044 if (value & (2 << (i * 2))) { 1045 GIC_SET_EDGE_TRIGGER(irq + i); 1046 } else { 1047 GIC_CLEAR_EDGE_TRIGGER(irq + i); 1048 } 1049 } 1050 } else if (offset < 0xf10) { 1051 /* 0xf00 is only handled for 32-bit writes. */ 1052 goto bad_reg; 1053 } else if (offset < 0xf20) { 1054 /* GICD_CPENDSGIRn */ 1055 if (s->revision == REV_11MPCORE) { 1056 goto bad_reg; 1057 } 1058 irq = (offset - 0xf10); 1059 1060 if (!s->security_extn || attrs.secure || 1061 GIC_TEST_GROUP(irq, 1 << cpu)) { 1062 s->sgi_pending[irq][cpu] &= ~value; 1063 if (s->sgi_pending[irq][cpu] == 0) { 1064 GIC_CLEAR_PENDING(irq, 1 << cpu); 1065 } 1066 } 1067 } else if (offset < 0xf30) { 1068 /* GICD_SPENDSGIRn */ 1069 if (s->revision == REV_11MPCORE) { 1070 goto bad_reg; 1071 } 1072 irq = (offset - 0xf20); 1073 1074 if (!s->security_extn || attrs.secure || 1075 GIC_TEST_GROUP(irq, 1 << cpu)) { 1076 GIC_SET_PENDING(irq, 1 << cpu); 1077 s->sgi_pending[irq][cpu] |= value; 1078 } 1079 } else { 1080 goto bad_reg; 1081 } 1082 gic_update(s); 1083 return; 1084 bad_reg: 1085 qemu_log_mask(LOG_GUEST_ERROR, 1086 "gic_dist_writeb: Bad offset %x\n", (int)offset); 1087 } 1088 1089 static void gic_dist_writew(void *opaque, hwaddr offset, 1090 uint32_t value, MemTxAttrs attrs) 1091 { 1092 gic_dist_writeb(opaque, offset, value & 0xff, attrs); 1093 gic_dist_writeb(opaque, offset + 1, value >> 8, attrs); 1094 } 1095 1096 static void gic_dist_writel(void *opaque, hwaddr offset, 1097 uint32_t value, MemTxAttrs attrs) 1098 { 1099 GICState *s = (GICState *)opaque; 1100 if (offset == 0xf00) { 1101 int cpu; 1102 int irq; 1103 int mask; 1104 int target_cpu; 1105 1106 cpu = gic_get_current_cpu(s); 1107 irq = value & 0x3ff; 1108 switch ((value >> 24) & 3) { 1109 case 0: 1110 mask = (value >> 16) & ALL_CPU_MASK; 1111 break; 1112 case 1: 1113 mask = ALL_CPU_MASK ^ (1 << cpu); 1114 break; 1115 case 2: 1116 mask = 1 << cpu; 1117 break; 1118 default: 1119 DPRINTF("Bad Soft Int target filter\n"); 1120 mask = ALL_CPU_MASK; 1121 break; 1122 } 1123 GIC_SET_PENDING(irq, mask); 1124 target_cpu = ctz32(mask); 1125 while (target_cpu < GIC_NCPU) { 1126 s->sgi_pending[irq][target_cpu] |= (1 << cpu); 1127 mask &= ~(1 << target_cpu); 1128 target_cpu = ctz32(mask); 1129 } 1130 gic_update(s); 1131 return; 1132 } 1133 gic_dist_writew(opaque, offset, value & 0xffff, attrs); 1134 gic_dist_writew(opaque, offset + 2, value >> 16, attrs); 1135 } 1136 1137 static MemTxResult gic_dist_write(void *opaque, hwaddr offset, uint64_t data, 1138 unsigned size, MemTxAttrs attrs) 1139 { 1140 switch (size) { 1141 case 1: 1142 gic_dist_writeb(opaque, offset, data, attrs); 1143 return MEMTX_OK; 1144 case 2: 1145 gic_dist_writew(opaque, offset, data, attrs); 1146 return MEMTX_OK; 1147 case 4: 1148 gic_dist_writel(opaque, offset, data, attrs); 1149 return MEMTX_OK; 1150 default: 1151 return MEMTX_ERROR; 1152 } 1153 } 1154 1155 static inline uint32_t gic_apr_ns_view(GICState *s, int cpu, int regno) 1156 { 1157 /* Return the Nonsecure view of GICC_APR<regno>. This is the 1158 * second half of GICC_NSAPR. 1159 */ 1160 switch (GIC_MIN_BPR) { 1161 case 0: 1162 if (regno < 2) { 1163 return s->nsapr[regno + 2][cpu]; 1164 } 1165 break; 1166 case 1: 1167 if (regno == 0) { 1168 return s->nsapr[regno + 1][cpu]; 1169 } 1170 break; 1171 case 2: 1172 if (regno == 0) { 1173 return extract32(s->nsapr[0][cpu], 16, 16); 1174 } 1175 break; 1176 case 3: 1177 if (regno == 0) { 1178 return extract32(s->nsapr[0][cpu], 8, 8); 1179 } 1180 break; 1181 default: 1182 g_assert_not_reached(); 1183 } 1184 return 0; 1185 } 1186 1187 static inline void gic_apr_write_ns_view(GICState *s, int cpu, int regno, 1188 uint32_t value) 1189 { 1190 /* Write the Nonsecure view of GICC_APR<regno>. */ 1191 switch (GIC_MIN_BPR) { 1192 case 0: 1193 if (regno < 2) { 1194 s->nsapr[regno + 2][cpu] = value; 1195 } 1196 break; 1197 case 1: 1198 if (regno == 0) { 1199 s->nsapr[regno + 1][cpu] = value; 1200 } 1201 break; 1202 case 2: 1203 if (regno == 0) { 1204 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 16, 16, value); 1205 } 1206 break; 1207 case 3: 1208 if (regno == 0) { 1209 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 8, 8, value); 1210 } 1211 break; 1212 default: 1213 g_assert_not_reached(); 1214 } 1215 } 1216 1217 static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset, 1218 uint64_t *data, MemTxAttrs attrs) 1219 { 1220 switch (offset) { 1221 case 0x00: /* Control */ 1222 *data = gic_get_cpu_control(s, cpu, attrs); 1223 break; 1224 case 0x04: /* Priority mask */ 1225 *data = gic_get_priority_mask(s, cpu, attrs); 1226 break; 1227 case 0x08: /* Binary Point */ 1228 if (s->security_extn && !attrs.secure) { 1229 if (s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) { 1230 /* NS view of BPR when CBPR is 1 */ 1231 *data = MIN(s->bpr[cpu] + 1, 7); 1232 } else { 1233 /* BPR is banked. Non-secure copy stored in ABPR. */ 1234 *data = s->abpr[cpu]; 1235 } 1236 } else { 1237 *data = s->bpr[cpu]; 1238 } 1239 break; 1240 case 0x0c: /* Acknowledge */ 1241 *data = gic_acknowledge_irq(s, cpu, attrs); 1242 break; 1243 case 0x14: /* Running Priority */ 1244 *data = gic_get_running_priority(s, cpu, attrs); 1245 break; 1246 case 0x18: /* Highest Pending Interrupt */ 1247 *data = gic_get_current_pending_irq(s, cpu, attrs); 1248 break; 1249 case 0x1c: /* Aliased Binary Point */ 1250 /* GIC v2, no security: ABPR 1251 * GIC v1, no security: not implemented (RAZ/WI) 1252 * With security extensions, secure access: ABPR (alias of NS BPR) 1253 * With security extensions, nonsecure access: RAZ/WI 1254 */ 1255 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 1256 *data = 0; 1257 } else { 1258 *data = s->abpr[cpu]; 1259 } 1260 break; 1261 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 1262 { 1263 int regno = (offset - 0xd0) / 4; 1264 1265 if (regno >= GIC_NR_APRS || s->revision != 2) { 1266 *data = 0; 1267 } else if (s->security_extn && !attrs.secure) { 1268 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ 1269 *data = gic_apr_ns_view(s, regno, cpu); 1270 } else { 1271 *data = s->apr[regno][cpu]; 1272 } 1273 break; 1274 } 1275 case 0xe0: case 0xe4: case 0xe8: case 0xec: 1276 { 1277 int regno = (offset - 0xe0) / 4; 1278 1279 if (regno >= GIC_NR_APRS || s->revision != 2 || !gic_has_groups(s) || 1280 (s->security_extn && !attrs.secure)) { 1281 *data = 0; 1282 } else { 1283 *data = s->nsapr[regno][cpu]; 1284 } 1285 break; 1286 } 1287 default: 1288 qemu_log_mask(LOG_GUEST_ERROR, 1289 "gic_cpu_read: Bad offset %x\n", (int)offset); 1290 *data = 0; 1291 break; 1292 } 1293 return MEMTX_OK; 1294 } 1295 1296 static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset, 1297 uint32_t value, MemTxAttrs attrs) 1298 { 1299 switch (offset) { 1300 case 0x00: /* Control */ 1301 gic_set_cpu_control(s, cpu, value, attrs); 1302 break; 1303 case 0x04: /* Priority mask */ 1304 gic_set_priority_mask(s, cpu, value, attrs); 1305 break; 1306 case 0x08: /* Binary Point */ 1307 if (s->security_extn && !attrs.secure) { 1308 if (s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) { 1309 /* WI when CBPR is 1 */ 1310 return MEMTX_OK; 1311 } else { 1312 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 1313 } 1314 } else { 1315 s->bpr[cpu] = MAX(value & 0x7, GIC_MIN_BPR); 1316 } 1317 break; 1318 case 0x10: /* End Of Interrupt */ 1319 gic_complete_irq(s, cpu, value & 0x3ff, attrs); 1320 return MEMTX_OK; 1321 case 0x1c: /* Aliased Binary Point */ 1322 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 1323 /* unimplemented, or NS access: RAZ/WI */ 1324 return MEMTX_OK; 1325 } else { 1326 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 1327 } 1328 break; 1329 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 1330 { 1331 int regno = (offset - 0xd0) / 4; 1332 1333 if (regno >= GIC_NR_APRS || s->revision != 2) { 1334 return MEMTX_OK; 1335 } 1336 if (s->security_extn && !attrs.secure) { 1337 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ 1338 gic_apr_write_ns_view(s, regno, cpu, value); 1339 } else { 1340 s->apr[regno][cpu] = value; 1341 } 1342 break; 1343 } 1344 case 0xe0: case 0xe4: case 0xe8: case 0xec: 1345 { 1346 int regno = (offset - 0xe0) / 4; 1347 1348 if (regno >= GIC_NR_APRS || s->revision != 2) { 1349 return MEMTX_OK; 1350 } 1351 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 1352 return MEMTX_OK; 1353 } 1354 s->nsapr[regno][cpu] = value; 1355 break; 1356 } 1357 case 0x1000: 1358 /* GICC_DIR */ 1359 gic_deactivate_irq(s, cpu, value & 0x3ff, attrs); 1360 break; 1361 default: 1362 qemu_log_mask(LOG_GUEST_ERROR, 1363 "gic_cpu_write: Bad offset %x\n", (int)offset); 1364 return MEMTX_OK; 1365 } 1366 gic_update(s); 1367 return MEMTX_OK; 1368 } 1369 1370 /* Wrappers to read/write the GIC CPU interface for the current CPU */ 1371 static MemTxResult gic_thiscpu_read(void *opaque, hwaddr addr, uint64_t *data, 1372 unsigned size, MemTxAttrs attrs) 1373 { 1374 GICState *s = (GICState *)opaque; 1375 return gic_cpu_read(s, gic_get_current_cpu(s), addr, data, attrs); 1376 } 1377 1378 static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, 1379 uint64_t value, unsigned size, 1380 MemTxAttrs attrs) 1381 { 1382 GICState *s = (GICState *)opaque; 1383 return gic_cpu_write(s, gic_get_current_cpu(s), addr, value, attrs); 1384 } 1385 1386 /* Wrappers to read/write the GIC CPU interface for a specific CPU. 1387 * These just decode the opaque pointer into GICState* + cpu id. 1388 */ 1389 static MemTxResult gic_do_cpu_read(void *opaque, hwaddr addr, uint64_t *data, 1390 unsigned size, MemTxAttrs attrs) 1391 { 1392 GICState **backref = (GICState **)opaque; 1393 GICState *s = *backref; 1394 int id = (backref - s->backref); 1395 return gic_cpu_read(s, id, addr, data, attrs); 1396 } 1397 1398 static MemTxResult gic_do_cpu_write(void *opaque, hwaddr addr, 1399 uint64_t value, unsigned size, 1400 MemTxAttrs attrs) 1401 { 1402 GICState **backref = (GICState **)opaque; 1403 GICState *s = *backref; 1404 int id = (backref - s->backref); 1405 return gic_cpu_write(s, id, addr, value, attrs); 1406 } 1407 1408 static const MemoryRegionOps gic_ops[2] = { 1409 { 1410 .read_with_attrs = gic_dist_read, 1411 .write_with_attrs = gic_dist_write, 1412 .endianness = DEVICE_NATIVE_ENDIAN, 1413 }, 1414 { 1415 .read_with_attrs = gic_thiscpu_read, 1416 .write_with_attrs = gic_thiscpu_write, 1417 .endianness = DEVICE_NATIVE_ENDIAN, 1418 } 1419 }; 1420 1421 static const MemoryRegionOps gic_cpu_ops = { 1422 .read_with_attrs = gic_do_cpu_read, 1423 .write_with_attrs = gic_do_cpu_write, 1424 .endianness = DEVICE_NATIVE_ENDIAN, 1425 }; 1426 1427 /* This function is used by nvic model */ 1428 void gic_init_irqs_and_distributor(GICState *s) 1429 { 1430 gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops); 1431 } 1432 1433 static void arm_gic_realize(DeviceState *dev, Error **errp) 1434 { 1435 /* Device instance realize function for the GIC sysbus device */ 1436 int i; 1437 GICState *s = ARM_GIC(dev); 1438 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1439 ARMGICClass *agc = ARM_GIC_GET_CLASS(s); 1440 Error *local_err = NULL; 1441 1442 agc->parent_realize(dev, &local_err); 1443 if (local_err) { 1444 error_propagate(errp, local_err); 1445 return; 1446 } 1447 1448 if (kvm_enabled() && !kvm_arm_supports_user_irq()) { 1449 error_setg(errp, "KVM with user space irqchip only works when the " 1450 "host kernel supports KVM_CAP_ARM_USER_IRQ"); 1451 return; 1452 } 1453 1454 /* This creates distributor and main CPU interface (s->cpuiomem[0]) */ 1455 gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops); 1456 1457 /* Extra core-specific regions for the CPU interfaces. This is 1458 * necessary for "franken-GIC" implementations, for example on 1459 * Exynos 4. 1460 * NB that the memory region size of 0x100 applies for the 11MPCore 1461 * and also cores following the GIC v1 spec (ie A9). 1462 * GIC v2 defines a larger memory region (0x1000) so this will need 1463 * to be extended when we implement A15. 1464 */ 1465 for (i = 0; i < s->num_cpu; i++) { 1466 s->backref[i] = s; 1467 memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops, 1468 &s->backref[i], "gic_cpu", 0x100); 1469 sysbus_init_mmio(sbd, &s->cpuiomem[i+1]); 1470 } 1471 } 1472 1473 static void arm_gic_class_init(ObjectClass *klass, void *data) 1474 { 1475 DeviceClass *dc = DEVICE_CLASS(klass); 1476 ARMGICClass *agc = ARM_GIC_CLASS(klass); 1477 1478 device_class_set_parent_realize(dc, arm_gic_realize, &agc->parent_realize); 1479 } 1480 1481 static const TypeInfo arm_gic_info = { 1482 .name = TYPE_ARM_GIC, 1483 .parent = TYPE_ARM_GIC_COMMON, 1484 .instance_size = sizeof(GICState), 1485 .class_init = arm_gic_class_init, 1486 .class_size = sizeof(ARMGICClass), 1487 }; 1488 1489 static void arm_gic_register_types(void) 1490 { 1491 type_register_static(&arm_gic_info); 1492 } 1493 1494 type_init(arm_gic_register_types) 1495