1 /* 2 * ARM Generic/Distributed Interrupt Controller 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 /* This file contains implementation code for the RealView EB interrupt 11 * controller, MPCore distributed interrupt controller and ARMv7-M 12 * Nested Vectored Interrupt Controller. 13 * It is compiled in two ways: 14 * (1) as a standalone file to produce a sysbus device which is a GIC 15 * that can be used on the realview board and as one of the builtin 16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc) 17 * (2) by being directly #included into armv7m_nvic.c to produce the 18 * armv7m_nvic device. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/irq.h" 23 #include "hw/sysbus.h" 24 #include "gic_internal.h" 25 #include "qapi/error.h" 26 #include "hw/core/cpu.h" 27 #include "qemu/log.h" 28 #include "qemu/module.h" 29 #include "trace.h" 30 #include "sysemu/kvm.h" 31 32 /* #define DEBUG_GIC */ 33 34 #ifdef DEBUG_GIC 35 #define DEBUG_GIC_GATE 1 36 #else 37 #define DEBUG_GIC_GATE 0 38 #endif 39 40 #define DPRINTF(fmt, ...) do { \ 41 if (DEBUG_GIC_GATE) { \ 42 fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \ 43 } \ 44 } while (0) 45 46 static const uint8_t gic_id_11mpcore[] = { 47 0x00, 0x00, 0x00, 0x00, 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 48 }; 49 50 static const uint8_t gic_id_gicv1[] = { 51 0x04, 0x00, 0x00, 0x00, 0x90, 0xb3, 0x1b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 52 }; 53 54 static const uint8_t gic_id_gicv2[] = { 55 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 56 }; 57 58 static inline int gic_get_current_cpu(GICState *s) 59 { 60 if (s->num_cpu > 1) { 61 return current_cpu->cpu_index; 62 } 63 return 0; 64 } 65 66 static inline int gic_get_current_vcpu(GICState *s) 67 { 68 return gic_get_current_cpu(s) + GIC_NCPU; 69 } 70 71 /* Return true if this GIC config has interrupt groups, which is 72 * true if we're a GICv2, or a GICv1 with the security extensions. 73 */ 74 static inline bool gic_has_groups(GICState *s) 75 { 76 return s->revision == 2 || s->security_extn; 77 } 78 79 static inline bool gic_cpu_ns_access(GICState *s, int cpu, MemTxAttrs attrs) 80 { 81 return !gic_is_vcpu(cpu) && s->security_extn && !attrs.secure; 82 } 83 84 static inline void gic_get_best_irq(GICState *s, int cpu, 85 int *best_irq, int *best_prio, int *group) 86 { 87 int irq; 88 int cm = 1 << cpu; 89 90 *best_irq = 1023; 91 *best_prio = 0x100; 92 93 for (irq = 0; irq < s->num_irq; irq++) { 94 if (GIC_DIST_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm) && 95 (!GIC_DIST_TEST_ACTIVE(irq, cm)) && 96 (irq < GIC_INTERNAL || GIC_DIST_TARGET(irq) & cm)) { 97 if (GIC_DIST_GET_PRIORITY(irq, cpu) < *best_prio) { 98 *best_prio = GIC_DIST_GET_PRIORITY(irq, cpu); 99 *best_irq = irq; 100 } 101 } 102 } 103 104 if (*best_irq < 1023) { 105 *group = GIC_DIST_TEST_GROUP(*best_irq, cm); 106 } 107 } 108 109 static inline void gic_get_best_virq(GICState *s, int cpu, 110 int *best_irq, int *best_prio, int *group) 111 { 112 int lr_idx = 0; 113 114 *best_irq = 1023; 115 *best_prio = 0x100; 116 117 for (lr_idx = 0; lr_idx < s->num_lrs; lr_idx++) { 118 uint32_t lr_entry = s->h_lr[lr_idx][cpu]; 119 int state = GICH_LR_STATE(lr_entry); 120 121 if (state == GICH_LR_STATE_PENDING) { 122 int prio = GICH_LR_PRIORITY(lr_entry); 123 124 if (prio < *best_prio) { 125 *best_prio = prio; 126 *best_irq = GICH_LR_VIRT_ID(lr_entry); 127 *group = GICH_LR_GROUP(lr_entry); 128 } 129 } 130 } 131 } 132 133 /* Return true if IRQ signaling is enabled for the given cpu and at least one 134 * of the given groups: 135 * - in the non-virt case, the distributor must be enabled for one of the 136 * given groups 137 * - in the virt case, the virtual interface must be enabled. 138 * - in all cases, the (v)CPU interface must be enabled for one of the given 139 * groups. 140 */ 141 static inline bool gic_irq_signaling_enabled(GICState *s, int cpu, bool virt, 142 int group_mask) 143 { 144 if (!virt && !(s->ctlr & group_mask)) { 145 return false; 146 } 147 148 if (virt && !(s->h_hcr[cpu] & R_GICH_HCR_EN_MASK)) { 149 return false; 150 } 151 152 if (!(s->cpu_ctlr[cpu] & group_mask)) { 153 return false; 154 } 155 156 return true; 157 } 158 159 /* TODO: Many places that call this routine could be optimized. */ 160 /* Update interrupt status after enabled or pending bits have been changed. */ 161 static inline void gic_update_internal(GICState *s, bool virt) 162 { 163 int best_irq; 164 int best_prio; 165 int irq_level, fiq_level; 166 int cpu, cpu_iface; 167 int group = 0; 168 qemu_irq *irq_lines = virt ? s->parent_virq : s->parent_irq; 169 qemu_irq *fiq_lines = virt ? s->parent_vfiq : s->parent_fiq; 170 171 for (cpu = 0; cpu < s->num_cpu; cpu++) { 172 cpu_iface = virt ? (cpu + GIC_NCPU) : cpu; 173 174 s->current_pending[cpu_iface] = 1023; 175 if (!gic_irq_signaling_enabled(s, cpu, virt, 176 GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1)) { 177 qemu_irq_lower(irq_lines[cpu]); 178 qemu_irq_lower(fiq_lines[cpu]); 179 continue; 180 } 181 182 if (virt) { 183 gic_get_best_virq(s, cpu, &best_irq, &best_prio, &group); 184 } else { 185 gic_get_best_irq(s, cpu, &best_irq, &best_prio, &group); 186 } 187 188 if (best_irq != 1023) { 189 trace_gic_update_bestirq(virt ? "vcpu" : "cpu", cpu, 190 best_irq, best_prio, 191 s->priority_mask[cpu_iface], 192 s->running_priority[cpu_iface]); 193 } 194 195 irq_level = fiq_level = 0; 196 197 if (best_prio < s->priority_mask[cpu_iface]) { 198 s->current_pending[cpu_iface] = best_irq; 199 if (best_prio < s->running_priority[cpu_iface]) { 200 if (gic_irq_signaling_enabled(s, cpu, virt, 1 << group)) { 201 if (group == 0 && 202 s->cpu_ctlr[cpu_iface] & GICC_CTLR_FIQ_EN) { 203 DPRINTF("Raised pending FIQ %d (cpu %d)\n", 204 best_irq, cpu_iface); 205 fiq_level = 1; 206 trace_gic_update_set_irq(cpu, virt ? "vfiq" : "fiq", 207 fiq_level); 208 } else { 209 DPRINTF("Raised pending IRQ %d (cpu %d)\n", 210 best_irq, cpu_iface); 211 irq_level = 1; 212 trace_gic_update_set_irq(cpu, virt ? "virq" : "irq", 213 irq_level); 214 } 215 } 216 } 217 } 218 219 qemu_set_irq(irq_lines[cpu], irq_level); 220 qemu_set_irq(fiq_lines[cpu], fiq_level); 221 } 222 } 223 224 static void gic_update(GICState *s) 225 { 226 gic_update_internal(s, false); 227 } 228 229 /* Return true if this LR is empty, i.e. the corresponding bit 230 * in ELRSR is set. 231 */ 232 static inline bool gic_lr_entry_is_free(uint32_t entry) 233 { 234 return (GICH_LR_STATE(entry) == GICH_LR_STATE_INVALID) 235 && (GICH_LR_HW(entry) || !GICH_LR_EOI(entry)); 236 } 237 238 /* Return true if this LR should trigger an EOI maintenance interrupt, i.e. the 239 * corrsponding bit in EISR is set. 240 */ 241 static inline bool gic_lr_entry_is_eoi(uint32_t entry) 242 { 243 return (GICH_LR_STATE(entry) == GICH_LR_STATE_INVALID) 244 && !GICH_LR_HW(entry) && GICH_LR_EOI(entry); 245 } 246 247 static inline void gic_extract_lr_info(GICState *s, int cpu, 248 int *num_eoi, int *num_valid, int *num_pending) 249 { 250 int lr_idx; 251 252 *num_eoi = 0; 253 *num_valid = 0; 254 *num_pending = 0; 255 256 for (lr_idx = 0; lr_idx < s->num_lrs; lr_idx++) { 257 uint32_t *entry = &s->h_lr[lr_idx][cpu]; 258 259 if (gic_lr_entry_is_eoi(*entry)) { 260 (*num_eoi)++; 261 } 262 263 if (GICH_LR_STATE(*entry) != GICH_LR_STATE_INVALID) { 264 (*num_valid)++; 265 } 266 267 if (GICH_LR_STATE(*entry) == GICH_LR_STATE_PENDING) { 268 (*num_pending)++; 269 } 270 } 271 } 272 273 static void gic_compute_misr(GICState *s, int cpu) 274 { 275 uint32_t value = 0; 276 int vcpu = cpu + GIC_NCPU; 277 278 int num_eoi, num_valid, num_pending; 279 280 gic_extract_lr_info(s, cpu, &num_eoi, &num_valid, &num_pending); 281 282 /* EOI */ 283 if (num_eoi) { 284 value |= R_GICH_MISR_EOI_MASK; 285 } 286 287 /* U: true if only 0 or 1 LR entry is valid */ 288 if ((s->h_hcr[cpu] & R_GICH_HCR_UIE_MASK) && (num_valid < 2)) { 289 value |= R_GICH_MISR_U_MASK; 290 } 291 292 /* LRENP: EOICount is not 0 */ 293 if ((s->h_hcr[cpu] & R_GICH_HCR_LRENPIE_MASK) && 294 ((s->h_hcr[cpu] & R_GICH_HCR_EOICount_MASK) != 0)) { 295 value |= R_GICH_MISR_LRENP_MASK; 296 } 297 298 /* NP: no pending interrupts */ 299 if ((s->h_hcr[cpu] & R_GICH_HCR_NPIE_MASK) && (num_pending == 0)) { 300 value |= R_GICH_MISR_NP_MASK; 301 } 302 303 /* VGrp0E: group0 virq signaling enabled */ 304 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP0EIE_MASK) && 305 (s->cpu_ctlr[vcpu] & GICC_CTLR_EN_GRP0)) { 306 value |= R_GICH_MISR_VGrp0E_MASK; 307 } 308 309 /* VGrp0D: group0 virq signaling disabled */ 310 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP0DIE_MASK) && 311 !(s->cpu_ctlr[vcpu] & GICC_CTLR_EN_GRP0)) { 312 value |= R_GICH_MISR_VGrp0D_MASK; 313 } 314 315 /* VGrp1E: group1 virq signaling enabled */ 316 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP1EIE_MASK) && 317 (s->cpu_ctlr[vcpu] & GICC_CTLR_EN_GRP1)) { 318 value |= R_GICH_MISR_VGrp1E_MASK; 319 } 320 321 /* VGrp1D: group1 virq signaling disabled */ 322 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP1DIE_MASK) && 323 !(s->cpu_ctlr[vcpu] & GICC_CTLR_EN_GRP1)) { 324 value |= R_GICH_MISR_VGrp1D_MASK; 325 } 326 327 s->h_misr[cpu] = value; 328 } 329 330 static void gic_update_maintenance(GICState *s) 331 { 332 int cpu = 0; 333 int maint_level; 334 335 for (cpu = 0; cpu < s->num_cpu; cpu++) { 336 gic_compute_misr(s, cpu); 337 maint_level = (s->h_hcr[cpu] & R_GICH_HCR_EN_MASK) && s->h_misr[cpu]; 338 339 trace_gic_update_maintenance_irq(cpu, maint_level); 340 qemu_set_irq(s->maintenance_irq[cpu], maint_level); 341 } 342 } 343 344 static void gic_update_virt(GICState *s) 345 { 346 gic_update_internal(s, true); 347 gic_update_maintenance(s); 348 } 349 350 static void gic_set_irq_11mpcore(GICState *s, int irq, int level, 351 int cm, int target) 352 { 353 if (level) { 354 GIC_DIST_SET_LEVEL(irq, cm); 355 if (GIC_DIST_TEST_EDGE_TRIGGER(irq) || GIC_DIST_TEST_ENABLED(irq, cm)) { 356 DPRINTF("Set %d pending mask %x\n", irq, target); 357 GIC_DIST_SET_PENDING(irq, target); 358 } 359 } else { 360 GIC_DIST_CLEAR_LEVEL(irq, cm); 361 } 362 } 363 364 static void gic_set_irq_generic(GICState *s, int irq, int level, 365 int cm, int target) 366 { 367 if (level) { 368 GIC_DIST_SET_LEVEL(irq, cm); 369 DPRINTF("Set %d pending mask %x\n", irq, target); 370 if (GIC_DIST_TEST_EDGE_TRIGGER(irq)) { 371 GIC_DIST_SET_PENDING(irq, target); 372 } 373 } else { 374 GIC_DIST_CLEAR_LEVEL(irq, cm); 375 } 376 } 377 378 /* Process a change in an external IRQ input. */ 379 static void gic_set_irq(void *opaque, int irq, int level) 380 { 381 /* Meaning of the 'irq' parameter: 382 * [0..N-1] : external interrupts 383 * [N..N+31] : PPI (internal) interrupts for CPU 0 384 * [N+32..N+63] : PPI (internal interrupts for CPU 1 385 * ... 386 */ 387 GICState *s = (GICState *)opaque; 388 int cm, target; 389 if (irq < (s->num_irq - GIC_INTERNAL)) { 390 /* The first external input line is internal interrupt 32. */ 391 cm = ALL_CPU_MASK; 392 irq += GIC_INTERNAL; 393 target = GIC_DIST_TARGET(irq); 394 } else { 395 int cpu; 396 irq -= (s->num_irq - GIC_INTERNAL); 397 cpu = irq / GIC_INTERNAL; 398 irq %= GIC_INTERNAL; 399 cm = 1 << cpu; 400 target = cm; 401 } 402 403 assert(irq >= GIC_NR_SGIS); 404 405 if (level == GIC_DIST_TEST_LEVEL(irq, cm)) { 406 return; 407 } 408 409 if (s->revision == REV_11MPCORE) { 410 gic_set_irq_11mpcore(s, irq, level, cm, target); 411 } else { 412 gic_set_irq_generic(s, irq, level, cm, target); 413 } 414 trace_gic_set_irq(irq, level, cm, target); 415 416 gic_update(s); 417 } 418 419 static uint16_t gic_get_current_pending_irq(GICState *s, int cpu, 420 MemTxAttrs attrs) 421 { 422 uint16_t pending_irq = s->current_pending[cpu]; 423 424 if (pending_irq < GIC_MAXIRQ && gic_has_groups(s)) { 425 int group = gic_test_group(s, pending_irq, cpu); 426 427 /* On a GIC without the security extensions, reading this register 428 * behaves in the same way as a secure access to a GIC with them. 429 */ 430 bool secure = !gic_cpu_ns_access(s, cpu, attrs); 431 432 if (group == 0 && !secure) { 433 /* Group0 interrupts hidden from Non-secure access */ 434 return 1023; 435 } 436 if (group == 1 && secure && !(s->cpu_ctlr[cpu] & GICC_CTLR_ACK_CTL)) { 437 /* Group1 interrupts only seen by Secure access if 438 * AckCtl bit set. 439 */ 440 return 1022; 441 } 442 } 443 return pending_irq; 444 } 445 446 static int gic_get_group_priority(GICState *s, int cpu, int irq) 447 { 448 /* Return the group priority of the specified interrupt 449 * (which is the top bits of its priority, with the number 450 * of bits masked determined by the applicable binary point register). 451 */ 452 int bpr; 453 uint32_t mask; 454 455 if (gic_has_groups(s) && 456 !(s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) && 457 gic_test_group(s, irq, cpu)) { 458 bpr = s->abpr[cpu] - 1; 459 assert(bpr >= 0); 460 } else { 461 bpr = s->bpr[cpu]; 462 } 463 464 /* a BPR of 0 means the group priority bits are [7:1]; 465 * a BPR of 1 means they are [7:2], and so on down to 466 * a BPR of 7 meaning no group priority bits at all. 467 */ 468 mask = ~0U << ((bpr & 7) + 1); 469 470 return gic_get_priority(s, irq, cpu) & mask; 471 } 472 473 static void gic_activate_irq(GICState *s, int cpu, int irq) 474 { 475 /* Set the appropriate Active Priority Register bit for this IRQ, 476 * and update the running priority. 477 */ 478 int prio = gic_get_group_priority(s, cpu, irq); 479 int min_bpr = gic_is_vcpu(cpu) ? GIC_VIRT_MIN_BPR : GIC_MIN_BPR; 480 int preemption_level = prio >> (min_bpr + 1); 481 int regno = preemption_level / 32; 482 int bitno = preemption_level % 32; 483 uint32_t *papr = NULL; 484 485 if (gic_is_vcpu(cpu)) { 486 assert(regno == 0); 487 papr = &s->h_apr[gic_get_vcpu_real_id(cpu)]; 488 } else if (gic_has_groups(s) && gic_test_group(s, irq, cpu)) { 489 papr = &s->nsapr[regno][cpu]; 490 } else { 491 papr = &s->apr[regno][cpu]; 492 } 493 494 *papr |= (1 << bitno); 495 496 s->running_priority[cpu] = prio; 497 gic_set_active(s, irq, cpu); 498 } 499 500 static int gic_get_prio_from_apr_bits(GICState *s, int cpu) 501 { 502 /* Recalculate the current running priority for this CPU based 503 * on the set bits in the Active Priority Registers. 504 */ 505 int i; 506 507 if (gic_is_vcpu(cpu)) { 508 uint32_t apr = s->h_apr[gic_get_vcpu_real_id(cpu)]; 509 if (apr) { 510 return ctz32(apr) << (GIC_VIRT_MIN_BPR + 1); 511 } else { 512 return 0x100; 513 } 514 } 515 516 for (i = 0; i < GIC_NR_APRS; i++) { 517 uint32_t apr = s->apr[i][cpu] | s->nsapr[i][cpu]; 518 if (!apr) { 519 continue; 520 } 521 return (i * 32 + ctz32(apr)) << (GIC_MIN_BPR + 1); 522 } 523 return 0x100; 524 } 525 526 static void gic_drop_prio(GICState *s, int cpu, int group) 527 { 528 /* Drop the priority of the currently active interrupt in the 529 * specified group. 530 * 531 * Note that we can guarantee (because of the requirement to nest 532 * GICC_IAR reads [which activate an interrupt and raise priority] 533 * with GICC_EOIR writes [which drop the priority for the interrupt]) 534 * that the interrupt we're being called for is the highest priority 535 * active interrupt, meaning that it has the lowest set bit in the 536 * APR registers. 537 * 538 * If the guest does not honour the ordering constraints then the 539 * behaviour of the GIC is UNPREDICTABLE, which for us means that 540 * the values of the APR registers might become incorrect and the 541 * running priority will be wrong, so interrupts that should preempt 542 * might not do so, and interrupts that should not preempt might do so. 543 */ 544 if (gic_is_vcpu(cpu)) { 545 int rcpu = gic_get_vcpu_real_id(cpu); 546 547 if (s->h_apr[rcpu]) { 548 /* Clear lowest set bit */ 549 s->h_apr[rcpu] &= s->h_apr[rcpu] - 1; 550 } 551 } else { 552 int i; 553 554 for (i = 0; i < GIC_NR_APRS; i++) { 555 uint32_t *papr = group ? &s->nsapr[i][cpu] : &s->apr[i][cpu]; 556 if (!*papr) { 557 continue; 558 } 559 /* Clear lowest set bit */ 560 *papr &= *papr - 1; 561 break; 562 } 563 } 564 565 s->running_priority[cpu] = gic_get_prio_from_apr_bits(s, cpu); 566 } 567 568 static inline uint32_t gic_clear_pending_sgi(GICState *s, int irq, int cpu) 569 { 570 int src; 571 uint32_t ret; 572 573 if (!gic_is_vcpu(cpu)) { 574 /* Lookup the source CPU for the SGI and clear this in the 575 * sgi_pending map. Return the src and clear the overall pending 576 * state on this CPU if the SGI is not pending from any CPUs. 577 */ 578 assert(s->sgi_pending[irq][cpu] != 0); 579 src = ctz32(s->sgi_pending[irq][cpu]); 580 s->sgi_pending[irq][cpu] &= ~(1 << src); 581 if (s->sgi_pending[irq][cpu] == 0) { 582 gic_clear_pending(s, irq, cpu); 583 } 584 ret = irq | ((src & 0x7) << 10); 585 } else { 586 uint32_t *lr_entry = gic_get_lr_entry(s, irq, cpu); 587 src = GICH_LR_CPUID(*lr_entry); 588 589 gic_clear_pending(s, irq, cpu); 590 ret = irq | (src << 10); 591 } 592 593 return ret; 594 } 595 596 uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs) 597 { 598 int ret, irq; 599 600 /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately 601 * for the case where this GIC supports grouping and the pending interrupt 602 * is in the wrong group. 603 */ 604 irq = gic_get_current_pending_irq(s, cpu, attrs); 605 trace_gic_acknowledge_irq(gic_is_vcpu(cpu) ? "vcpu" : "cpu", 606 gic_get_vcpu_real_id(cpu), irq); 607 608 if (irq >= GIC_MAXIRQ) { 609 DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq); 610 return irq; 611 } 612 613 if (gic_get_priority(s, irq, cpu) >= s->running_priority[cpu]) { 614 DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq); 615 return 1023; 616 } 617 618 gic_activate_irq(s, cpu, irq); 619 620 if (s->revision == REV_11MPCORE) { 621 /* Clear pending flags for both level and edge triggered interrupts. 622 * Level triggered IRQs will be reasserted once they become inactive. 623 */ 624 gic_clear_pending(s, irq, cpu); 625 ret = irq; 626 } else { 627 if (irq < GIC_NR_SGIS) { 628 ret = gic_clear_pending_sgi(s, irq, cpu); 629 } else { 630 gic_clear_pending(s, irq, cpu); 631 ret = irq; 632 } 633 } 634 635 if (gic_is_vcpu(cpu)) { 636 gic_update_virt(s); 637 } else { 638 gic_update(s); 639 } 640 DPRINTF("ACK %d\n", irq); 641 return ret; 642 } 643 644 static uint32_t gic_fullprio_mask(GICState *s, int cpu) 645 { 646 /* 647 * Return a mask word which clears the unimplemented priority 648 * bits from a priority value for an interrupt. (Not to be 649 * confused with the group priority, whose mask depends on BPR.) 650 */ 651 int priBits; 652 653 if (gic_is_vcpu(cpu)) { 654 priBits = GIC_VIRT_MAX_GROUP_PRIO_BITS; 655 } else { 656 priBits = s->n_prio_bits; 657 } 658 return ~0U << (8 - priBits); 659 } 660 661 void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val, 662 MemTxAttrs attrs) 663 { 664 if (s->security_extn && !attrs.secure) { 665 if (!GIC_DIST_TEST_GROUP(irq, (1 << cpu))) { 666 return; /* Ignore Non-secure access of Group0 IRQ */ 667 } 668 val = 0x80 | (val >> 1); /* Non-secure view */ 669 } 670 671 val &= gic_fullprio_mask(s, cpu); 672 673 if (irq < GIC_INTERNAL) { 674 s->priority1[irq][cpu] = val; 675 } else { 676 s->priority2[(irq) - GIC_INTERNAL] = val; 677 } 678 } 679 680 static uint32_t gic_dist_get_priority(GICState *s, int cpu, int irq, 681 MemTxAttrs attrs) 682 { 683 uint32_t prio = GIC_DIST_GET_PRIORITY(irq, cpu); 684 685 if (s->security_extn && !attrs.secure) { 686 if (!GIC_DIST_TEST_GROUP(irq, (1 << cpu))) { 687 return 0; /* Non-secure access cannot read priority of Group0 IRQ */ 688 } 689 prio = (prio << 1) & 0xff; /* Non-secure view */ 690 } 691 return prio & gic_fullprio_mask(s, cpu); 692 } 693 694 static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, 695 MemTxAttrs attrs) 696 { 697 if (gic_cpu_ns_access(s, cpu, attrs)) { 698 if (s->priority_mask[cpu] & 0x80) { 699 /* Priority Mask in upper half */ 700 pmask = 0x80 | (pmask >> 1); 701 } else { 702 /* Non-secure write ignored if priority mask is in lower half */ 703 return; 704 } 705 } 706 s->priority_mask[cpu] = pmask & gic_fullprio_mask(s, cpu); 707 } 708 709 static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs) 710 { 711 uint32_t pmask = s->priority_mask[cpu]; 712 713 if (gic_cpu_ns_access(s, cpu, attrs)) { 714 if (pmask & 0x80) { 715 /* Priority Mask in upper half, return Non-secure view */ 716 pmask = (pmask << 1) & 0xff; 717 } else { 718 /* Priority Mask in lower half, RAZ */ 719 pmask = 0; 720 } 721 } 722 return pmask; 723 } 724 725 static uint32_t gic_get_cpu_control(GICState *s, int cpu, MemTxAttrs attrs) 726 { 727 uint32_t ret = s->cpu_ctlr[cpu]; 728 729 if (gic_cpu_ns_access(s, cpu, attrs)) { 730 /* Construct the NS banked view of GICC_CTLR from the correct 731 * bits of the S banked view. We don't need to move the bypass 732 * control bits because we don't implement that (IMPDEF) part 733 * of the GIC architecture. 734 */ 735 ret = (ret & (GICC_CTLR_EN_GRP1 | GICC_CTLR_EOIMODE_NS)) >> 1; 736 } 737 return ret; 738 } 739 740 static void gic_set_cpu_control(GICState *s, int cpu, uint32_t value, 741 MemTxAttrs attrs) 742 { 743 uint32_t mask; 744 745 if (gic_cpu_ns_access(s, cpu, attrs)) { 746 /* The NS view can only write certain bits in the register; 747 * the rest are unchanged 748 */ 749 mask = GICC_CTLR_EN_GRP1; 750 if (s->revision == 2) { 751 mask |= GICC_CTLR_EOIMODE_NS; 752 } 753 s->cpu_ctlr[cpu] &= ~mask; 754 s->cpu_ctlr[cpu] |= (value << 1) & mask; 755 } else { 756 if (s->revision == 2) { 757 mask = s->security_extn ? GICC_CTLR_V2_S_MASK : GICC_CTLR_V2_MASK; 758 } else { 759 mask = s->security_extn ? GICC_CTLR_V1_S_MASK : GICC_CTLR_V1_MASK; 760 } 761 s->cpu_ctlr[cpu] = value & mask; 762 } 763 DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, " 764 "Group1 Interrupts %sabled\n", cpu, 765 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP0) ? "En" : "Dis", 766 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP1) ? "En" : "Dis"); 767 } 768 769 static uint8_t gic_get_running_priority(GICState *s, int cpu, MemTxAttrs attrs) 770 { 771 if ((s->revision != REV_11MPCORE) && (s->running_priority[cpu] > 0xff)) { 772 /* Idle priority */ 773 return 0xff; 774 } 775 776 if (gic_cpu_ns_access(s, cpu, attrs)) { 777 if (s->running_priority[cpu] & 0x80) { 778 /* Running priority in upper half of range: return the Non-secure 779 * view of the priority. 780 */ 781 return s->running_priority[cpu] << 1; 782 } else { 783 /* Running priority in lower half of range: RAZ */ 784 return 0; 785 } 786 } else { 787 return s->running_priority[cpu]; 788 } 789 } 790 791 /* Return true if we should split priority drop and interrupt deactivation, 792 * ie whether the relevant EOIMode bit is set. 793 */ 794 static bool gic_eoi_split(GICState *s, int cpu, MemTxAttrs attrs) 795 { 796 if (s->revision != 2) { 797 /* Before GICv2 prio-drop and deactivate are not separable */ 798 return false; 799 } 800 if (gic_cpu_ns_access(s, cpu, attrs)) { 801 return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE_NS; 802 } 803 return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE; 804 } 805 806 static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) 807 { 808 int group; 809 810 if (irq >= GIC_MAXIRQ || (!gic_is_vcpu(cpu) && irq >= s->num_irq)) { 811 /* 812 * This handles two cases: 813 * 1. If software writes the ID of a spurious interrupt [ie 1023] 814 * to the GICC_DIR, the GIC ignores that write. 815 * 2. If software writes the number of a non-existent interrupt 816 * this must be a subcase of "value written is not an active interrupt" 817 * and so this is UNPREDICTABLE. We choose to ignore it. For vCPUs, 818 * all IRQs potentially exist, so this limit does not apply. 819 */ 820 return; 821 } 822 823 if (!gic_eoi_split(s, cpu, attrs)) { 824 /* This is UNPREDICTABLE; we choose to ignore it */ 825 qemu_log_mask(LOG_GUEST_ERROR, 826 "gic_deactivate_irq: GICC_DIR write when EOIMode clear"); 827 return; 828 } 829 830 if (gic_is_vcpu(cpu) && !gic_virq_is_valid(s, irq, cpu)) { 831 /* This vIRQ does not have an LR entry which is either active or 832 * pending and active. Increment EOICount and ignore the write. 833 */ 834 int rcpu = gic_get_vcpu_real_id(cpu); 835 s->h_hcr[rcpu] += 1 << R_GICH_HCR_EOICount_SHIFT; 836 837 /* Update the virtual interface in case a maintenance interrupt should 838 * be raised. 839 */ 840 gic_update_virt(s); 841 return; 842 } 843 844 group = gic_has_groups(s) && gic_test_group(s, irq, cpu); 845 846 if (gic_cpu_ns_access(s, cpu, attrs) && !group) { 847 DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq); 848 return; 849 } 850 851 gic_clear_active(s, irq, cpu); 852 } 853 854 static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) 855 { 856 int cm = 1 << cpu; 857 int group; 858 859 DPRINTF("EOI %d\n", irq); 860 if (gic_is_vcpu(cpu)) { 861 /* The call to gic_prio_drop() will clear a bit in GICH_APR iff the 862 * running prio is < 0x100. 863 */ 864 bool prio_drop = s->running_priority[cpu] < 0x100; 865 866 if (irq >= GIC_MAXIRQ) { 867 /* Ignore spurious interrupt */ 868 return; 869 } 870 871 gic_drop_prio(s, cpu, 0); 872 873 if (!gic_eoi_split(s, cpu, attrs)) { 874 bool valid = gic_virq_is_valid(s, irq, cpu); 875 if (prio_drop && !valid) { 876 /* We are in a situation where: 877 * - V_CTRL.EOIMode is false (no EOI split), 878 * - The call to gic_drop_prio() cleared a bit in GICH_APR, 879 * - This vIRQ does not have an LR entry which is either 880 * active or pending and active. 881 * In that case, we must increment EOICount. 882 */ 883 int rcpu = gic_get_vcpu_real_id(cpu); 884 s->h_hcr[rcpu] += 1 << R_GICH_HCR_EOICount_SHIFT; 885 } else if (valid) { 886 gic_clear_active(s, irq, cpu); 887 } 888 } 889 890 gic_update_virt(s); 891 return; 892 } 893 894 if (irq >= s->num_irq) { 895 /* This handles two cases: 896 * 1. If software writes the ID of a spurious interrupt [ie 1023] 897 * to the GICC_EOIR, the GIC ignores that write. 898 * 2. If software writes the number of a non-existent interrupt 899 * this must be a subcase of "value written does not match the last 900 * valid interrupt value read from the Interrupt Acknowledge 901 * register" and so this is UNPREDICTABLE. We choose to ignore it. 902 */ 903 return; 904 } 905 if (s->running_priority[cpu] == 0x100) { 906 return; /* No active IRQ. */ 907 } 908 909 if (s->revision == REV_11MPCORE) { 910 /* Mark level triggered interrupts as pending if they are still 911 raised. */ 912 if (!GIC_DIST_TEST_EDGE_TRIGGER(irq) && GIC_DIST_TEST_ENABLED(irq, cm) 913 && GIC_DIST_TEST_LEVEL(irq, cm) 914 && (GIC_DIST_TARGET(irq) & cm) != 0) { 915 DPRINTF("Set %d pending mask %x\n", irq, cm); 916 GIC_DIST_SET_PENDING(irq, cm); 917 } 918 } 919 920 group = gic_has_groups(s) && gic_test_group(s, irq, cpu); 921 922 if (gic_cpu_ns_access(s, cpu, attrs) && !group) { 923 DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq); 924 return; 925 } 926 927 /* Secure EOI with GICC_CTLR.AckCtl == 0 when the IRQ is a Group 1 928 * interrupt is UNPREDICTABLE. We choose to handle it as if AckCtl == 1, 929 * i.e. go ahead and complete the irq anyway. 930 */ 931 932 gic_drop_prio(s, cpu, group); 933 934 /* In GICv2 the guest can choose to split priority-drop and deactivate */ 935 if (!gic_eoi_split(s, cpu, attrs)) { 936 gic_clear_active(s, irq, cpu); 937 } 938 gic_update(s); 939 } 940 941 static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) 942 { 943 GICState *s = (GICState *)opaque; 944 uint32_t res; 945 int irq; 946 int i; 947 int cpu; 948 int cm; 949 int mask; 950 951 cpu = gic_get_current_cpu(s); 952 cm = 1 << cpu; 953 if (offset < 0x100) { 954 if (offset == 0) { /* GICD_CTLR */ 955 if (s->security_extn && !attrs.secure) { 956 /* The NS bank of this register is just an alias of the 957 * EnableGrp1 bit in the S bank version. 958 */ 959 return extract32(s->ctlr, 1, 1); 960 } else { 961 return s->ctlr; 962 } 963 } 964 if (offset == 4) 965 /* Interrupt Controller Type Register */ 966 return ((s->num_irq / 32) - 1) 967 | ((s->num_cpu - 1) << 5) 968 | (s->security_extn << 10); 969 if (offset < 0x08) 970 return 0; 971 if (offset >= 0x80) { 972 /* Interrupt Group Registers: these RAZ/WI if this is an NS 973 * access to a GIC with the security extensions, or if the GIC 974 * doesn't have groups at all. 975 */ 976 res = 0; 977 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 978 /* Every byte offset holds 8 group status bits */ 979 irq = (offset - 0x080) * 8; 980 if (irq >= s->num_irq) { 981 goto bad_reg; 982 } 983 for (i = 0; i < 8; i++) { 984 if (GIC_DIST_TEST_GROUP(irq + i, cm)) { 985 res |= (1 << i); 986 } 987 } 988 } 989 return res; 990 } 991 goto bad_reg; 992 } else if (offset < 0x200) { 993 /* Interrupt Set/Clear Enable. */ 994 if (offset < 0x180) 995 irq = (offset - 0x100) * 8; 996 else 997 irq = (offset - 0x180) * 8; 998 if (irq >= s->num_irq) 999 goto bad_reg; 1000 res = 0; 1001 for (i = 0; i < 8; i++) { 1002 if (s->security_extn && !attrs.secure && 1003 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 1004 continue; /* Ignore Non-secure access of Group0 IRQ */ 1005 } 1006 1007 if (GIC_DIST_TEST_ENABLED(irq + i, cm)) { 1008 res |= (1 << i); 1009 } 1010 } 1011 } else if (offset < 0x300) { 1012 /* Interrupt Set/Clear Pending. */ 1013 if (offset < 0x280) 1014 irq = (offset - 0x200) * 8; 1015 else 1016 irq = (offset - 0x280) * 8; 1017 if (irq >= s->num_irq) 1018 goto bad_reg; 1019 res = 0; 1020 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 1021 for (i = 0; i < 8; i++) { 1022 if (s->security_extn && !attrs.secure && 1023 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 1024 continue; /* Ignore Non-secure access of Group0 IRQ */ 1025 } 1026 1027 if (gic_test_pending(s, irq + i, mask)) { 1028 res |= (1 << i); 1029 } 1030 } 1031 } else if (offset < 0x400) { 1032 /* Interrupt Set/Clear Active. */ 1033 if (offset < 0x380) { 1034 irq = (offset - 0x300) * 8; 1035 } else if (s->revision == 2) { 1036 irq = (offset - 0x380) * 8; 1037 } else { 1038 goto bad_reg; 1039 } 1040 1041 if (irq >= s->num_irq) 1042 goto bad_reg; 1043 res = 0; 1044 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 1045 for (i = 0; i < 8; i++) { 1046 if (s->security_extn && !attrs.secure && 1047 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 1048 continue; /* Ignore Non-secure access of Group0 IRQ */ 1049 } 1050 1051 if (GIC_DIST_TEST_ACTIVE(irq + i, mask)) { 1052 res |= (1 << i); 1053 } 1054 } 1055 } else if (offset < 0x800) { 1056 /* Interrupt Priority. */ 1057 irq = (offset - 0x400); 1058 if (irq >= s->num_irq) 1059 goto bad_reg; 1060 res = gic_dist_get_priority(s, cpu, irq, attrs); 1061 } else if (offset < 0xc00) { 1062 /* Interrupt CPU Target. */ 1063 if (s->num_cpu == 1 && s->revision != REV_11MPCORE) { 1064 /* For uniprocessor GICs these RAZ/WI */ 1065 res = 0; 1066 } else { 1067 irq = (offset - 0x800); 1068 if (irq >= s->num_irq) { 1069 goto bad_reg; 1070 } 1071 if (irq < 29 && s->revision == REV_11MPCORE) { 1072 res = 0; 1073 } else if (irq < GIC_INTERNAL) { 1074 res = cm; 1075 } else { 1076 res = GIC_DIST_TARGET(irq); 1077 } 1078 } 1079 } else if (offset < 0xf00) { 1080 /* Interrupt Configuration. */ 1081 irq = (offset - 0xc00) * 4; 1082 if (irq >= s->num_irq) 1083 goto bad_reg; 1084 res = 0; 1085 for (i = 0; i < 4; i++) { 1086 if (s->security_extn && !attrs.secure && 1087 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 1088 continue; /* Ignore Non-secure access of Group0 IRQ */ 1089 } 1090 1091 if (GIC_DIST_TEST_MODEL(irq + i)) { 1092 res |= (1 << (i * 2)); 1093 } 1094 if (GIC_DIST_TEST_EDGE_TRIGGER(irq + i)) { 1095 res |= (2 << (i * 2)); 1096 } 1097 } 1098 } else if (offset < 0xf10) { 1099 goto bad_reg; 1100 } else if (offset < 0xf30) { 1101 if (s->revision == REV_11MPCORE) { 1102 goto bad_reg; 1103 } 1104 1105 if (offset < 0xf20) { 1106 /* GICD_CPENDSGIRn */ 1107 irq = (offset - 0xf10); 1108 } else { 1109 irq = (offset - 0xf20); 1110 /* GICD_SPENDSGIRn */ 1111 } 1112 1113 if (s->security_extn && !attrs.secure && 1114 !GIC_DIST_TEST_GROUP(irq, 1 << cpu)) { 1115 res = 0; /* Ignore Non-secure access of Group0 IRQ */ 1116 } else { 1117 res = s->sgi_pending[irq][cpu]; 1118 } 1119 } else if (offset < 0xfd0) { 1120 goto bad_reg; 1121 } else if (offset < 0x1000) { 1122 if (offset & 3) { 1123 res = 0; 1124 } else { 1125 switch (s->revision) { 1126 case REV_11MPCORE: 1127 res = gic_id_11mpcore[(offset - 0xfd0) >> 2]; 1128 break; 1129 case 1: 1130 res = gic_id_gicv1[(offset - 0xfd0) >> 2]; 1131 break; 1132 case 2: 1133 res = gic_id_gicv2[(offset - 0xfd0) >> 2]; 1134 break; 1135 default: 1136 res = 0; 1137 } 1138 } 1139 } else { 1140 g_assert_not_reached(); 1141 } 1142 return res; 1143 bad_reg: 1144 qemu_log_mask(LOG_GUEST_ERROR, 1145 "gic_dist_readb: Bad offset %x\n", (int)offset); 1146 return 0; 1147 } 1148 1149 static MemTxResult gic_dist_read(void *opaque, hwaddr offset, uint64_t *data, 1150 unsigned size, MemTxAttrs attrs) 1151 { 1152 switch (size) { 1153 case 1: 1154 *data = gic_dist_readb(opaque, offset, attrs); 1155 break; 1156 case 2: 1157 *data = gic_dist_readb(opaque, offset, attrs); 1158 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 1159 break; 1160 case 4: 1161 *data = gic_dist_readb(opaque, offset, attrs); 1162 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 1163 *data |= gic_dist_readb(opaque, offset + 2, attrs) << 16; 1164 *data |= gic_dist_readb(opaque, offset + 3, attrs) << 24; 1165 break; 1166 default: 1167 return MEMTX_ERROR; 1168 } 1169 1170 trace_gic_dist_read(offset, size, *data); 1171 return MEMTX_OK; 1172 } 1173 1174 static void gic_dist_writeb(void *opaque, hwaddr offset, 1175 uint32_t value, MemTxAttrs attrs) 1176 { 1177 GICState *s = (GICState *)opaque; 1178 int irq; 1179 int i; 1180 int cpu; 1181 1182 cpu = gic_get_current_cpu(s); 1183 if (offset < 0x100) { 1184 if (offset == 0) { 1185 if (s->security_extn && !attrs.secure) { 1186 /* NS version is just an alias of the S version's bit 1 */ 1187 s->ctlr = deposit32(s->ctlr, 1, 1, value); 1188 } else if (gic_has_groups(s)) { 1189 s->ctlr = value & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1); 1190 } else { 1191 s->ctlr = value & GICD_CTLR_EN_GRP0; 1192 } 1193 DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n", 1194 s->ctlr & GICD_CTLR_EN_GRP0 ? "En" : "Dis", 1195 s->ctlr & GICD_CTLR_EN_GRP1 ? "En" : "Dis"); 1196 } else if (offset < 4) { 1197 /* ignored. */ 1198 } else if (offset >= 0x80) { 1199 /* Interrupt Group Registers: RAZ/WI for NS access to secure 1200 * GIC, or for GICs without groups. 1201 */ 1202 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 1203 /* Every byte offset holds 8 group status bits */ 1204 irq = (offset - 0x80) * 8; 1205 if (irq >= s->num_irq) { 1206 goto bad_reg; 1207 } 1208 for (i = 0; i < 8; i++) { 1209 /* Group bits are banked for private interrupts */ 1210 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 1211 if (value & (1 << i)) { 1212 /* Group1 (Non-secure) */ 1213 GIC_DIST_SET_GROUP(irq + i, cm); 1214 } else { 1215 /* Group0 (Secure) */ 1216 GIC_DIST_CLEAR_GROUP(irq + i, cm); 1217 } 1218 } 1219 } 1220 } else { 1221 goto bad_reg; 1222 } 1223 } else if (offset < 0x180) { 1224 /* Interrupt Set Enable. */ 1225 irq = (offset - 0x100) * 8; 1226 if (irq >= s->num_irq) 1227 goto bad_reg; 1228 if (irq < GIC_NR_SGIS) { 1229 value = 0xff; 1230 } 1231 1232 for (i = 0; i < 8; i++) { 1233 if (value & (1 << i)) { 1234 int mask = 1235 (irq < GIC_INTERNAL) ? (1 << cpu) 1236 : GIC_DIST_TARGET(irq + i); 1237 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 1238 1239 if (s->security_extn && !attrs.secure && 1240 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 1241 continue; /* Ignore Non-secure access of Group0 IRQ */ 1242 } 1243 1244 if (!GIC_DIST_TEST_ENABLED(irq + i, cm)) { 1245 DPRINTF("Enabled IRQ %d\n", irq + i); 1246 trace_gic_enable_irq(irq + i); 1247 } 1248 GIC_DIST_SET_ENABLED(irq + i, cm); 1249 /* If a raised level triggered IRQ enabled then mark 1250 is as pending. */ 1251 if (GIC_DIST_TEST_LEVEL(irq + i, mask) 1252 && !GIC_DIST_TEST_EDGE_TRIGGER(irq + i)) { 1253 DPRINTF("Set %d pending mask %x\n", irq + i, mask); 1254 GIC_DIST_SET_PENDING(irq + i, mask); 1255 } 1256 } 1257 } 1258 } else if (offset < 0x200) { 1259 /* Interrupt Clear Enable. */ 1260 irq = (offset - 0x180) * 8; 1261 if (irq >= s->num_irq) 1262 goto bad_reg; 1263 if (irq < GIC_NR_SGIS) { 1264 value = 0; 1265 } 1266 1267 for (i = 0; i < 8; i++) { 1268 if (value & (1 << i)) { 1269 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 1270 1271 if (s->security_extn && !attrs.secure && 1272 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 1273 continue; /* Ignore Non-secure access of Group0 IRQ */ 1274 } 1275 1276 if (GIC_DIST_TEST_ENABLED(irq + i, cm)) { 1277 DPRINTF("Disabled IRQ %d\n", irq + i); 1278 trace_gic_disable_irq(irq + i); 1279 } 1280 GIC_DIST_CLEAR_ENABLED(irq + i, cm); 1281 } 1282 } 1283 } else if (offset < 0x280) { 1284 /* Interrupt Set Pending. */ 1285 irq = (offset - 0x200) * 8; 1286 if (irq >= s->num_irq) 1287 goto bad_reg; 1288 if (irq < GIC_NR_SGIS) { 1289 value = 0; 1290 } 1291 1292 for (i = 0; i < 8; i++) { 1293 if (value & (1 << i)) { 1294 if (s->security_extn && !attrs.secure && 1295 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 1296 continue; /* Ignore Non-secure access of Group0 IRQ */ 1297 } 1298 1299 GIC_DIST_SET_PENDING(irq + i, GIC_DIST_TARGET(irq + i)); 1300 } 1301 } 1302 } else if (offset < 0x300) { 1303 /* Interrupt Clear Pending. */ 1304 irq = (offset - 0x280) * 8; 1305 if (irq >= s->num_irq) 1306 goto bad_reg; 1307 if (irq < GIC_NR_SGIS) { 1308 value = 0; 1309 } 1310 1311 for (i = 0; i < 8; i++) { 1312 if (s->security_extn && !attrs.secure && 1313 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 1314 continue; /* Ignore Non-secure access of Group0 IRQ */ 1315 } 1316 1317 /* ??? This currently clears the pending bit for all CPUs, even 1318 for per-CPU interrupts. It's unclear whether this is the 1319 corect behavior. */ 1320 if (value & (1 << i)) { 1321 GIC_DIST_CLEAR_PENDING(irq + i, ALL_CPU_MASK); 1322 } 1323 } 1324 } else if (offset < 0x380) { 1325 /* Interrupt Set Active. */ 1326 if (s->revision != 2) { 1327 goto bad_reg; 1328 } 1329 1330 irq = (offset - 0x300) * 8; 1331 if (irq >= s->num_irq) { 1332 goto bad_reg; 1333 } 1334 1335 /* This register is banked per-cpu for PPIs */ 1336 int cm = irq < GIC_INTERNAL ? (1 << cpu) : ALL_CPU_MASK; 1337 1338 for (i = 0; i < 8; i++) { 1339 if (s->security_extn && !attrs.secure && 1340 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 1341 continue; /* Ignore Non-secure access of Group0 IRQ */ 1342 } 1343 1344 if (value & (1 << i)) { 1345 GIC_DIST_SET_ACTIVE(irq + i, cm); 1346 } 1347 } 1348 } else if (offset < 0x400) { 1349 /* Interrupt Clear Active. */ 1350 if (s->revision != 2) { 1351 goto bad_reg; 1352 } 1353 1354 irq = (offset - 0x380) * 8; 1355 if (irq >= s->num_irq) { 1356 goto bad_reg; 1357 } 1358 1359 /* This register is banked per-cpu for PPIs */ 1360 int cm = irq < GIC_INTERNAL ? (1 << cpu) : ALL_CPU_MASK; 1361 1362 for (i = 0; i < 8; i++) { 1363 if (s->security_extn && !attrs.secure && 1364 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 1365 continue; /* Ignore Non-secure access of Group0 IRQ */ 1366 } 1367 1368 if (value & (1 << i)) { 1369 GIC_DIST_CLEAR_ACTIVE(irq + i, cm); 1370 } 1371 } 1372 } else if (offset < 0x800) { 1373 /* Interrupt Priority. */ 1374 irq = (offset - 0x400); 1375 if (irq >= s->num_irq) 1376 goto bad_reg; 1377 gic_dist_set_priority(s, cpu, irq, value, attrs); 1378 } else if (offset < 0xc00) { 1379 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the 1380 * annoying exception of the 11MPCore's GIC. 1381 */ 1382 if (s->num_cpu != 1 || s->revision == REV_11MPCORE) { 1383 irq = (offset - 0x800); 1384 if (irq >= s->num_irq) { 1385 goto bad_reg; 1386 } 1387 if (irq < 29 && s->revision == REV_11MPCORE) { 1388 value = 0; 1389 } else if (irq < GIC_INTERNAL) { 1390 value = ALL_CPU_MASK; 1391 } 1392 s->irq_target[irq] = value & ALL_CPU_MASK; 1393 } 1394 } else if (offset < 0xf00) { 1395 /* Interrupt Configuration. */ 1396 irq = (offset - 0xc00) * 4; 1397 if (irq >= s->num_irq) 1398 goto bad_reg; 1399 if (irq < GIC_NR_SGIS) 1400 value |= 0xaa; 1401 for (i = 0; i < 4; i++) { 1402 if (s->security_extn && !attrs.secure && 1403 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 1404 continue; /* Ignore Non-secure access of Group0 IRQ */ 1405 } 1406 1407 if (s->revision == REV_11MPCORE) { 1408 if (value & (1 << (i * 2))) { 1409 GIC_DIST_SET_MODEL(irq + i); 1410 } else { 1411 GIC_DIST_CLEAR_MODEL(irq + i); 1412 } 1413 } 1414 if (value & (2 << (i * 2))) { 1415 GIC_DIST_SET_EDGE_TRIGGER(irq + i); 1416 } else { 1417 GIC_DIST_CLEAR_EDGE_TRIGGER(irq + i); 1418 } 1419 } 1420 } else if (offset < 0xf10) { 1421 /* 0xf00 is only handled for 32-bit writes. */ 1422 goto bad_reg; 1423 } else if (offset < 0xf20) { 1424 /* GICD_CPENDSGIRn */ 1425 if (s->revision == REV_11MPCORE) { 1426 goto bad_reg; 1427 } 1428 irq = (offset - 0xf10); 1429 1430 if (!s->security_extn || attrs.secure || 1431 GIC_DIST_TEST_GROUP(irq, 1 << cpu)) { 1432 s->sgi_pending[irq][cpu] &= ~value; 1433 if (s->sgi_pending[irq][cpu] == 0) { 1434 GIC_DIST_CLEAR_PENDING(irq, 1 << cpu); 1435 } 1436 } 1437 } else if (offset < 0xf30) { 1438 /* GICD_SPENDSGIRn */ 1439 if (s->revision == REV_11MPCORE) { 1440 goto bad_reg; 1441 } 1442 irq = (offset - 0xf20); 1443 1444 if (!s->security_extn || attrs.secure || 1445 GIC_DIST_TEST_GROUP(irq, 1 << cpu)) { 1446 GIC_DIST_SET_PENDING(irq, 1 << cpu); 1447 s->sgi_pending[irq][cpu] |= value; 1448 } 1449 } else { 1450 goto bad_reg; 1451 } 1452 gic_update(s); 1453 return; 1454 bad_reg: 1455 qemu_log_mask(LOG_GUEST_ERROR, 1456 "gic_dist_writeb: Bad offset %x\n", (int)offset); 1457 } 1458 1459 static void gic_dist_writew(void *opaque, hwaddr offset, 1460 uint32_t value, MemTxAttrs attrs) 1461 { 1462 gic_dist_writeb(opaque, offset, value & 0xff, attrs); 1463 gic_dist_writeb(opaque, offset + 1, value >> 8, attrs); 1464 } 1465 1466 static void gic_dist_writel(void *opaque, hwaddr offset, 1467 uint32_t value, MemTxAttrs attrs) 1468 { 1469 GICState *s = (GICState *)opaque; 1470 if (offset == 0xf00) { 1471 int cpu; 1472 int irq; 1473 int mask; 1474 int target_cpu; 1475 1476 cpu = gic_get_current_cpu(s); 1477 irq = value & 0x3ff; 1478 switch ((value >> 24) & 3) { 1479 case 0: 1480 mask = (value >> 16) & ALL_CPU_MASK; 1481 break; 1482 case 1: 1483 mask = ALL_CPU_MASK ^ (1 << cpu); 1484 break; 1485 case 2: 1486 mask = 1 << cpu; 1487 break; 1488 default: 1489 DPRINTF("Bad Soft Int target filter\n"); 1490 mask = ALL_CPU_MASK; 1491 break; 1492 } 1493 GIC_DIST_SET_PENDING(irq, mask); 1494 target_cpu = ctz32(mask); 1495 while (target_cpu < GIC_NCPU) { 1496 s->sgi_pending[irq][target_cpu] |= (1 << cpu); 1497 mask &= ~(1 << target_cpu); 1498 target_cpu = ctz32(mask); 1499 } 1500 gic_update(s); 1501 return; 1502 } 1503 gic_dist_writew(opaque, offset, value & 0xffff, attrs); 1504 gic_dist_writew(opaque, offset + 2, value >> 16, attrs); 1505 } 1506 1507 static MemTxResult gic_dist_write(void *opaque, hwaddr offset, uint64_t data, 1508 unsigned size, MemTxAttrs attrs) 1509 { 1510 trace_gic_dist_write(offset, size, data); 1511 1512 switch (size) { 1513 case 1: 1514 gic_dist_writeb(opaque, offset, data, attrs); 1515 return MEMTX_OK; 1516 case 2: 1517 gic_dist_writew(opaque, offset, data, attrs); 1518 return MEMTX_OK; 1519 case 4: 1520 gic_dist_writel(opaque, offset, data, attrs); 1521 return MEMTX_OK; 1522 default: 1523 return MEMTX_ERROR; 1524 } 1525 } 1526 1527 static inline uint32_t gic_apr_ns_view(GICState *s, int cpu, int regno) 1528 { 1529 /* Return the Nonsecure view of GICC_APR<regno>. This is the 1530 * second half of GICC_NSAPR. 1531 */ 1532 switch (GIC_MIN_BPR) { 1533 case 0: 1534 if (regno < 2) { 1535 return s->nsapr[regno + 2][cpu]; 1536 } 1537 break; 1538 case 1: 1539 if (regno == 0) { 1540 return s->nsapr[regno + 1][cpu]; 1541 } 1542 break; 1543 case 2: 1544 if (regno == 0) { 1545 return extract32(s->nsapr[0][cpu], 16, 16); 1546 } 1547 break; 1548 case 3: 1549 if (regno == 0) { 1550 return extract32(s->nsapr[0][cpu], 8, 8); 1551 } 1552 break; 1553 default: 1554 g_assert_not_reached(); 1555 } 1556 return 0; 1557 } 1558 1559 static inline void gic_apr_write_ns_view(GICState *s, int cpu, int regno, 1560 uint32_t value) 1561 { 1562 /* Write the Nonsecure view of GICC_APR<regno>. */ 1563 switch (GIC_MIN_BPR) { 1564 case 0: 1565 if (regno < 2) { 1566 s->nsapr[regno + 2][cpu] = value; 1567 } 1568 break; 1569 case 1: 1570 if (regno == 0) { 1571 s->nsapr[regno + 1][cpu] = value; 1572 } 1573 break; 1574 case 2: 1575 if (regno == 0) { 1576 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 16, 16, value); 1577 } 1578 break; 1579 case 3: 1580 if (regno == 0) { 1581 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 8, 8, value); 1582 } 1583 break; 1584 default: 1585 g_assert_not_reached(); 1586 } 1587 } 1588 1589 static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset, 1590 uint64_t *data, MemTxAttrs attrs) 1591 { 1592 switch (offset) { 1593 case 0x00: /* Control */ 1594 *data = gic_get_cpu_control(s, cpu, attrs); 1595 break; 1596 case 0x04: /* Priority mask */ 1597 *data = gic_get_priority_mask(s, cpu, attrs); 1598 break; 1599 case 0x08: /* Binary Point */ 1600 if (gic_cpu_ns_access(s, cpu, attrs)) { 1601 if (s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) { 1602 /* NS view of BPR when CBPR is 1 */ 1603 *data = MIN(s->bpr[cpu] + 1, 7); 1604 } else { 1605 /* BPR is banked. Non-secure copy stored in ABPR. */ 1606 *data = s->abpr[cpu]; 1607 } 1608 } else { 1609 *data = s->bpr[cpu]; 1610 } 1611 break; 1612 case 0x0c: /* Acknowledge */ 1613 *data = gic_acknowledge_irq(s, cpu, attrs); 1614 break; 1615 case 0x14: /* Running Priority */ 1616 *data = gic_get_running_priority(s, cpu, attrs); 1617 break; 1618 case 0x18: /* Highest Pending Interrupt */ 1619 *data = gic_get_current_pending_irq(s, cpu, attrs); 1620 break; 1621 case 0x1c: /* Aliased Binary Point */ 1622 /* GIC v2, no security: ABPR 1623 * GIC v1, no security: not implemented (RAZ/WI) 1624 * With security extensions, secure access: ABPR (alias of NS BPR) 1625 * With security extensions, nonsecure access: RAZ/WI 1626 */ 1627 if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) { 1628 *data = 0; 1629 } else { 1630 *data = s->abpr[cpu]; 1631 } 1632 break; 1633 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 1634 { 1635 int regno = (offset - 0xd0) / 4; 1636 int nr_aprs = gic_is_vcpu(cpu) ? GIC_VIRT_NR_APRS : GIC_NR_APRS; 1637 1638 if (regno >= nr_aprs || s->revision != 2) { 1639 *data = 0; 1640 } else if (gic_is_vcpu(cpu)) { 1641 *data = s->h_apr[gic_get_vcpu_real_id(cpu)]; 1642 } else if (gic_cpu_ns_access(s, cpu, attrs)) { 1643 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ 1644 *data = gic_apr_ns_view(s, regno, cpu); 1645 } else { 1646 *data = s->apr[regno][cpu]; 1647 } 1648 break; 1649 } 1650 case 0xe0: case 0xe4: case 0xe8: case 0xec: 1651 { 1652 int regno = (offset - 0xe0) / 4; 1653 1654 if (regno >= GIC_NR_APRS || s->revision != 2 || !gic_has_groups(s) || 1655 gic_cpu_ns_access(s, cpu, attrs) || gic_is_vcpu(cpu)) { 1656 *data = 0; 1657 } else { 1658 *data = s->nsapr[regno][cpu]; 1659 } 1660 break; 1661 } 1662 default: 1663 qemu_log_mask(LOG_GUEST_ERROR, 1664 "gic_cpu_read: Bad offset %x\n", (int)offset); 1665 *data = 0; 1666 break; 1667 } 1668 1669 trace_gic_cpu_read(gic_is_vcpu(cpu) ? "vcpu" : "cpu", 1670 gic_get_vcpu_real_id(cpu), offset, *data); 1671 return MEMTX_OK; 1672 } 1673 1674 static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset, 1675 uint32_t value, MemTxAttrs attrs) 1676 { 1677 trace_gic_cpu_write(gic_is_vcpu(cpu) ? "vcpu" : "cpu", 1678 gic_get_vcpu_real_id(cpu), offset, value); 1679 1680 switch (offset) { 1681 case 0x00: /* Control */ 1682 gic_set_cpu_control(s, cpu, value, attrs); 1683 break; 1684 case 0x04: /* Priority mask */ 1685 gic_set_priority_mask(s, cpu, value, attrs); 1686 break; 1687 case 0x08: /* Binary Point */ 1688 if (gic_cpu_ns_access(s, cpu, attrs)) { 1689 if (s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) { 1690 /* WI when CBPR is 1 */ 1691 return MEMTX_OK; 1692 } else { 1693 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 1694 } 1695 } else { 1696 int min_bpr = gic_is_vcpu(cpu) ? GIC_VIRT_MIN_BPR : GIC_MIN_BPR; 1697 s->bpr[cpu] = MAX(value & 0x7, min_bpr); 1698 } 1699 break; 1700 case 0x10: /* End Of Interrupt */ 1701 gic_complete_irq(s, cpu, value & 0x3ff, attrs); 1702 return MEMTX_OK; 1703 case 0x1c: /* Aliased Binary Point */ 1704 if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) { 1705 /* unimplemented, or NS access: RAZ/WI */ 1706 return MEMTX_OK; 1707 } else { 1708 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 1709 } 1710 break; 1711 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 1712 { 1713 int regno = (offset - 0xd0) / 4; 1714 int nr_aprs = gic_is_vcpu(cpu) ? GIC_VIRT_NR_APRS : GIC_NR_APRS; 1715 1716 if (regno >= nr_aprs || s->revision != 2) { 1717 return MEMTX_OK; 1718 } 1719 if (gic_is_vcpu(cpu)) { 1720 s->h_apr[gic_get_vcpu_real_id(cpu)] = value; 1721 } else if (gic_cpu_ns_access(s, cpu, attrs)) { 1722 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ 1723 gic_apr_write_ns_view(s, regno, cpu, value); 1724 } else { 1725 s->apr[regno][cpu] = value; 1726 } 1727 break; 1728 } 1729 case 0xe0: case 0xe4: case 0xe8: case 0xec: 1730 { 1731 int regno = (offset - 0xe0) / 4; 1732 1733 if (regno >= GIC_NR_APRS || s->revision != 2) { 1734 return MEMTX_OK; 1735 } 1736 if (gic_is_vcpu(cpu)) { 1737 return MEMTX_OK; 1738 } 1739 if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) { 1740 return MEMTX_OK; 1741 } 1742 s->nsapr[regno][cpu] = value; 1743 break; 1744 } 1745 case 0x1000: 1746 /* GICC_DIR */ 1747 gic_deactivate_irq(s, cpu, value & 0x3ff, attrs); 1748 break; 1749 default: 1750 qemu_log_mask(LOG_GUEST_ERROR, 1751 "gic_cpu_write: Bad offset %x\n", (int)offset); 1752 return MEMTX_OK; 1753 } 1754 1755 if (gic_is_vcpu(cpu)) { 1756 gic_update_virt(s); 1757 } else { 1758 gic_update(s); 1759 } 1760 1761 return MEMTX_OK; 1762 } 1763 1764 /* Wrappers to read/write the GIC CPU interface for the current CPU */ 1765 static MemTxResult gic_thiscpu_read(void *opaque, hwaddr addr, uint64_t *data, 1766 unsigned size, MemTxAttrs attrs) 1767 { 1768 GICState *s = (GICState *)opaque; 1769 return gic_cpu_read(s, gic_get_current_cpu(s), addr, data, attrs); 1770 } 1771 1772 static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, 1773 uint64_t value, unsigned size, 1774 MemTxAttrs attrs) 1775 { 1776 GICState *s = (GICState *)opaque; 1777 return gic_cpu_write(s, gic_get_current_cpu(s), addr, value, attrs); 1778 } 1779 1780 /* Wrappers to read/write the GIC CPU interface for a specific CPU. 1781 * These just decode the opaque pointer into GICState* + cpu id. 1782 */ 1783 static MemTxResult gic_do_cpu_read(void *opaque, hwaddr addr, uint64_t *data, 1784 unsigned size, MemTxAttrs attrs) 1785 { 1786 GICState **backref = (GICState **)opaque; 1787 GICState *s = *backref; 1788 int id = (backref - s->backref); 1789 return gic_cpu_read(s, id, addr, data, attrs); 1790 } 1791 1792 static MemTxResult gic_do_cpu_write(void *opaque, hwaddr addr, 1793 uint64_t value, unsigned size, 1794 MemTxAttrs attrs) 1795 { 1796 GICState **backref = (GICState **)opaque; 1797 GICState *s = *backref; 1798 int id = (backref - s->backref); 1799 return gic_cpu_write(s, id, addr, value, attrs); 1800 } 1801 1802 static MemTxResult gic_thisvcpu_read(void *opaque, hwaddr addr, uint64_t *data, 1803 unsigned size, MemTxAttrs attrs) 1804 { 1805 GICState *s = (GICState *)opaque; 1806 1807 return gic_cpu_read(s, gic_get_current_vcpu(s), addr, data, attrs); 1808 } 1809 1810 static MemTxResult gic_thisvcpu_write(void *opaque, hwaddr addr, 1811 uint64_t value, unsigned size, 1812 MemTxAttrs attrs) 1813 { 1814 GICState *s = (GICState *)opaque; 1815 1816 return gic_cpu_write(s, gic_get_current_vcpu(s), addr, value, attrs); 1817 } 1818 1819 static uint32_t gic_compute_eisr(GICState *s, int cpu, int lr_start) 1820 { 1821 int lr_idx; 1822 uint32_t ret = 0; 1823 1824 for (lr_idx = lr_start; lr_idx < s->num_lrs; lr_idx++) { 1825 uint32_t *entry = &s->h_lr[lr_idx][cpu]; 1826 ret = deposit32(ret, lr_idx - lr_start, 1, 1827 gic_lr_entry_is_eoi(*entry)); 1828 } 1829 1830 return ret; 1831 } 1832 1833 static uint32_t gic_compute_elrsr(GICState *s, int cpu, int lr_start) 1834 { 1835 int lr_idx; 1836 uint32_t ret = 0; 1837 1838 for (lr_idx = lr_start; lr_idx < s->num_lrs; lr_idx++) { 1839 uint32_t *entry = &s->h_lr[lr_idx][cpu]; 1840 ret = deposit32(ret, lr_idx - lr_start, 1, 1841 gic_lr_entry_is_free(*entry)); 1842 } 1843 1844 return ret; 1845 } 1846 1847 static void gic_vmcr_write(GICState *s, uint32_t value, MemTxAttrs attrs) 1848 { 1849 int vcpu = gic_get_current_vcpu(s); 1850 uint32_t ctlr; 1851 uint32_t abpr; 1852 uint32_t bpr; 1853 uint32_t prio_mask; 1854 1855 ctlr = FIELD_EX32(value, GICH_VMCR, VMCCtlr); 1856 abpr = FIELD_EX32(value, GICH_VMCR, VMABP); 1857 bpr = FIELD_EX32(value, GICH_VMCR, VMBP); 1858 prio_mask = FIELD_EX32(value, GICH_VMCR, VMPriMask) << 3; 1859 1860 gic_set_cpu_control(s, vcpu, ctlr, attrs); 1861 s->abpr[vcpu] = MAX(abpr, GIC_VIRT_MIN_ABPR); 1862 s->bpr[vcpu] = MAX(bpr, GIC_VIRT_MIN_BPR); 1863 gic_set_priority_mask(s, vcpu, prio_mask, attrs); 1864 } 1865 1866 static MemTxResult gic_hyp_read(void *opaque, int cpu, hwaddr addr, 1867 uint64_t *data, MemTxAttrs attrs) 1868 { 1869 GICState *s = ARM_GIC(opaque); 1870 int vcpu = cpu + GIC_NCPU; 1871 1872 switch (addr) { 1873 case A_GICH_HCR: /* Hypervisor Control */ 1874 *data = s->h_hcr[cpu]; 1875 break; 1876 1877 case A_GICH_VTR: /* VGIC Type */ 1878 *data = FIELD_DP32(0, GICH_VTR, ListRegs, s->num_lrs - 1); 1879 *data = FIELD_DP32(*data, GICH_VTR, PREbits, 1880 GIC_VIRT_MAX_GROUP_PRIO_BITS - 1); 1881 *data = FIELD_DP32(*data, GICH_VTR, PRIbits, 1882 (7 - GIC_VIRT_MIN_BPR) - 1); 1883 break; 1884 1885 case A_GICH_VMCR: /* Virtual Machine Control */ 1886 *data = FIELD_DP32(0, GICH_VMCR, VMCCtlr, 1887 extract32(s->cpu_ctlr[vcpu], 0, 10)); 1888 *data = FIELD_DP32(*data, GICH_VMCR, VMABP, s->abpr[vcpu]); 1889 *data = FIELD_DP32(*data, GICH_VMCR, VMBP, s->bpr[vcpu]); 1890 *data = FIELD_DP32(*data, GICH_VMCR, VMPriMask, 1891 extract32(s->priority_mask[vcpu], 3, 5)); 1892 break; 1893 1894 case A_GICH_MISR: /* Maintenance Interrupt Status */ 1895 *data = s->h_misr[cpu]; 1896 break; 1897 1898 case A_GICH_EISR0: /* End of Interrupt Status 0 and 1 */ 1899 case A_GICH_EISR1: 1900 *data = gic_compute_eisr(s, cpu, (addr - A_GICH_EISR0) * 8); 1901 break; 1902 1903 case A_GICH_ELRSR0: /* Empty List Status 0 and 1 */ 1904 case A_GICH_ELRSR1: 1905 *data = gic_compute_elrsr(s, cpu, (addr - A_GICH_ELRSR0) * 8); 1906 break; 1907 1908 case A_GICH_APR: /* Active Priorities */ 1909 *data = s->h_apr[cpu]; 1910 break; 1911 1912 case A_GICH_LR0 ... A_GICH_LR63: /* List Registers */ 1913 { 1914 int lr_idx = (addr - A_GICH_LR0) / 4; 1915 1916 if (lr_idx > s->num_lrs) { 1917 *data = 0; 1918 } else { 1919 *data = s->h_lr[lr_idx][cpu]; 1920 } 1921 break; 1922 } 1923 1924 default: 1925 qemu_log_mask(LOG_GUEST_ERROR, 1926 "gic_hyp_read: Bad offset %" HWADDR_PRIx "\n", addr); 1927 return MEMTX_OK; 1928 } 1929 1930 trace_gic_hyp_read(addr, *data); 1931 return MEMTX_OK; 1932 } 1933 1934 static MemTxResult gic_hyp_write(void *opaque, int cpu, hwaddr addr, 1935 uint64_t value, MemTxAttrs attrs) 1936 { 1937 GICState *s = ARM_GIC(opaque); 1938 int vcpu = cpu + GIC_NCPU; 1939 1940 trace_gic_hyp_write(addr, value); 1941 1942 switch (addr) { 1943 case A_GICH_HCR: /* Hypervisor Control */ 1944 s->h_hcr[cpu] = value & GICH_HCR_MASK; 1945 break; 1946 1947 case A_GICH_VMCR: /* Virtual Machine Control */ 1948 gic_vmcr_write(s, value, attrs); 1949 break; 1950 1951 case A_GICH_APR: /* Active Priorities */ 1952 s->h_apr[cpu] = value; 1953 s->running_priority[vcpu] = gic_get_prio_from_apr_bits(s, vcpu); 1954 break; 1955 1956 case A_GICH_LR0 ... A_GICH_LR63: /* List Registers */ 1957 { 1958 int lr_idx = (addr - A_GICH_LR0) / 4; 1959 1960 if (lr_idx > s->num_lrs) { 1961 return MEMTX_OK; 1962 } 1963 1964 s->h_lr[lr_idx][cpu] = value & GICH_LR_MASK; 1965 trace_gic_lr_entry(cpu, lr_idx, s->h_lr[lr_idx][cpu]); 1966 break; 1967 } 1968 1969 default: 1970 qemu_log_mask(LOG_GUEST_ERROR, 1971 "gic_hyp_write: Bad offset %" HWADDR_PRIx "\n", addr); 1972 return MEMTX_OK; 1973 } 1974 1975 gic_update_virt(s); 1976 return MEMTX_OK; 1977 } 1978 1979 static MemTxResult gic_thiscpu_hyp_read(void *opaque, hwaddr addr, uint64_t *data, 1980 unsigned size, MemTxAttrs attrs) 1981 { 1982 GICState *s = (GICState *)opaque; 1983 1984 return gic_hyp_read(s, gic_get_current_cpu(s), addr, data, attrs); 1985 } 1986 1987 static MemTxResult gic_thiscpu_hyp_write(void *opaque, hwaddr addr, 1988 uint64_t value, unsigned size, 1989 MemTxAttrs attrs) 1990 { 1991 GICState *s = (GICState *)opaque; 1992 1993 return gic_hyp_write(s, gic_get_current_cpu(s), addr, value, attrs); 1994 } 1995 1996 static MemTxResult gic_do_hyp_read(void *opaque, hwaddr addr, uint64_t *data, 1997 unsigned size, MemTxAttrs attrs) 1998 { 1999 GICState **backref = (GICState **)opaque; 2000 GICState *s = *backref; 2001 int id = (backref - s->backref); 2002 2003 return gic_hyp_read(s, id, addr, data, attrs); 2004 } 2005 2006 static MemTxResult gic_do_hyp_write(void *opaque, hwaddr addr, 2007 uint64_t value, unsigned size, 2008 MemTxAttrs attrs) 2009 { 2010 GICState **backref = (GICState **)opaque; 2011 GICState *s = *backref; 2012 int id = (backref - s->backref); 2013 2014 return gic_hyp_write(s, id + GIC_NCPU, addr, value, attrs); 2015 2016 } 2017 2018 static const MemoryRegionOps gic_ops[2] = { 2019 { 2020 .read_with_attrs = gic_dist_read, 2021 .write_with_attrs = gic_dist_write, 2022 .endianness = DEVICE_NATIVE_ENDIAN, 2023 }, 2024 { 2025 .read_with_attrs = gic_thiscpu_read, 2026 .write_with_attrs = gic_thiscpu_write, 2027 .endianness = DEVICE_NATIVE_ENDIAN, 2028 } 2029 }; 2030 2031 static const MemoryRegionOps gic_cpu_ops = { 2032 .read_with_attrs = gic_do_cpu_read, 2033 .write_with_attrs = gic_do_cpu_write, 2034 .endianness = DEVICE_NATIVE_ENDIAN, 2035 }; 2036 2037 static const MemoryRegionOps gic_virt_ops[2] = { 2038 { 2039 .read_with_attrs = gic_thiscpu_hyp_read, 2040 .write_with_attrs = gic_thiscpu_hyp_write, 2041 .endianness = DEVICE_NATIVE_ENDIAN, 2042 }, 2043 { 2044 .read_with_attrs = gic_thisvcpu_read, 2045 .write_with_attrs = gic_thisvcpu_write, 2046 .endianness = DEVICE_NATIVE_ENDIAN, 2047 } 2048 }; 2049 2050 static const MemoryRegionOps gic_viface_ops = { 2051 .read_with_attrs = gic_do_hyp_read, 2052 .write_with_attrs = gic_do_hyp_write, 2053 .endianness = DEVICE_NATIVE_ENDIAN, 2054 }; 2055 2056 static void arm_gic_realize(DeviceState *dev, Error **errp) 2057 { 2058 /* Device instance realize function for the GIC sysbus device */ 2059 int i; 2060 GICState *s = ARM_GIC(dev); 2061 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 2062 ARMGICClass *agc = ARM_GIC_GET_CLASS(s); 2063 Error *local_err = NULL; 2064 2065 agc->parent_realize(dev, &local_err); 2066 if (local_err) { 2067 error_propagate(errp, local_err); 2068 return; 2069 } 2070 2071 if (kvm_enabled() && !kvm_arm_supports_user_irq()) { 2072 error_setg(errp, "KVM with user space irqchip only works when the " 2073 "host kernel supports KVM_CAP_ARM_USER_IRQ"); 2074 return; 2075 } 2076 2077 if (s->n_prio_bits > GIC_MAX_PRIORITY_BITS || 2078 (s->virt_extn ? s->n_prio_bits < GIC_VIRT_MAX_GROUP_PRIO_BITS : 2079 s->n_prio_bits < GIC_MIN_PRIORITY_BITS)) { 2080 error_setg(errp, "num-priority-bits cannot be greater than %d" 2081 " or less than %d", GIC_MAX_PRIORITY_BITS, 2082 s->virt_extn ? GIC_VIRT_MAX_GROUP_PRIO_BITS : 2083 GIC_MIN_PRIORITY_BITS); 2084 return; 2085 } 2086 2087 /* This creates distributor, main CPU interface (s->cpuiomem[0]) and if 2088 * enabled, virtualization extensions related interfaces (main virtual 2089 * interface (s->vifaceiomem[0]) and virtual CPU interface). 2090 */ 2091 gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops, gic_virt_ops); 2092 2093 /* Extra core-specific regions for the CPU interfaces. This is 2094 * necessary for "franken-GIC" implementations, for example on 2095 * Exynos 4. 2096 * NB that the memory region size of 0x100 applies for the 11MPCore 2097 * and also cores following the GIC v1 spec (ie A9). 2098 * GIC v2 defines a larger memory region (0x1000) so this will need 2099 * to be extended when we implement A15. 2100 */ 2101 for (i = 0; i < s->num_cpu; i++) { 2102 s->backref[i] = s; 2103 memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops, 2104 &s->backref[i], "gic_cpu", 0x100); 2105 sysbus_init_mmio(sbd, &s->cpuiomem[i+1]); 2106 } 2107 2108 /* Extra core-specific regions for virtual interfaces. This is required by 2109 * the GICv2 specification. 2110 */ 2111 if (s->virt_extn) { 2112 for (i = 0; i < s->num_cpu; i++) { 2113 memory_region_init_io(&s->vifaceiomem[i + 1], OBJECT(s), 2114 &gic_viface_ops, &s->backref[i], 2115 "gic_viface", 0x200); 2116 sysbus_init_mmio(sbd, &s->vifaceiomem[i + 1]); 2117 } 2118 } 2119 2120 } 2121 2122 static void arm_gic_class_init(ObjectClass *klass, void *data) 2123 { 2124 DeviceClass *dc = DEVICE_CLASS(klass); 2125 ARMGICClass *agc = ARM_GIC_CLASS(klass); 2126 2127 device_class_set_parent_realize(dc, arm_gic_realize, &agc->parent_realize); 2128 } 2129 2130 static const TypeInfo arm_gic_info = { 2131 .name = TYPE_ARM_GIC, 2132 .parent = TYPE_ARM_GIC_COMMON, 2133 .instance_size = sizeof(GICState), 2134 .class_init = arm_gic_class_init, 2135 .class_size = sizeof(ARMGICClass), 2136 }; 2137 2138 static void arm_gic_register_types(void) 2139 { 2140 type_register_static(&arm_gic_info); 2141 } 2142 2143 type_init(arm_gic_register_types) 2144