1 /* 2 * ARM Generic/Distributed Interrupt Controller 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 /* This file contains implementation code for the RealView EB interrupt 11 * controller, MPCore distributed interrupt controller and ARMv7-M 12 * Nested Vectored Interrupt Controller. 13 * It is compiled in two ways: 14 * (1) as a standalone file to produce a sysbus device which is a GIC 15 * that can be used on the realview board and as one of the builtin 16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc) 17 * (2) by being directly #included into armv7m_nvic.c to produce the 18 * armv7m_nvic device. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/sysbus.h" 23 #include "gic_internal.h" 24 #include "qapi/error.h" 25 #include "qom/cpu.h" 26 #include "qemu/log.h" 27 #include "trace.h" 28 #include "sysemu/kvm.h" 29 30 /* #define DEBUG_GIC */ 31 32 #ifdef DEBUG_GIC 33 #define DEBUG_GIC_GATE 1 34 #else 35 #define DEBUG_GIC_GATE 0 36 #endif 37 38 #define DPRINTF(fmt, ...) do { \ 39 if (DEBUG_GIC_GATE) { \ 40 fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \ 41 } \ 42 } while (0) 43 44 static const uint8_t gic_id_11mpcore[] = { 45 0x00, 0x00, 0x00, 0x00, 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 46 }; 47 48 static const uint8_t gic_id_gicv1[] = { 49 0x04, 0x00, 0x00, 0x00, 0x90, 0xb3, 0x1b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 50 }; 51 52 static const uint8_t gic_id_gicv2[] = { 53 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 54 }; 55 56 static inline int gic_get_current_cpu(GICState *s) 57 { 58 if (s->num_cpu > 1) { 59 return current_cpu->cpu_index; 60 } 61 return 0; 62 } 63 64 /* Return true if this GIC config has interrupt groups, which is 65 * true if we're a GICv2, or a GICv1 with the security extensions. 66 */ 67 static inline bool gic_has_groups(GICState *s) 68 { 69 return s->revision == 2 || s->security_extn; 70 } 71 72 /* TODO: Many places that call this routine could be optimized. */ 73 /* Update interrupt status after enabled or pending bits have been changed. */ 74 void gic_update(GICState *s) 75 { 76 int best_irq; 77 int best_prio; 78 int irq; 79 int irq_level, fiq_level; 80 int cpu; 81 int cm; 82 83 for (cpu = 0; cpu < s->num_cpu; cpu++) { 84 cm = 1 << cpu; 85 s->current_pending[cpu] = 1023; 86 if (!(s->ctlr & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1)) 87 || !(s->cpu_ctlr[cpu] & (GICC_CTLR_EN_GRP0 | GICC_CTLR_EN_GRP1))) { 88 qemu_irq_lower(s->parent_irq[cpu]); 89 qemu_irq_lower(s->parent_fiq[cpu]); 90 continue; 91 } 92 best_prio = 0x100; 93 best_irq = 1023; 94 for (irq = 0; irq < s->num_irq; irq++) { 95 if (GIC_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm) && 96 (!GIC_TEST_ACTIVE(irq, cm)) && 97 (irq < GIC_INTERNAL || GIC_TARGET(irq) & cm)) { 98 if (GIC_GET_PRIORITY(irq, cpu) < best_prio) { 99 best_prio = GIC_GET_PRIORITY(irq, cpu); 100 best_irq = irq; 101 } 102 } 103 } 104 105 if (best_irq != 1023) { 106 trace_gic_update_bestirq(cpu, best_irq, best_prio, 107 s->priority_mask[cpu], s->running_priority[cpu]); 108 } 109 110 irq_level = fiq_level = 0; 111 112 if (best_prio < s->priority_mask[cpu]) { 113 s->current_pending[cpu] = best_irq; 114 if (best_prio < s->running_priority[cpu]) { 115 int group = GIC_TEST_GROUP(best_irq, cm); 116 117 if (extract32(s->ctlr, group, 1) && 118 extract32(s->cpu_ctlr[cpu], group, 1)) { 119 if (group == 0 && s->cpu_ctlr[cpu] & GICC_CTLR_FIQ_EN) { 120 DPRINTF("Raised pending FIQ %d (cpu %d)\n", 121 best_irq, cpu); 122 fiq_level = 1; 123 trace_gic_update_set_irq(cpu, "fiq", fiq_level); 124 } else { 125 DPRINTF("Raised pending IRQ %d (cpu %d)\n", 126 best_irq, cpu); 127 irq_level = 1; 128 trace_gic_update_set_irq(cpu, "irq", irq_level); 129 } 130 } 131 } 132 } 133 134 qemu_set_irq(s->parent_irq[cpu], irq_level); 135 qemu_set_irq(s->parent_fiq[cpu], fiq_level); 136 } 137 } 138 139 void gic_set_pending_private(GICState *s, int cpu, int irq) 140 { 141 int cm = 1 << cpu; 142 143 if (gic_test_pending(s, irq, cm)) { 144 return; 145 } 146 147 DPRINTF("Set %d pending cpu %d\n", irq, cpu); 148 GIC_SET_PENDING(irq, cm); 149 gic_update(s); 150 } 151 152 static void gic_set_irq_11mpcore(GICState *s, int irq, int level, 153 int cm, int target) 154 { 155 if (level) { 156 GIC_SET_LEVEL(irq, cm); 157 if (GIC_TEST_EDGE_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) { 158 DPRINTF("Set %d pending mask %x\n", irq, target); 159 GIC_SET_PENDING(irq, target); 160 } 161 } else { 162 GIC_CLEAR_LEVEL(irq, cm); 163 } 164 } 165 166 static void gic_set_irq_generic(GICState *s, int irq, int level, 167 int cm, int target) 168 { 169 if (level) { 170 GIC_SET_LEVEL(irq, cm); 171 DPRINTF("Set %d pending mask %x\n", irq, target); 172 if (GIC_TEST_EDGE_TRIGGER(irq)) { 173 GIC_SET_PENDING(irq, target); 174 } 175 } else { 176 GIC_CLEAR_LEVEL(irq, cm); 177 } 178 } 179 180 /* Process a change in an external IRQ input. */ 181 static void gic_set_irq(void *opaque, int irq, int level) 182 { 183 /* Meaning of the 'irq' parameter: 184 * [0..N-1] : external interrupts 185 * [N..N+31] : PPI (internal) interrupts for CPU 0 186 * [N+32..N+63] : PPI (internal interrupts for CPU 1 187 * ... 188 */ 189 GICState *s = (GICState *)opaque; 190 int cm, target; 191 if (irq < (s->num_irq - GIC_INTERNAL)) { 192 /* The first external input line is internal interrupt 32. */ 193 cm = ALL_CPU_MASK; 194 irq += GIC_INTERNAL; 195 target = GIC_TARGET(irq); 196 } else { 197 int cpu; 198 irq -= (s->num_irq - GIC_INTERNAL); 199 cpu = irq / GIC_INTERNAL; 200 irq %= GIC_INTERNAL; 201 cm = 1 << cpu; 202 target = cm; 203 } 204 205 assert(irq >= GIC_NR_SGIS); 206 207 if (level == GIC_TEST_LEVEL(irq, cm)) { 208 return; 209 } 210 211 if (s->revision == REV_11MPCORE) { 212 gic_set_irq_11mpcore(s, irq, level, cm, target); 213 } else { 214 gic_set_irq_generic(s, irq, level, cm, target); 215 } 216 trace_gic_set_irq(irq, level, cm, target); 217 218 gic_update(s); 219 } 220 221 static uint16_t gic_get_current_pending_irq(GICState *s, int cpu, 222 MemTxAttrs attrs) 223 { 224 uint16_t pending_irq = s->current_pending[cpu]; 225 226 if (pending_irq < GIC_MAXIRQ && gic_has_groups(s)) { 227 int group = GIC_TEST_GROUP(pending_irq, (1 << cpu)); 228 /* On a GIC without the security extensions, reading this register 229 * behaves in the same way as a secure access to a GIC with them. 230 */ 231 bool secure = !s->security_extn || attrs.secure; 232 233 if (group == 0 && !secure) { 234 /* Group0 interrupts hidden from Non-secure access */ 235 return 1023; 236 } 237 if (group == 1 && secure && !(s->cpu_ctlr[cpu] & GICC_CTLR_ACK_CTL)) { 238 /* Group1 interrupts only seen by Secure access if 239 * AckCtl bit set. 240 */ 241 return 1022; 242 } 243 } 244 return pending_irq; 245 } 246 247 static int gic_get_group_priority(GICState *s, int cpu, int irq) 248 { 249 /* Return the group priority of the specified interrupt 250 * (which is the top bits of its priority, with the number 251 * of bits masked determined by the applicable binary point register). 252 */ 253 int bpr; 254 uint32_t mask; 255 256 if (gic_has_groups(s) && 257 !(s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) && 258 GIC_TEST_GROUP(irq, (1 << cpu))) { 259 bpr = s->abpr[cpu] - 1; 260 assert(bpr >= 0); 261 } else { 262 bpr = s->bpr[cpu]; 263 } 264 265 /* a BPR of 0 means the group priority bits are [7:1]; 266 * a BPR of 1 means they are [7:2], and so on down to 267 * a BPR of 7 meaning no group priority bits at all. 268 */ 269 mask = ~0U << ((bpr & 7) + 1); 270 271 return GIC_GET_PRIORITY(irq, cpu) & mask; 272 } 273 274 static void gic_activate_irq(GICState *s, int cpu, int irq) 275 { 276 /* Set the appropriate Active Priority Register bit for this IRQ, 277 * and update the running priority. 278 */ 279 int prio = gic_get_group_priority(s, cpu, irq); 280 int preemption_level = prio >> (GIC_MIN_BPR + 1); 281 int regno = preemption_level / 32; 282 int bitno = preemption_level % 32; 283 284 if (gic_has_groups(s) && GIC_TEST_GROUP(irq, (1 << cpu))) { 285 s->nsapr[regno][cpu] |= (1 << bitno); 286 } else { 287 s->apr[regno][cpu] |= (1 << bitno); 288 } 289 290 s->running_priority[cpu] = prio; 291 GIC_SET_ACTIVE(irq, 1 << cpu); 292 } 293 294 static int gic_get_prio_from_apr_bits(GICState *s, int cpu) 295 { 296 /* Recalculate the current running priority for this CPU based 297 * on the set bits in the Active Priority Registers. 298 */ 299 int i; 300 for (i = 0; i < GIC_NR_APRS; i++) { 301 uint32_t apr = s->apr[i][cpu] | s->nsapr[i][cpu]; 302 if (!apr) { 303 continue; 304 } 305 return (i * 32 + ctz32(apr)) << (GIC_MIN_BPR + 1); 306 } 307 return 0x100; 308 } 309 310 static void gic_drop_prio(GICState *s, int cpu, int group) 311 { 312 /* Drop the priority of the currently active interrupt in the 313 * specified group. 314 * 315 * Note that we can guarantee (because of the requirement to nest 316 * GICC_IAR reads [which activate an interrupt and raise priority] 317 * with GICC_EOIR writes [which drop the priority for the interrupt]) 318 * that the interrupt we're being called for is the highest priority 319 * active interrupt, meaning that it has the lowest set bit in the 320 * APR registers. 321 * 322 * If the guest does not honour the ordering constraints then the 323 * behaviour of the GIC is UNPREDICTABLE, which for us means that 324 * the values of the APR registers might become incorrect and the 325 * running priority will be wrong, so interrupts that should preempt 326 * might not do so, and interrupts that should not preempt might do so. 327 */ 328 int i; 329 330 for (i = 0; i < GIC_NR_APRS; i++) { 331 uint32_t *papr = group ? &s->nsapr[i][cpu] : &s->apr[i][cpu]; 332 if (!*papr) { 333 continue; 334 } 335 /* Clear lowest set bit */ 336 *papr &= *papr - 1; 337 break; 338 } 339 340 s->running_priority[cpu] = gic_get_prio_from_apr_bits(s, cpu); 341 } 342 343 uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs) 344 { 345 int ret, irq, src; 346 int cm = 1 << cpu; 347 348 /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately 349 * for the case where this GIC supports grouping and the pending interrupt 350 * is in the wrong group. 351 */ 352 irq = gic_get_current_pending_irq(s, cpu, attrs); 353 trace_gic_acknowledge_irq(cpu, irq); 354 355 if (irq >= GIC_MAXIRQ) { 356 DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq); 357 return irq; 358 } 359 360 if (GIC_GET_PRIORITY(irq, cpu) >= s->running_priority[cpu]) { 361 DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq); 362 return 1023; 363 } 364 365 if (s->revision == REV_11MPCORE) { 366 /* Clear pending flags for both level and edge triggered interrupts. 367 * Level triggered IRQs will be reasserted once they become inactive. 368 */ 369 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 370 ret = irq; 371 } else { 372 if (irq < GIC_NR_SGIS) { 373 /* Lookup the source CPU for the SGI and clear this in the 374 * sgi_pending map. Return the src and clear the overall pending 375 * state on this CPU if the SGI is not pending from any CPUs. 376 */ 377 assert(s->sgi_pending[irq][cpu] != 0); 378 src = ctz32(s->sgi_pending[irq][cpu]); 379 s->sgi_pending[irq][cpu] &= ~(1 << src); 380 if (s->sgi_pending[irq][cpu] == 0) { 381 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 382 } 383 ret = irq | ((src & 0x7) << 10); 384 } else { 385 /* Clear pending state for both level and edge triggered 386 * interrupts. (level triggered interrupts with an active line 387 * remain pending, see gic_test_pending) 388 */ 389 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 390 ret = irq; 391 } 392 } 393 394 gic_activate_irq(s, cpu, irq); 395 gic_update(s); 396 DPRINTF("ACK %d\n", irq); 397 return ret; 398 } 399 400 void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val, 401 MemTxAttrs attrs) 402 { 403 if (s->security_extn && !attrs.secure) { 404 if (!GIC_TEST_GROUP(irq, (1 << cpu))) { 405 return; /* Ignore Non-secure access of Group0 IRQ */ 406 } 407 val = 0x80 | (val >> 1); /* Non-secure view */ 408 } 409 410 if (irq < GIC_INTERNAL) { 411 s->priority1[irq][cpu] = val; 412 } else { 413 s->priority2[(irq) - GIC_INTERNAL] = val; 414 } 415 } 416 417 static uint32_t gic_get_priority(GICState *s, int cpu, int irq, 418 MemTxAttrs attrs) 419 { 420 uint32_t prio = GIC_GET_PRIORITY(irq, cpu); 421 422 if (s->security_extn && !attrs.secure) { 423 if (!GIC_TEST_GROUP(irq, (1 << cpu))) { 424 return 0; /* Non-secure access cannot read priority of Group0 IRQ */ 425 } 426 prio = (prio << 1) & 0xff; /* Non-secure view */ 427 } 428 return prio; 429 } 430 431 static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, 432 MemTxAttrs attrs) 433 { 434 if (s->security_extn && !attrs.secure) { 435 if (s->priority_mask[cpu] & 0x80) { 436 /* Priority Mask in upper half */ 437 pmask = 0x80 | (pmask >> 1); 438 } else { 439 /* Non-secure write ignored if priority mask is in lower half */ 440 return; 441 } 442 } 443 s->priority_mask[cpu] = pmask; 444 } 445 446 static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs) 447 { 448 uint32_t pmask = s->priority_mask[cpu]; 449 450 if (s->security_extn && !attrs.secure) { 451 if (pmask & 0x80) { 452 /* Priority Mask in upper half, return Non-secure view */ 453 pmask = (pmask << 1) & 0xff; 454 } else { 455 /* Priority Mask in lower half, RAZ */ 456 pmask = 0; 457 } 458 } 459 return pmask; 460 } 461 462 static uint32_t gic_get_cpu_control(GICState *s, int cpu, MemTxAttrs attrs) 463 { 464 uint32_t ret = s->cpu_ctlr[cpu]; 465 466 if (s->security_extn && !attrs.secure) { 467 /* Construct the NS banked view of GICC_CTLR from the correct 468 * bits of the S banked view. We don't need to move the bypass 469 * control bits because we don't implement that (IMPDEF) part 470 * of the GIC architecture. 471 */ 472 ret = (ret & (GICC_CTLR_EN_GRP1 | GICC_CTLR_EOIMODE_NS)) >> 1; 473 } 474 return ret; 475 } 476 477 static void gic_set_cpu_control(GICState *s, int cpu, uint32_t value, 478 MemTxAttrs attrs) 479 { 480 uint32_t mask; 481 482 if (s->security_extn && !attrs.secure) { 483 /* The NS view can only write certain bits in the register; 484 * the rest are unchanged 485 */ 486 mask = GICC_CTLR_EN_GRP1; 487 if (s->revision == 2) { 488 mask |= GICC_CTLR_EOIMODE_NS; 489 } 490 s->cpu_ctlr[cpu] &= ~mask; 491 s->cpu_ctlr[cpu] |= (value << 1) & mask; 492 } else { 493 if (s->revision == 2) { 494 mask = s->security_extn ? GICC_CTLR_V2_S_MASK : GICC_CTLR_V2_MASK; 495 } else { 496 mask = s->security_extn ? GICC_CTLR_V1_S_MASK : GICC_CTLR_V1_MASK; 497 } 498 s->cpu_ctlr[cpu] = value & mask; 499 } 500 DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, " 501 "Group1 Interrupts %sabled\n", cpu, 502 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP0) ? "En" : "Dis", 503 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP1) ? "En" : "Dis"); 504 } 505 506 static uint8_t gic_get_running_priority(GICState *s, int cpu, MemTxAttrs attrs) 507 { 508 if ((s->revision != REV_11MPCORE) && (s->running_priority[cpu] > 0xff)) { 509 /* Idle priority */ 510 return 0xff; 511 } 512 513 if (s->security_extn && !attrs.secure) { 514 if (s->running_priority[cpu] & 0x80) { 515 /* Running priority in upper half of range: return the Non-secure 516 * view of the priority. 517 */ 518 return s->running_priority[cpu] << 1; 519 } else { 520 /* Running priority in lower half of range: RAZ */ 521 return 0; 522 } 523 } else { 524 return s->running_priority[cpu]; 525 } 526 } 527 528 /* Return true if we should split priority drop and interrupt deactivation, 529 * ie whether the relevant EOIMode bit is set. 530 */ 531 static bool gic_eoi_split(GICState *s, int cpu, MemTxAttrs attrs) 532 { 533 if (s->revision != 2) { 534 /* Before GICv2 prio-drop and deactivate are not separable */ 535 return false; 536 } 537 if (s->security_extn && !attrs.secure) { 538 return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE_NS; 539 } 540 return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE; 541 } 542 543 static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) 544 { 545 int cm = 1 << cpu; 546 int group; 547 548 if (irq >= s->num_irq) { 549 /* 550 * This handles two cases: 551 * 1. If software writes the ID of a spurious interrupt [ie 1023] 552 * to the GICC_DIR, the GIC ignores that write. 553 * 2. If software writes the number of a non-existent interrupt 554 * this must be a subcase of "value written is not an active interrupt" 555 * and so this is UNPREDICTABLE. We choose to ignore it. 556 */ 557 return; 558 } 559 560 group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm); 561 562 if (!gic_eoi_split(s, cpu, attrs)) { 563 /* This is UNPREDICTABLE; we choose to ignore it */ 564 qemu_log_mask(LOG_GUEST_ERROR, 565 "gic_deactivate_irq: GICC_DIR write when EOIMode clear"); 566 return; 567 } 568 569 if (s->security_extn && !attrs.secure && !group) { 570 DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq); 571 return; 572 } 573 574 GIC_CLEAR_ACTIVE(irq, cm); 575 } 576 577 void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) 578 { 579 int cm = 1 << cpu; 580 int group; 581 582 DPRINTF("EOI %d\n", irq); 583 if (irq >= s->num_irq) { 584 /* This handles two cases: 585 * 1. If software writes the ID of a spurious interrupt [ie 1023] 586 * to the GICC_EOIR, the GIC ignores that write. 587 * 2. If software writes the number of a non-existent interrupt 588 * this must be a subcase of "value written does not match the last 589 * valid interrupt value read from the Interrupt Acknowledge 590 * register" and so this is UNPREDICTABLE. We choose to ignore it. 591 */ 592 return; 593 } 594 if (s->running_priority[cpu] == 0x100) { 595 return; /* No active IRQ. */ 596 } 597 598 if (s->revision == REV_11MPCORE) { 599 /* Mark level triggered interrupts as pending if they are still 600 raised. */ 601 if (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm) 602 && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) { 603 DPRINTF("Set %d pending mask %x\n", irq, cm); 604 GIC_SET_PENDING(irq, cm); 605 } 606 } 607 608 group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm); 609 610 if (s->security_extn && !attrs.secure && !group) { 611 DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq); 612 return; 613 } 614 615 /* Secure EOI with GICC_CTLR.AckCtl == 0 when the IRQ is a Group 1 616 * interrupt is UNPREDICTABLE. We choose to handle it as if AckCtl == 1, 617 * i.e. go ahead and complete the irq anyway. 618 */ 619 620 gic_drop_prio(s, cpu, group); 621 622 /* In GICv2 the guest can choose to split priority-drop and deactivate */ 623 if (!gic_eoi_split(s, cpu, attrs)) { 624 GIC_CLEAR_ACTIVE(irq, cm); 625 } 626 gic_update(s); 627 } 628 629 static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) 630 { 631 GICState *s = (GICState *)opaque; 632 uint32_t res; 633 int irq; 634 int i; 635 int cpu; 636 int cm; 637 int mask; 638 639 cpu = gic_get_current_cpu(s); 640 cm = 1 << cpu; 641 if (offset < 0x100) { 642 if (offset == 0) { /* GICD_CTLR */ 643 if (s->security_extn && !attrs.secure) { 644 /* The NS bank of this register is just an alias of the 645 * EnableGrp1 bit in the S bank version. 646 */ 647 return extract32(s->ctlr, 1, 1); 648 } else { 649 return s->ctlr; 650 } 651 } 652 if (offset == 4) 653 /* Interrupt Controller Type Register */ 654 return ((s->num_irq / 32) - 1) 655 | ((s->num_cpu - 1) << 5) 656 | (s->security_extn << 10); 657 if (offset < 0x08) 658 return 0; 659 if (offset >= 0x80) { 660 /* Interrupt Group Registers: these RAZ/WI if this is an NS 661 * access to a GIC with the security extensions, or if the GIC 662 * doesn't have groups at all. 663 */ 664 res = 0; 665 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 666 /* Every byte offset holds 8 group status bits */ 667 irq = (offset - 0x080) * 8 + GIC_BASE_IRQ; 668 if (irq >= s->num_irq) { 669 goto bad_reg; 670 } 671 for (i = 0; i < 8; i++) { 672 if (GIC_TEST_GROUP(irq + i, cm)) { 673 res |= (1 << i); 674 } 675 } 676 } 677 return res; 678 } 679 goto bad_reg; 680 } else if (offset < 0x200) { 681 /* Interrupt Set/Clear Enable. */ 682 if (offset < 0x180) 683 irq = (offset - 0x100) * 8; 684 else 685 irq = (offset - 0x180) * 8; 686 irq += GIC_BASE_IRQ; 687 if (irq >= s->num_irq) 688 goto bad_reg; 689 res = 0; 690 for (i = 0; i < 8; i++) { 691 if (s->security_extn && !attrs.secure && 692 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 693 continue; /* Ignore Non-secure access of Group0 IRQ */ 694 } 695 696 if (GIC_TEST_ENABLED(irq + i, cm)) { 697 res |= (1 << i); 698 } 699 } 700 } else if (offset < 0x300) { 701 /* Interrupt Set/Clear Pending. */ 702 if (offset < 0x280) 703 irq = (offset - 0x200) * 8; 704 else 705 irq = (offset - 0x280) * 8; 706 irq += GIC_BASE_IRQ; 707 if (irq >= s->num_irq) 708 goto bad_reg; 709 res = 0; 710 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 711 for (i = 0; i < 8; i++) { 712 if (s->security_extn && !attrs.secure && 713 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 714 continue; /* Ignore Non-secure access of Group0 IRQ */ 715 } 716 717 if (gic_test_pending(s, irq + i, mask)) { 718 res |= (1 << i); 719 } 720 } 721 } else if (offset < 0x400) { 722 /* Interrupt Active. */ 723 irq = (offset - 0x300) * 8 + GIC_BASE_IRQ; 724 if (irq >= s->num_irq) 725 goto bad_reg; 726 res = 0; 727 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 728 for (i = 0; i < 8; i++) { 729 if (s->security_extn && !attrs.secure && 730 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 731 continue; /* Ignore Non-secure access of Group0 IRQ */ 732 } 733 734 if (GIC_TEST_ACTIVE(irq + i, mask)) { 735 res |= (1 << i); 736 } 737 } 738 } else if (offset < 0x800) { 739 /* Interrupt Priority. */ 740 irq = (offset - 0x400) + GIC_BASE_IRQ; 741 if (irq >= s->num_irq) 742 goto bad_reg; 743 res = gic_get_priority(s, cpu, irq, attrs); 744 } else if (offset < 0xc00) { 745 /* Interrupt CPU Target. */ 746 if (s->num_cpu == 1 && s->revision != REV_11MPCORE) { 747 /* For uniprocessor GICs these RAZ/WI */ 748 res = 0; 749 } else { 750 irq = (offset - 0x800) + GIC_BASE_IRQ; 751 if (irq >= s->num_irq) { 752 goto bad_reg; 753 } 754 if (irq < 29 && s->revision == REV_11MPCORE) { 755 res = 0; 756 } else if (irq < GIC_INTERNAL) { 757 res = cm; 758 } else { 759 res = GIC_TARGET(irq); 760 } 761 } 762 } else if (offset < 0xf00) { 763 /* Interrupt Configuration. */ 764 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 765 if (irq >= s->num_irq) 766 goto bad_reg; 767 res = 0; 768 for (i = 0; i < 4; i++) { 769 if (s->security_extn && !attrs.secure && 770 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 771 continue; /* Ignore Non-secure access of Group0 IRQ */ 772 } 773 774 if (GIC_TEST_MODEL(irq + i)) 775 res |= (1 << (i * 2)); 776 if (GIC_TEST_EDGE_TRIGGER(irq + i)) 777 res |= (2 << (i * 2)); 778 } 779 } else if (offset < 0xf10) { 780 goto bad_reg; 781 } else if (offset < 0xf30) { 782 if (s->revision == REV_11MPCORE) { 783 goto bad_reg; 784 } 785 786 if (offset < 0xf20) { 787 /* GICD_CPENDSGIRn */ 788 irq = (offset - 0xf10); 789 } else { 790 irq = (offset - 0xf20); 791 /* GICD_SPENDSGIRn */ 792 } 793 794 if (s->security_extn && !attrs.secure && 795 !GIC_TEST_GROUP(irq, 1 << cpu)) { 796 res = 0; /* Ignore Non-secure access of Group0 IRQ */ 797 } else { 798 res = s->sgi_pending[irq][cpu]; 799 } 800 } else if (offset < 0xfd0) { 801 goto bad_reg; 802 } else if (offset < 0x1000) { 803 if (offset & 3) { 804 res = 0; 805 } else { 806 switch (s->revision) { 807 case REV_11MPCORE: 808 res = gic_id_11mpcore[(offset - 0xfd0) >> 2]; 809 break; 810 case 1: 811 res = gic_id_gicv1[(offset - 0xfd0) >> 2]; 812 break; 813 case 2: 814 res = gic_id_gicv2[(offset - 0xfd0) >> 2]; 815 break; 816 default: 817 res = 0; 818 } 819 } 820 } else { 821 g_assert_not_reached(); 822 } 823 return res; 824 bad_reg: 825 qemu_log_mask(LOG_GUEST_ERROR, 826 "gic_dist_readb: Bad offset %x\n", (int)offset); 827 return 0; 828 } 829 830 static MemTxResult gic_dist_read(void *opaque, hwaddr offset, uint64_t *data, 831 unsigned size, MemTxAttrs attrs) 832 { 833 switch (size) { 834 case 1: 835 *data = gic_dist_readb(opaque, offset, attrs); 836 return MEMTX_OK; 837 case 2: 838 *data = gic_dist_readb(opaque, offset, attrs); 839 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 840 return MEMTX_OK; 841 case 4: 842 *data = gic_dist_readb(opaque, offset, attrs); 843 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 844 *data |= gic_dist_readb(opaque, offset + 2, attrs) << 16; 845 *data |= gic_dist_readb(opaque, offset + 3, attrs) << 24; 846 return MEMTX_OK; 847 default: 848 return MEMTX_ERROR; 849 } 850 } 851 852 static void gic_dist_writeb(void *opaque, hwaddr offset, 853 uint32_t value, MemTxAttrs attrs) 854 { 855 GICState *s = (GICState *)opaque; 856 int irq; 857 int i; 858 int cpu; 859 860 cpu = gic_get_current_cpu(s); 861 if (offset < 0x100) { 862 if (offset == 0) { 863 if (s->security_extn && !attrs.secure) { 864 /* NS version is just an alias of the S version's bit 1 */ 865 s->ctlr = deposit32(s->ctlr, 1, 1, value); 866 } else if (gic_has_groups(s)) { 867 s->ctlr = value & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1); 868 } else { 869 s->ctlr = value & GICD_CTLR_EN_GRP0; 870 } 871 DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n", 872 s->ctlr & GICD_CTLR_EN_GRP0 ? "En" : "Dis", 873 s->ctlr & GICD_CTLR_EN_GRP1 ? "En" : "Dis"); 874 } else if (offset < 4) { 875 /* ignored. */ 876 } else if (offset >= 0x80) { 877 /* Interrupt Group Registers: RAZ/WI for NS access to secure 878 * GIC, or for GICs without groups. 879 */ 880 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 881 /* Every byte offset holds 8 group status bits */ 882 irq = (offset - 0x80) * 8 + GIC_BASE_IRQ; 883 if (irq >= s->num_irq) { 884 goto bad_reg; 885 } 886 for (i = 0; i < 8; i++) { 887 /* Group bits are banked for private interrupts */ 888 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 889 if (value & (1 << i)) { 890 /* Group1 (Non-secure) */ 891 GIC_SET_GROUP(irq + i, cm); 892 } else { 893 /* Group0 (Secure) */ 894 GIC_CLEAR_GROUP(irq + i, cm); 895 } 896 } 897 } 898 } else { 899 goto bad_reg; 900 } 901 } else if (offset < 0x180) { 902 /* Interrupt Set Enable. */ 903 irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; 904 if (irq >= s->num_irq) 905 goto bad_reg; 906 if (irq < GIC_NR_SGIS) { 907 value = 0xff; 908 } 909 910 for (i = 0; i < 8; i++) { 911 if (value & (1 << i)) { 912 int mask = 913 (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq + i); 914 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 915 916 if (s->security_extn && !attrs.secure && 917 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 918 continue; /* Ignore Non-secure access of Group0 IRQ */ 919 } 920 921 if (!GIC_TEST_ENABLED(irq + i, cm)) { 922 DPRINTF("Enabled IRQ %d\n", irq + i); 923 trace_gic_enable_irq(irq + i); 924 } 925 GIC_SET_ENABLED(irq + i, cm); 926 /* If a raised level triggered IRQ enabled then mark 927 is as pending. */ 928 if (GIC_TEST_LEVEL(irq + i, mask) 929 && !GIC_TEST_EDGE_TRIGGER(irq + i)) { 930 DPRINTF("Set %d pending mask %x\n", irq + i, mask); 931 GIC_SET_PENDING(irq + i, mask); 932 } 933 } 934 } 935 } else if (offset < 0x200) { 936 /* Interrupt Clear Enable. */ 937 irq = (offset - 0x180) * 8 + GIC_BASE_IRQ; 938 if (irq >= s->num_irq) 939 goto bad_reg; 940 if (irq < GIC_NR_SGIS) { 941 value = 0; 942 } 943 944 for (i = 0; i < 8; i++) { 945 if (value & (1 << i)) { 946 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 947 948 if (s->security_extn && !attrs.secure && 949 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 950 continue; /* Ignore Non-secure access of Group0 IRQ */ 951 } 952 953 if (GIC_TEST_ENABLED(irq + i, cm)) { 954 DPRINTF("Disabled IRQ %d\n", irq + i); 955 trace_gic_disable_irq(irq + i); 956 } 957 GIC_CLEAR_ENABLED(irq + i, cm); 958 } 959 } 960 } else if (offset < 0x280) { 961 /* Interrupt Set Pending. */ 962 irq = (offset - 0x200) * 8 + GIC_BASE_IRQ; 963 if (irq >= s->num_irq) 964 goto bad_reg; 965 if (irq < GIC_NR_SGIS) { 966 value = 0; 967 } 968 969 for (i = 0; i < 8; i++) { 970 if (value & (1 << i)) { 971 if (s->security_extn && !attrs.secure && 972 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 973 continue; /* Ignore Non-secure access of Group0 IRQ */ 974 } 975 976 GIC_SET_PENDING(irq + i, GIC_TARGET(irq + i)); 977 } 978 } 979 } else if (offset < 0x300) { 980 /* Interrupt Clear Pending. */ 981 irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; 982 if (irq >= s->num_irq) 983 goto bad_reg; 984 if (irq < GIC_NR_SGIS) { 985 value = 0; 986 } 987 988 for (i = 0; i < 8; i++) { 989 if (s->security_extn && !attrs.secure && 990 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 991 continue; /* Ignore Non-secure access of Group0 IRQ */ 992 } 993 994 /* ??? This currently clears the pending bit for all CPUs, even 995 for per-CPU interrupts. It's unclear whether this is the 996 corect behavior. */ 997 if (value & (1 << i)) { 998 GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK); 999 } 1000 } 1001 } else if (offset < 0x400) { 1002 /* Interrupt Active. */ 1003 goto bad_reg; 1004 } else if (offset < 0x800) { 1005 /* Interrupt Priority. */ 1006 irq = (offset - 0x400) + GIC_BASE_IRQ; 1007 if (irq >= s->num_irq) 1008 goto bad_reg; 1009 gic_set_priority(s, cpu, irq, value, attrs); 1010 } else if (offset < 0xc00) { 1011 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the 1012 * annoying exception of the 11MPCore's GIC. 1013 */ 1014 if (s->num_cpu != 1 || s->revision == REV_11MPCORE) { 1015 irq = (offset - 0x800) + GIC_BASE_IRQ; 1016 if (irq >= s->num_irq) { 1017 goto bad_reg; 1018 } 1019 if (irq < 29 && s->revision == REV_11MPCORE) { 1020 value = 0; 1021 } else if (irq < GIC_INTERNAL) { 1022 value = ALL_CPU_MASK; 1023 } 1024 s->irq_target[irq] = value & ALL_CPU_MASK; 1025 } 1026 } else if (offset < 0xf00) { 1027 /* Interrupt Configuration. */ 1028 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 1029 if (irq >= s->num_irq) 1030 goto bad_reg; 1031 if (irq < GIC_NR_SGIS) 1032 value |= 0xaa; 1033 for (i = 0; i < 4; i++) { 1034 if (s->security_extn && !attrs.secure && 1035 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 1036 continue; /* Ignore Non-secure access of Group0 IRQ */ 1037 } 1038 1039 if (s->revision == REV_11MPCORE) { 1040 if (value & (1 << (i * 2))) { 1041 GIC_SET_MODEL(irq + i); 1042 } else { 1043 GIC_CLEAR_MODEL(irq + i); 1044 } 1045 } 1046 if (value & (2 << (i * 2))) { 1047 GIC_SET_EDGE_TRIGGER(irq + i); 1048 } else { 1049 GIC_CLEAR_EDGE_TRIGGER(irq + i); 1050 } 1051 } 1052 } else if (offset < 0xf10) { 1053 /* 0xf00 is only handled for 32-bit writes. */ 1054 goto bad_reg; 1055 } else if (offset < 0xf20) { 1056 /* GICD_CPENDSGIRn */ 1057 if (s->revision == REV_11MPCORE) { 1058 goto bad_reg; 1059 } 1060 irq = (offset - 0xf10); 1061 1062 if (!s->security_extn || attrs.secure || 1063 GIC_TEST_GROUP(irq, 1 << cpu)) { 1064 s->sgi_pending[irq][cpu] &= ~value; 1065 if (s->sgi_pending[irq][cpu] == 0) { 1066 GIC_CLEAR_PENDING(irq, 1 << cpu); 1067 } 1068 } 1069 } else if (offset < 0xf30) { 1070 /* GICD_SPENDSGIRn */ 1071 if (s->revision == REV_11MPCORE) { 1072 goto bad_reg; 1073 } 1074 irq = (offset - 0xf20); 1075 1076 if (!s->security_extn || attrs.secure || 1077 GIC_TEST_GROUP(irq, 1 << cpu)) { 1078 GIC_SET_PENDING(irq, 1 << cpu); 1079 s->sgi_pending[irq][cpu] |= value; 1080 } 1081 } else { 1082 goto bad_reg; 1083 } 1084 gic_update(s); 1085 return; 1086 bad_reg: 1087 qemu_log_mask(LOG_GUEST_ERROR, 1088 "gic_dist_writeb: Bad offset %x\n", (int)offset); 1089 } 1090 1091 static void gic_dist_writew(void *opaque, hwaddr offset, 1092 uint32_t value, MemTxAttrs attrs) 1093 { 1094 gic_dist_writeb(opaque, offset, value & 0xff, attrs); 1095 gic_dist_writeb(opaque, offset + 1, value >> 8, attrs); 1096 } 1097 1098 static void gic_dist_writel(void *opaque, hwaddr offset, 1099 uint32_t value, MemTxAttrs attrs) 1100 { 1101 GICState *s = (GICState *)opaque; 1102 if (offset == 0xf00) { 1103 int cpu; 1104 int irq; 1105 int mask; 1106 int target_cpu; 1107 1108 cpu = gic_get_current_cpu(s); 1109 irq = value & 0x3ff; 1110 switch ((value >> 24) & 3) { 1111 case 0: 1112 mask = (value >> 16) & ALL_CPU_MASK; 1113 break; 1114 case 1: 1115 mask = ALL_CPU_MASK ^ (1 << cpu); 1116 break; 1117 case 2: 1118 mask = 1 << cpu; 1119 break; 1120 default: 1121 DPRINTF("Bad Soft Int target filter\n"); 1122 mask = ALL_CPU_MASK; 1123 break; 1124 } 1125 GIC_SET_PENDING(irq, mask); 1126 target_cpu = ctz32(mask); 1127 while (target_cpu < GIC_NCPU) { 1128 s->sgi_pending[irq][target_cpu] |= (1 << cpu); 1129 mask &= ~(1 << target_cpu); 1130 target_cpu = ctz32(mask); 1131 } 1132 gic_update(s); 1133 return; 1134 } 1135 gic_dist_writew(opaque, offset, value & 0xffff, attrs); 1136 gic_dist_writew(opaque, offset + 2, value >> 16, attrs); 1137 } 1138 1139 static MemTxResult gic_dist_write(void *opaque, hwaddr offset, uint64_t data, 1140 unsigned size, MemTxAttrs attrs) 1141 { 1142 switch (size) { 1143 case 1: 1144 gic_dist_writeb(opaque, offset, data, attrs); 1145 return MEMTX_OK; 1146 case 2: 1147 gic_dist_writew(opaque, offset, data, attrs); 1148 return MEMTX_OK; 1149 case 4: 1150 gic_dist_writel(opaque, offset, data, attrs); 1151 return MEMTX_OK; 1152 default: 1153 return MEMTX_ERROR; 1154 } 1155 } 1156 1157 static inline uint32_t gic_apr_ns_view(GICState *s, int cpu, int regno) 1158 { 1159 /* Return the Nonsecure view of GICC_APR<regno>. This is the 1160 * second half of GICC_NSAPR. 1161 */ 1162 switch (GIC_MIN_BPR) { 1163 case 0: 1164 if (regno < 2) { 1165 return s->nsapr[regno + 2][cpu]; 1166 } 1167 break; 1168 case 1: 1169 if (regno == 0) { 1170 return s->nsapr[regno + 1][cpu]; 1171 } 1172 break; 1173 case 2: 1174 if (regno == 0) { 1175 return extract32(s->nsapr[0][cpu], 16, 16); 1176 } 1177 break; 1178 case 3: 1179 if (regno == 0) { 1180 return extract32(s->nsapr[0][cpu], 8, 8); 1181 } 1182 break; 1183 default: 1184 g_assert_not_reached(); 1185 } 1186 return 0; 1187 } 1188 1189 static inline void gic_apr_write_ns_view(GICState *s, int cpu, int regno, 1190 uint32_t value) 1191 { 1192 /* Write the Nonsecure view of GICC_APR<regno>. */ 1193 switch (GIC_MIN_BPR) { 1194 case 0: 1195 if (regno < 2) { 1196 s->nsapr[regno + 2][cpu] = value; 1197 } 1198 break; 1199 case 1: 1200 if (regno == 0) { 1201 s->nsapr[regno + 1][cpu] = value; 1202 } 1203 break; 1204 case 2: 1205 if (regno == 0) { 1206 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 16, 16, value); 1207 } 1208 break; 1209 case 3: 1210 if (regno == 0) { 1211 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 8, 8, value); 1212 } 1213 break; 1214 default: 1215 g_assert_not_reached(); 1216 } 1217 } 1218 1219 static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset, 1220 uint64_t *data, MemTxAttrs attrs) 1221 { 1222 switch (offset) { 1223 case 0x00: /* Control */ 1224 *data = gic_get_cpu_control(s, cpu, attrs); 1225 break; 1226 case 0x04: /* Priority mask */ 1227 *data = gic_get_priority_mask(s, cpu, attrs); 1228 break; 1229 case 0x08: /* Binary Point */ 1230 if (s->security_extn && !attrs.secure) { 1231 if (s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) { 1232 /* NS view of BPR when CBPR is 1 */ 1233 *data = MIN(s->bpr[cpu] + 1, 7); 1234 } else { 1235 /* BPR is banked. Non-secure copy stored in ABPR. */ 1236 *data = s->abpr[cpu]; 1237 } 1238 } else { 1239 *data = s->bpr[cpu]; 1240 } 1241 break; 1242 case 0x0c: /* Acknowledge */ 1243 *data = gic_acknowledge_irq(s, cpu, attrs); 1244 break; 1245 case 0x14: /* Running Priority */ 1246 *data = gic_get_running_priority(s, cpu, attrs); 1247 break; 1248 case 0x18: /* Highest Pending Interrupt */ 1249 *data = gic_get_current_pending_irq(s, cpu, attrs); 1250 break; 1251 case 0x1c: /* Aliased Binary Point */ 1252 /* GIC v2, no security: ABPR 1253 * GIC v1, no security: not implemented (RAZ/WI) 1254 * With security extensions, secure access: ABPR (alias of NS BPR) 1255 * With security extensions, nonsecure access: RAZ/WI 1256 */ 1257 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 1258 *data = 0; 1259 } else { 1260 *data = s->abpr[cpu]; 1261 } 1262 break; 1263 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 1264 { 1265 int regno = (offset - 0xd0) / 4; 1266 1267 if (regno >= GIC_NR_APRS || s->revision != 2) { 1268 *data = 0; 1269 } else if (s->security_extn && !attrs.secure) { 1270 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ 1271 *data = gic_apr_ns_view(s, regno, cpu); 1272 } else { 1273 *data = s->apr[regno][cpu]; 1274 } 1275 break; 1276 } 1277 case 0xe0: case 0xe4: case 0xe8: case 0xec: 1278 { 1279 int regno = (offset - 0xe0) / 4; 1280 1281 if (regno >= GIC_NR_APRS || s->revision != 2 || !gic_has_groups(s) || 1282 (s->security_extn && !attrs.secure)) { 1283 *data = 0; 1284 } else { 1285 *data = s->nsapr[regno][cpu]; 1286 } 1287 break; 1288 } 1289 default: 1290 qemu_log_mask(LOG_GUEST_ERROR, 1291 "gic_cpu_read: Bad offset %x\n", (int)offset); 1292 *data = 0; 1293 break; 1294 } 1295 return MEMTX_OK; 1296 } 1297 1298 static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset, 1299 uint32_t value, MemTxAttrs attrs) 1300 { 1301 switch (offset) { 1302 case 0x00: /* Control */ 1303 gic_set_cpu_control(s, cpu, value, attrs); 1304 break; 1305 case 0x04: /* Priority mask */ 1306 gic_set_priority_mask(s, cpu, value, attrs); 1307 break; 1308 case 0x08: /* Binary Point */ 1309 if (s->security_extn && !attrs.secure) { 1310 if (s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) { 1311 /* WI when CBPR is 1 */ 1312 return MEMTX_OK; 1313 } else { 1314 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 1315 } 1316 } else { 1317 s->bpr[cpu] = MAX(value & 0x7, GIC_MIN_BPR); 1318 } 1319 break; 1320 case 0x10: /* End Of Interrupt */ 1321 gic_complete_irq(s, cpu, value & 0x3ff, attrs); 1322 return MEMTX_OK; 1323 case 0x1c: /* Aliased Binary Point */ 1324 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 1325 /* unimplemented, or NS access: RAZ/WI */ 1326 return MEMTX_OK; 1327 } else { 1328 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 1329 } 1330 break; 1331 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 1332 { 1333 int regno = (offset - 0xd0) / 4; 1334 1335 if (regno >= GIC_NR_APRS || s->revision != 2) { 1336 return MEMTX_OK; 1337 } 1338 if (s->security_extn && !attrs.secure) { 1339 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ 1340 gic_apr_write_ns_view(s, regno, cpu, value); 1341 } else { 1342 s->apr[regno][cpu] = value; 1343 } 1344 break; 1345 } 1346 case 0xe0: case 0xe4: case 0xe8: case 0xec: 1347 { 1348 int regno = (offset - 0xe0) / 4; 1349 1350 if (regno >= GIC_NR_APRS || s->revision != 2) { 1351 return MEMTX_OK; 1352 } 1353 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 1354 return MEMTX_OK; 1355 } 1356 s->nsapr[regno][cpu] = value; 1357 break; 1358 } 1359 case 0x1000: 1360 /* GICC_DIR */ 1361 gic_deactivate_irq(s, cpu, value & 0x3ff, attrs); 1362 break; 1363 default: 1364 qemu_log_mask(LOG_GUEST_ERROR, 1365 "gic_cpu_write: Bad offset %x\n", (int)offset); 1366 return MEMTX_OK; 1367 } 1368 gic_update(s); 1369 return MEMTX_OK; 1370 } 1371 1372 /* Wrappers to read/write the GIC CPU interface for the current CPU */ 1373 static MemTxResult gic_thiscpu_read(void *opaque, hwaddr addr, uint64_t *data, 1374 unsigned size, MemTxAttrs attrs) 1375 { 1376 GICState *s = (GICState *)opaque; 1377 return gic_cpu_read(s, gic_get_current_cpu(s), addr, data, attrs); 1378 } 1379 1380 static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, 1381 uint64_t value, unsigned size, 1382 MemTxAttrs attrs) 1383 { 1384 GICState *s = (GICState *)opaque; 1385 return gic_cpu_write(s, gic_get_current_cpu(s), addr, value, attrs); 1386 } 1387 1388 /* Wrappers to read/write the GIC CPU interface for a specific CPU. 1389 * These just decode the opaque pointer into GICState* + cpu id. 1390 */ 1391 static MemTxResult gic_do_cpu_read(void *opaque, hwaddr addr, uint64_t *data, 1392 unsigned size, MemTxAttrs attrs) 1393 { 1394 GICState **backref = (GICState **)opaque; 1395 GICState *s = *backref; 1396 int id = (backref - s->backref); 1397 return gic_cpu_read(s, id, addr, data, attrs); 1398 } 1399 1400 static MemTxResult gic_do_cpu_write(void *opaque, hwaddr addr, 1401 uint64_t value, unsigned size, 1402 MemTxAttrs attrs) 1403 { 1404 GICState **backref = (GICState **)opaque; 1405 GICState *s = *backref; 1406 int id = (backref - s->backref); 1407 return gic_cpu_write(s, id, addr, value, attrs); 1408 } 1409 1410 static const MemoryRegionOps gic_ops[2] = { 1411 { 1412 .read_with_attrs = gic_dist_read, 1413 .write_with_attrs = gic_dist_write, 1414 .endianness = DEVICE_NATIVE_ENDIAN, 1415 }, 1416 { 1417 .read_with_attrs = gic_thiscpu_read, 1418 .write_with_attrs = gic_thiscpu_write, 1419 .endianness = DEVICE_NATIVE_ENDIAN, 1420 } 1421 }; 1422 1423 static const MemoryRegionOps gic_cpu_ops = { 1424 .read_with_attrs = gic_do_cpu_read, 1425 .write_with_attrs = gic_do_cpu_write, 1426 .endianness = DEVICE_NATIVE_ENDIAN, 1427 }; 1428 1429 /* This function is used by nvic model */ 1430 void gic_init_irqs_and_distributor(GICState *s) 1431 { 1432 gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops); 1433 } 1434 1435 static void arm_gic_realize(DeviceState *dev, Error **errp) 1436 { 1437 /* Device instance realize function for the GIC sysbus device */ 1438 int i; 1439 GICState *s = ARM_GIC(dev); 1440 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1441 ARMGICClass *agc = ARM_GIC_GET_CLASS(s); 1442 Error *local_err = NULL; 1443 1444 agc->parent_realize(dev, &local_err); 1445 if (local_err) { 1446 error_propagate(errp, local_err); 1447 return; 1448 } 1449 1450 if (kvm_enabled() && !kvm_arm_supports_user_irq()) { 1451 error_setg(errp, "KVM with user space irqchip only works when the " 1452 "host kernel supports KVM_CAP_ARM_USER_IRQ"); 1453 return; 1454 } 1455 1456 /* This creates distributor and main CPU interface (s->cpuiomem[0]) */ 1457 gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops); 1458 1459 /* Extra core-specific regions for the CPU interfaces. This is 1460 * necessary for "franken-GIC" implementations, for example on 1461 * Exynos 4. 1462 * NB that the memory region size of 0x100 applies for the 11MPCore 1463 * and also cores following the GIC v1 spec (ie A9). 1464 * GIC v2 defines a larger memory region (0x1000) so this will need 1465 * to be extended when we implement A15. 1466 */ 1467 for (i = 0; i < s->num_cpu; i++) { 1468 s->backref[i] = s; 1469 memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops, 1470 &s->backref[i], "gic_cpu", 0x100); 1471 sysbus_init_mmio(sbd, &s->cpuiomem[i+1]); 1472 } 1473 } 1474 1475 static void arm_gic_class_init(ObjectClass *klass, void *data) 1476 { 1477 DeviceClass *dc = DEVICE_CLASS(klass); 1478 ARMGICClass *agc = ARM_GIC_CLASS(klass); 1479 1480 device_class_set_parent_realize(dc, arm_gic_realize, &agc->parent_realize); 1481 } 1482 1483 static const TypeInfo arm_gic_info = { 1484 .name = TYPE_ARM_GIC, 1485 .parent = TYPE_ARM_GIC_COMMON, 1486 .instance_size = sizeof(GICState), 1487 .class_init = arm_gic_class_init, 1488 .class_size = sizeof(ARMGICClass), 1489 }; 1490 1491 static void arm_gic_register_types(void) 1492 { 1493 type_register_static(&arm_gic_info); 1494 } 1495 1496 type_init(arm_gic_register_types) 1497