1 /* 2 * ARM Generic/Distributed Interrupt Controller 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 /* This file contains implementation code for the RealView EB interrupt 11 * controller, MPCore distributed interrupt controller and ARMv7-M 12 * Nested Vectored Interrupt Controller. 13 * It is compiled in two ways: 14 * (1) as a standalone file to produce a sysbus device which is a GIC 15 * that can be used on the realview board and as one of the builtin 16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc) 17 * (2) by being directly #included into armv7m_nvic.c to produce the 18 * armv7m_nvic device. 19 */ 20 21 #include "hw/sysbus.h" 22 #include "gic_internal.h" 23 #include "qom/cpu.h" 24 25 //#define DEBUG_GIC 26 27 #ifdef DEBUG_GIC 28 #define DPRINTF(fmt, ...) \ 29 do { fprintf(stderr, "arm_gic: " fmt , ## __VA_ARGS__); } while (0) 30 #else 31 #define DPRINTF(fmt, ...) do {} while(0) 32 #endif 33 34 static const uint8_t gic_id_11mpcore[] = { 35 0x00, 0x00, 0x00, 0x00, 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 36 }; 37 38 static const uint8_t gic_id_gicv1[] = { 39 0x04, 0x00, 0x00, 0x00, 0x90, 0xb3, 0x1b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 40 }; 41 42 static const uint8_t gic_id_gicv2[] = { 43 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 44 }; 45 46 static inline int gic_get_current_cpu(GICState *s) 47 { 48 if (s->num_cpu > 1) { 49 return current_cpu->cpu_index; 50 } 51 return 0; 52 } 53 54 /* Return true if this GIC config has interrupt groups, which is 55 * true if we're a GICv2, or a GICv1 with the security extensions. 56 */ 57 static inline bool gic_has_groups(GICState *s) 58 { 59 return s->revision == 2 || s->security_extn; 60 } 61 62 /* TODO: Many places that call this routine could be optimized. */ 63 /* Update interrupt status after enabled or pending bits have been changed. */ 64 void gic_update(GICState *s) 65 { 66 int best_irq; 67 int best_prio; 68 int irq; 69 int irq_level, fiq_level; 70 int cpu; 71 int cm; 72 73 for (cpu = 0; cpu < s->num_cpu; cpu++) { 74 cm = 1 << cpu; 75 s->current_pending[cpu] = 1023; 76 if (!(s->ctlr & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1)) 77 || !(s->cpu_ctlr[cpu] & (GICC_CTLR_EN_GRP0 | GICC_CTLR_EN_GRP1))) { 78 qemu_irq_lower(s->parent_irq[cpu]); 79 qemu_irq_lower(s->parent_fiq[cpu]); 80 continue; 81 } 82 best_prio = 0x100; 83 best_irq = 1023; 84 for (irq = 0; irq < s->num_irq; irq++) { 85 if (GIC_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm) && 86 (irq < GIC_INTERNAL || GIC_TARGET(irq) & cm)) { 87 if (GIC_GET_PRIORITY(irq, cpu) < best_prio) { 88 best_prio = GIC_GET_PRIORITY(irq, cpu); 89 best_irq = irq; 90 } 91 } 92 } 93 94 irq_level = fiq_level = 0; 95 96 if (best_prio < s->priority_mask[cpu]) { 97 s->current_pending[cpu] = best_irq; 98 if (best_prio < s->running_priority[cpu]) { 99 int group = GIC_TEST_GROUP(best_irq, cm); 100 101 if (extract32(s->ctlr, group, 1) && 102 extract32(s->cpu_ctlr[cpu], group, 1)) { 103 if (group == 0 && s->cpu_ctlr[cpu] & GICC_CTLR_FIQ_EN) { 104 DPRINTF("Raised pending FIQ %d (cpu %d)\n", 105 best_irq, cpu); 106 fiq_level = 1; 107 } else { 108 DPRINTF("Raised pending IRQ %d (cpu %d)\n", 109 best_irq, cpu); 110 irq_level = 1; 111 } 112 } 113 } 114 } 115 116 qemu_set_irq(s->parent_irq[cpu], irq_level); 117 qemu_set_irq(s->parent_fiq[cpu], fiq_level); 118 } 119 } 120 121 void gic_set_pending_private(GICState *s, int cpu, int irq) 122 { 123 int cm = 1 << cpu; 124 125 if (gic_test_pending(s, irq, cm)) { 126 return; 127 } 128 129 DPRINTF("Set %d pending cpu %d\n", irq, cpu); 130 GIC_SET_PENDING(irq, cm); 131 gic_update(s); 132 } 133 134 static void gic_set_irq_11mpcore(GICState *s, int irq, int level, 135 int cm, int target) 136 { 137 if (level) { 138 GIC_SET_LEVEL(irq, cm); 139 if (GIC_TEST_EDGE_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) { 140 DPRINTF("Set %d pending mask %x\n", irq, target); 141 GIC_SET_PENDING(irq, target); 142 } 143 } else { 144 GIC_CLEAR_LEVEL(irq, cm); 145 } 146 } 147 148 static void gic_set_irq_generic(GICState *s, int irq, int level, 149 int cm, int target) 150 { 151 if (level) { 152 GIC_SET_LEVEL(irq, cm); 153 DPRINTF("Set %d pending mask %x\n", irq, target); 154 if (GIC_TEST_EDGE_TRIGGER(irq)) { 155 GIC_SET_PENDING(irq, target); 156 } 157 } else { 158 GIC_CLEAR_LEVEL(irq, cm); 159 } 160 } 161 162 /* Process a change in an external IRQ input. */ 163 static void gic_set_irq(void *opaque, int irq, int level) 164 { 165 /* Meaning of the 'irq' parameter: 166 * [0..N-1] : external interrupts 167 * [N..N+31] : PPI (internal) interrupts for CPU 0 168 * [N+32..N+63] : PPI (internal interrupts for CPU 1 169 * ... 170 */ 171 GICState *s = (GICState *)opaque; 172 int cm, target; 173 if (irq < (s->num_irq - GIC_INTERNAL)) { 174 /* The first external input line is internal interrupt 32. */ 175 cm = ALL_CPU_MASK; 176 irq += GIC_INTERNAL; 177 target = GIC_TARGET(irq); 178 } else { 179 int cpu; 180 irq -= (s->num_irq - GIC_INTERNAL); 181 cpu = irq / GIC_INTERNAL; 182 irq %= GIC_INTERNAL; 183 cm = 1 << cpu; 184 target = cm; 185 } 186 187 assert(irq >= GIC_NR_SGIS); 188 189 if (level == GIC_TEST_LEVEL(irq, cm)) { 190 return; 191 } 192 193 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 194 gic_set_irq_11mpcore(s, irq, level, cm, target); 195 } else { 196 gic_set_irq_generic(s, irq, level, cm, target); 197 } 198 199 gic_update(s); 200 } 201 202 static uint16_t gic_get_current_pending_irq(GICState *s, int cpu, 203 MemTxAttrs attrs) 204 { 205 uint16_t pending_irq = s->current_pending[cpu]; 206 207 if (pending_irq < GIC_MAXIRQ && gic_has_groups(s)) { 208 int group = GIC_TEST_GROUP(pending_irq, (1 << cpu)); 209 /* On a GIC without the security extensions, reading this register 210 * behaves in the same way as a secure access to a GIC with them. 211 */ 212 bool secure = !s->security_extn || attrs.secure; 213 214 if (group == 0 && !secure) { 215 /* Group0 interrupts hidden from Non-secure access */ 216 return 1023; 217 } 218 if (group == 1 && secure && !(s->cpu_ctlr[cpu] & GICC_CTLR_ACK_CTL)) { 219 /* Group1 interrupts only seen by Secure access if 220 * AckCtl bit set. 221 */ 222 return 1022; 223 } 224 } 225 return pending_irq; 226 } 227 228 static int gic_get_group_priority(GICState *s, int cpu, int irq) 229 { 230 /* Return the group priority of the specified interrupt 231 * (which is the top bits of its priority, with the number 232 * of bits masked determined by the applicable binary point register). 233 */ 234 int bpr; 235 uint32_t mask; 236 237 if (gic_has_groups(s) && 238 !(s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) && 239 GIC_TEST_GROUP(irq, (1 << cpu))) { 240 bpr = s->abpr[cpu]; 241 } else { 242 bpr = s->bpr[cpu]; 243 } 244 245 /* a BPR of 0 means the group priority bits are [7:1]; 246 * a BPR of 1 means they are [7:2], and so on down to 247 * a BPR of 7 meaning no group priority bits at all. 248 */ 249 mask = ~0U << ((bpr & 7) + 1); 250 251 return GIC_GET_PRIORITY(irq, cpu) & mask; 252 } 253 254 static void gic_activate_irq(GICState *s, int cpu, int irq) 255 { 256 /* Set the appropriate Active Priority Register bit for this IRQ, 257 * and update the running priority. 258 */ 259 int prio = gic_get_group_priority(s, cpu, irq); 260 int preemption_level = prio >> (GIC_MIN_BPR + 1); 261 int regno = preemption_level / 32; 262 int bitno = preemption_level % 32; 263 264 if (gic_has_groups(s) && GIC_TEST_GROUP(irq, (1 << cpu))) { 265 s->nsapr[regno][cpu] |= (1 << bitno); 266 } else { 267 s->apr[regno][cpu] |= (1 << bitno); 268 } 269 270 s->running_priority[cpu] = prio; 271 GIC_SET_ACTIVE(irq, 1 << cpu); 272 } 273 274 static int gic_get_prio_from_apr_bits(GICState *s, int cpu) 275 { 276 /* Recalculate the current running priority for this CPU based 277 * on the set bits in the Active Priority Registers. 278 */ 279 int i; 280 for (i = 0; i < GIC_NR_APRS; i++) { 281 uint32_t apr = s->apr[i][cpu] | s->nsapr[i][cpu]; 282 if (!apr) { 283 continue; 284 } 285 return (i * 32 + ctz32(apr)) << (GIC_MIN_BPR + 1); 286 } 287 return 0x100; 288 } 289 290 static void gic_drop_prio(GICState *s, int cpu, int group) 291 { 292 /* Drop the priority of the currently active interrupt in the 293 * specified group. 294 * 295 * Note that we can guarantee (because of the requirement to nest 296 * GICC_IAR reads [which activate an interrupt and raise priority] 297 * with GICC_EOIR writes [which drop the priority for the interrupt]) 298 * that the interrupt we're being called for is the highest priority 299 * active interrupt, meaning that it has the lowest set bit in the 300 * APR registers. 301 * 302 * If the guest does not honour the ordering constraints then the 303 * behaviour of the GIC is UNPREDICTABLE, which for us means that 304 * the values of the APR registers might become incorrect and the 305 * running priority will be wrong, so interrupts that should preempt 306 * might not do so, and interrupts that should not preempt might do so. 307 */ 308 int i; 309 310 for (i = 0; i < GIC_NR_APRS; i++) { 311 uint32_t *papr = group ? &s->nsapr[i][cpu] : &s->apr[i][cpu]; 312 if (!*papr) { 313 continue; 314 } 315 /* Clear lowest set bit */ 316 *papr &= *papr - 1; 317 break; 318 } 319 320 s->running_priority[cpu] = gic_get_prio_from_apr_bits(s, cpu); 321 } 322 323 uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs) 324 { 325 int ret, irq, src; 326 int cm = 1 << cpu; 327 328 /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately 329 * for the case where this GIC supports grouping and the pending interrupt 330 * is in the wrong group. 331 */ 332 irq = gic_get_current_pending_irq(s, cpu, attrs); 333 334 if (irq >= GIC_MAXIRQ) { 335 DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq); 336 return irq; 337 } 338 339 if (GIC_GET_PRIORITY(irq, cpu) >= s->running_priority[cpu]) { 340 DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq); 341 return 1023; 342 } 343 344 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 345 /* Clear pending flags for both level and edge triggered interrupts. 346 * Level triggered IRQs will be reasserted once they become inactive. 347 */ 348 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 349 ret = irq; 350 } else { 351 if (irq < GIC_NR_SGIS) { 352 /* Lookup the source CPU for the SGI and clear this in the 353 * sgi_pending map. Return the src and clear the overall pending 354 * state on this CPU if the SGI is not pending from any CPUs. 355 */ 356 assert(s->sgi_pending[irq][cpu] != 0); 357 src = ctz32(s->sgi_pending[irq][cpu]); 358 s->sgi_pending[irq][cpu] &= ~(1 << src); 359 if (s->sgi_pending[irq][cpu] == 0) { 360 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 361 } 362 ret = irq | ((src & 0x7) << 10); 363 } else { 364 /* Clear pending state for both level and edge triggered 365 * interrupts. (level triggered interrupts with an active line 366 * remain pending, see gic_test_pending) 367 */ 368 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 369 ret = irq; 370 } 371 } 372 373 gic_activate_irq(s, cpu, irq); 374 gic_update(s); 375 DPRINTF("ACK %d\n", irq); 376 return ret; 377 } 378 379 void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val, 380 MemTxAttrs attrs) 381 { 382 if (s->security_extn && !attrs.secure) { 383 if (!GIC_TEST_GROUP(irq, (1 << cpu))) { 384 return; /* Ignore Non-secure access of Group0 IRQ */ 385 } 386 val = 0x80 | (val >> 1); /* Non-secure view */ 387 } 388 389 if (irq < GIC_INTERNAL) { 390 s->priority1[irq][cpu] = val; 391 } else { 392 s->priority2[(irq) - GIC_INTERNAL] = val; 393 } 394 } 395 396 static uint32_t gic_get_priority(GICState *s, int cpu, int irq, 397 MemTxAttrs attrs) 398 { 399 uint32_t prio = GIC_GET_PRIORITY(irq, cpu); 400 401 if (s->security_extn && !attrs.secure) { 402 if (!GIC_TEST_GROUP(irq, (1 << cpu))) { 403 return 0; /* Non-secure access cannot read priority of Group0 IRQ */ 404 } 405 prio = (prio << 1) & 0xff; /* Non-secure view */ 406 } 407 return prio; 408 } 409 410 static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, 411 MemTxAttrs attrs) 412 { 413 if (s->security_extn && !attrs.secure) { 414 if (s->priority_mask[cpu] & 0x80) { 415 /* Priority Mask in upper half */ 416 pmask = 0x80 | (pmask >> 1); 417 } else { 418 /* Non-secure write ignored if priority mask is in lower half */ 419 return; 420 } 421 } 422 s->priority_mask[cpu] = pmask; 423 } 424 425 static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs) 426 { 427 uint32_t pmask = s->priority_mask[cpu]; 428 429 if (s->security_extn && !attrs.secure) { 430 if (pmask & 0x80) { 431 /* Priority Mask in upper half, return Non-secure view */ 432 pmask = (pmask << 1) & 0xff; 433 } else { 434 /* Priority Mask in lower half, RAZ */ 435 pmask = 0; 436 } 437 } 438 return pmask; 439 } 440 441 static uint32_t gic_get_cpu_control(GICState *s, int cpu, MemTxAttrs attrs) 442 { 443 uint32_t ret = s->cpu_ctlr[cpu]; 444 445 if (s->security_extn && !attrs.secure) { 446 /* Construct the NS banked view of GICC_CTLR from the correct 447 * bits of the S banked view. We don't need to move the bypass 448 * control bits because we don't implement that (IMPDEF) part 449 * of the GIC architecture. 450 */ 451 ret = (ret & (GICC_CTLR_EN_GRP1 | GICC_CTLR_EOIMODE_NS)) >> 1; 452 } 453 return ret; 454 } 455 456 static void gic_set_cpu_control(GICState *s, int cpu, uint32_t value, 457 MemTxAttrs attrs) 458 { 459 uint32_t mask; 460 461 if (s->security_extn && !attrs.secure) { 462 /* The NS view can only write certain bits in the register; 463 * the rest are unchanged 464 */ 465 mask = GICC_CTLR_EN_GRP1; 466 if (s->revision == 2) { 467 mask |= GICC_CTLR_EOIMODE_NS; 468 } 469 s->cpu_ctlr[cpu] &= ~mask; 470 s->cpu_ctlr[cpu] |= (value << 1) & mask; 471 } else { 472 if (s->revision == 2) { 473 mask = s->security_extn ? GICC_CTLR_V2_S_MASK : GICC_CTLR_V2_MASK; 474 } else { 475 mask = s->security_extn ? GICC_CTLR_V1_S_MASK : GICC_CTLR_V1_MASK; 476 } 477 s->cpu_ctlr[cpu] = value & mask; 478 } 479 DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, " 480 "Group1 Interrupts %sabled\n", cpu, 481 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP0) ? "En" : "Dis", 482 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP1) ? "En" : "Dis"); 483 } 484 485 static uint8_t gic_get_running_priority(GICState *s, int cpu, MemTxAttrs attrs) 486 { 487 if (s->security_extn && !attrs.secure) { 488 if (s->running_priority[cpu] & 0x80) { 489 /* Running priority in upper half of range: return the Non-secure 490 * view of the priority. 491 */ 492 return s->running_priority[cpu] << 1; 493 } else { 494 /* Running priority in lower half of range: RAZ */ 495 return 0; 496 } 497 } else { 498 return s->running_priority[cpu]; 499 } 500 } 501 502 void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) 503 { 504 int cm = 1 << cpu; 505 int group; 506 507 DPRINTF("EOI %d\n", irq); 508 if (irq >= s->num_irq) { 509 /* This handles two cases: 510 * 1. If software writes the ID of a spurious interrupt [ie 1023] 511 * to the GICC_EOIR, the GIC ignores that write. 512 * 2. If software writes the number of a non-existent interrupt 513 * this must be a subcase of "value written does not match the last 514 * valid interrupt value read from the Interrupt Acknowledge 515 * register" and so this is UNPREDICTABLE. We choose to ignore it. 516 */ 517 return; 518 } 519 if (s->running_priority[cpu] == 0x100) { 520 return; /* No active IRQ. */ 521 } 522 523 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 524 /* Mark level triggered interrupts as pending if they are still 525 raised. */ 526 if (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm) 527 && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) { 528 DPRINTF("Set %d pending mask %x\n", irq, cm); 529 GIC_SET_PENDING(irq, cm); 530 } 531 } 532 533 group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm); 534 535 if (s->security_extn && !attrs.secure && !group) { 536 DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq); 537 return; 538 } 539 540 /* Secure EOI with GICC_CTLR.AckCtl == 0 when the IRQ is a Group 1 541 * interrupt is UNPREDICTABLE. We choose to handle it as if AckCtl == 1, 542 * i.e. go ahead and complete the irq anyway. 543 */ 544 545 gic_drop_prio(s, cpu, group); 546 GIC_CLEAR_ACTIVE(irq, cm); 547 gic_update(s); 548 } 549 550 static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) 551 { 552 GICState *s = (GICState *)opaque; 553 uint32_t res; 554 int irq; 555 int i; 556 int cpu; 557 int cm; 558 int mask; 559 560 cpu = gic_get_current_cpu(s); 561 cm = 1 << cpu; 562 if (offset < 0x100) { 563 if (offset == 0) { /* GICD_CTLR */ 564 if (s->security_extn && !attrs.secure) { 565 /* The NS bank of this register is just an alias of the 566 * EnableGrp1 bit in the S bank version. 567 */ 568 return extract32(s->ctlr, 1, 1); 569 } else { 570 return s->ctlr; 571 } 572 } 573 if (offset == 4) 574 /* Interrupt Controller Type Register */ 575 return ((s->num_irq / 32) - 1) 576 | ((s->num_cpu - 1) << 5) 577 | (s->security_extn << 10); 578 if (offset < 0x08) 579 return 0; 580 if (offset >= 0x80) { 581 /* Interrupt Group Registers: these RAZ/WI if this is an NS 582 * access to a GIC with the security extensions, or if the GIC 583 * doesn't have groups at all. 584 */ 585 res = 0; 586 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 587 /* Every byte offset holds 8 group status bits */ 588 irq = (offset - 0x080) * 8 + GIC_BASE_IRQ; 589 if (irq >= s->num_irq) { 590 goto bad_reg; 591 } 592 for (i = 0; i < 8; i++) { 593 if (GIC_TEST_GROUP(irq + i, cm)) { 594 res |= (1 << i); 595 } 596 } 597 } 598 return res; 599 } 600 goto bad_reg; 601 } else if (offset < 0x200) { 602 /* Interrupt Set/Clear Enable. */ 603 if (offset < 0x180) 604 irq = (offset - 0x100) * 8; 605 else 606 irq = (offset - 0x180) * 8; 607 irq += GIC_BASE_IRQ; 608 if (irq >= s->num_irq) 609 goto bad_reg; 610 res = 0; 611 for (i = 0; i < 8; i++) { 612 if (GIC_TEST_ENABLED(irq + i, cm)) { 613 res |= (1 << i); 614 } 615 } 616 } else if (offset < 0x300) { 617 /* Interrupt Set/Clear Pending. */ 618 if (offset < 0x280) 619 irq = (offset - 0x200) * 8; 620 else 621 irq = (offset - 0x280) * 8; 622 irq += GIC_BASE_IRQ; 623 if (irq >= s->num_irq) 624 goto bad_reg; 625 res = 0; 626 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 627 for (i = 0; i < 8; i++) { 628 if (gic_test_pending(s, irq + i, mask)) { 629 res |= (1 << i); 630 } 631 } 632 } else if (offset < 0x400) { 633 /* Interrupt Active. */ 634 irq = (offset - 0x300) * 8 + GIC_BASE_IRQ; 635 if (irq >= s->num_irq) 636 goto bad_reg; 637 res = 0; 638 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 639 for (i = 0; i < 8; i++) { 640 if (GIC_TEST_ACTIVE(irq + i, mask)) { 641 res |= (1 << i); 642 } 643 } 644 } else if (offset < 0x800) { 645 /* Interrupt Priority. */ 646 irq = (offset - 0x400) + GIC_BASE_IRQ; 647 if (irq >= s->num_irq) 648 goto bad_reg; 649 res = gic_get_priority(s, cpu, irq, attrs); 650 } else if (offset < 0xc00) { 651 /* Interrupt CPU Target. */ 652 if (s->num_cpu == 1 && s->revision != REV_11MPCORE) { 653 /* For uniprocessor GICs these RAZ/WI */ 654 res = 0; 655 } else { 656 irq = (offset - 0x800) + GIC_BASE_IRQ; 657 if (irq >= s->num_irq) { 658 goto bad_reg; 659 } 660 if (irq >= 29 && irq <= 31) { 661 res = cm; 662 } else { 663 res = GIC_TARGET(irq); 664 } 665 } 666 } else if (offset < 0xf00) { 667 /* Interrupt Configuration. */ 668 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 669 if (irq >= s->num_irq) 670 goto bad_reg; 671 res = 0; 672 for (i = 0; i < 4; i++) { 673 if (GIC_TEST_MODEL(irq + i)) 674 res |= (1 << (i * 2)); 675 if (GIC_TEST_EDGE_TRIGGER(irq + i)) 676 res |= (2 << (i * 2)); 677 } 678 } else if (offset < 0xf10) { 679 goto bad_reg; 680 } else if (offset < 0xf30) { 681 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 682 goto bad_reg; 683 } 684 685 if (offset < 0xf20) { 686 /* GICD_CPENDSGIRn */ 687 irq = (offset - 0xf10); 688 } else { 689 irq = (offset - 0xf20); 690 /* GICD_SPENDSGIRn */ 691 } 692 693 res = s->sgi_pending[irq][cpu]; 694 } else if (offset < 0xfd0) { 695 goto bad_reg; 696 } else if (offset < 0x1000) { 697 if (offset & 3) { 698 res = 0; 699 } else { 700 switch (s->revision) { 701 case REV_11MPCORE: 702 res = gic_id_11mpcore[(offset - 0xfd0) >> 2]; 703 break; 704 case 1: 705 res = gic_id_gicv1[(offset - 0xfd0) >> 2]; 706 break; 707 case 2: 708 res = gic_id_gicv2[(offset - 0xfd0) >> 2]; 709 break; 710 case REV_NVIC: 711 /* Shouldn't be able to get here */ 712 abort(); 713 default: 714 res = 0; 715 } 716 } 717 } else { 718 g_assert_not_reached(); 719 } 720 return res; 721 bad_reg: 722 qemu_log_mask(LOG_GUEST_ERROR, 723 "gic_dist_readb: Bad offset %x\n", (int)offset); 724 return 0; 725 } 726 727 static MemTxResult gic_dist_read(void *opaque, hwaddr offset, uint64_t *data, 728 unsigned size, MemTxAttrs attrs) 729 { 730 switch (size) { 731 case 1: 732 *data = gic_dist_readb(opaque, offset, attrs); 733 return MEMTX_OK; 734 case 2: 735 *data = gic_dist_readb(opaque, offset, attrs); 736 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 737 return MEMTX_OK; 738 case 4: 739 *data = gic_dist_readb(opaque, offset, attrs); 740 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 741 *data |= gic_dist_readb(opaque, offset + 2, attrs) << 16; 742 *data |= gic_dist_readb(opaque, offset + 3, attrs) << 24; 743 return MEMTX_OK; 744 default: 745 return MEMTX_ERROR; 746 } 747 } 748 749 static void gic_dist_writeb(void *opaque, hwaddr offset, 750 uint32_t value, MemTxAttrs attrs) 751 { 752 GICState *s = (GICState *)opaque; 753 int irq; 754 int i; 755 int cpu; 756 757 cpu = gic_get_current_cpu(s); 758 if (offset < 0x100) { 759 if (offset == 0) { 760 if (s->security_extn && !attrs.secure) { 761 /* NS version is just an alias of the S version's bit 1 */ 762 s->ctlr = deposit32(s->ctlr, 1, 1, value); 763 } else if (gic_has_groups(s)) { 764 s->ctlr = value & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1); 765 } else { 766 s->ctlr = value & GICD_CTLR_EN_GRP0; 767 } 768 DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n", 769 s->ctlr & GICD_CTLR_EN_GRP0 ? "En" : "Dis", 770 s->ctlr & GICD_CTLR_EN_GRP1 ? "En" : "Dis"); 771 } else if (offset < 4) { 772 /* ignored. */ 773 } else if (offset >= 0x80) { 774 /* Interrupt Group Registers: RAZ/WI for NS access to secure 775 * GIC, or for GICs without groups. 776 */ 777 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 778 /* Every byte offset holds 8 group status bits */ 779 irq = (offset - 0x80) * 8 + GIC_BASE_IRQ; 780 if (irq >= s->num_irq) { 781 goto bad_reg; 782 } 783 for (i = 0; i < 8; i++) { 784 /* Group bits are banked for private interrupts */ 785 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 786 if (value & (1 << i)) { 787 /* Group1 (Non-secure) */ 788 GIC_SET_GROUP(irq + i, cm); 789 } else { 790 /* Group0 (Secure) */ 791 GIC_CLEAR_GROUP(irq + i, cm); 792 } 793 } 794 } 795 } else { 796 goto bad_reg; 797 } 798 } else if (offset < 0x180) { 799 /* Interrupt Set Enable. */ 800 irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; 801 if (irq >= s->num_irq) 802 goto bad_reg; 803 if (irq < GIC_NR_SGIS) { 804 value = 0xff; 805 } 806 807 for (i = 0; i < 8; i++) { 808 if (value & (1 << i)) { 809 int mask = 810 (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq + i); 811 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 812 813 if (!GIC_TEST_ENABLED(irq + i, cm)) { 814 DPRINTF("Enabled IRQ %d\n", irq + i); 815 } 816 GIC_SET_ENABLED(irq + i, cm); 817 /* If a raised level triggered IRQ enabled then mark 818 is as pending. */ 819 if (GIC_TEST_LEVEL(irq + i, mask) 820 && !GIC_TEST_EDGE_TRIGGER(irq + i)) { 821 DPRINTF("Set %d pending mask %x\n", irq + i, mask); 822 GIC_SET_PENDING(irq + i, mask); 823 } 824 } 825 } 826 } else if (offset < 0x200) { 827 /* Interrupt Clear Enable. */ 828 irq = (offset - 0x180) * 8 + GIC_BASE_IRQ; 829 if (irq >= s->num_irq) 830 goto bad_reg; 831 if (irq < GIC_NR_SGIS) { 832 value = 0; 833 } 834 835 for (i = 0; i < 8; i++) { 836 if (value & (1 << i)) { 837 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 838 839 if (GIC_TEST_ENABLED(irq + i, cm)) { 840 DPRINTF("Disabled IRQ %d\n", irq + i); 841 } 842 GIC_CLEAR_ENABLED(irq + i, cm); 843 } 844 } 845 } else if (offset < 0x280) { 846 /* Interrupt Set Pending. */ 847 irq = (offset - 0x200) * 8 + GIC_BASE_IRQ; 848 if (irq >= s->num_irq) 849 goto bad_reg; 850 if (irq < GIC_NR_SGIS) { 851 value = 0; 852 } 853 854 for (i = 0; i < 8; i++) { 855 if (value & (1 << i)) { 856 GIC_SET_PENDING(irq + i, GIC_TARGET(irq + i)); 857 } 858 } 859 } else if (offset < 0x300) { 860 /* Interrupt Clear Pending. */ 861 irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; 862 if (irq >= s->num_irq) 863 goto bad_reg; 864 if (irq < GIC_NR_SGIS) { 865 value = 0; 866 } 867 868 for (i = 0; i < 8; i++) { 869 /* ??? This currently clears the pending bit for all CPUs, even 870 for per-CPU interrupts. It's unclear whether this is the 871 corect behavior. */ 872 if (value & (1 << i)) { 873 GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK); 874 } 875 } 876 } else if (offset < 0x400) { 877 /* Interrupt Active. */ 878 goto bad_reg; 879 } else if (offset < 0x800) { 880 /* Interrupt Priority. */ 881 irq = (offset - 0x400) + GIC_BASE_IRQ; 882 if (irq >= s->num_irq) 883 goto bad_reg; 884 gic_set_priority(s, cpu, irq, value, attrs); 885 } else if (offset < 0xc00) { 886 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the 887 * annoying exception of the 11MPCore's GIC. 888 */ 889 if (s->num_cpu != 1 || s->revision == REV_11MPCORE) { 890 irq = (offset - 0x800) + GIC_BASE_IRQ; 891 if (irq >= s->num_irq) { 892 goto bad_reg; 893 } 894 if (irq < 29) { 895 value = 0; 896 } else if (irq < GIC_INTERNAL) { 897 value = ALL_CPU_MASK; 898 } 899 s->irq_target[irq] = value & ALL_CPU_MASK; 900 } 901 } else if (offset < 0xf00) { 902 /* Interrupt Configuration. */ 903 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 904 if (irq >= s->num_irq) 905 goto bad_reg; 906 if (irq < GIC_NR_SGIS) 907 value |= 0xaa; 908 for (i = 0; i < 4; i++) { 909 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 910 if (value & (1 << (i * 2))) { 911 GIC_SET_MODEL(irq + i); 912 } else { 913 GIC_CLEAR_MODEL(irq + i); 914 } 915 } 916 if (value & (2 << (i * 2))) { 917 GIC_SET_EDGE_TRIGGER(irq + i); 918 } else { 919 GIC_CLEAR_EDGE_TRIGGER(irq + i); 920 } 921 } 922 } else if (offset < 0xf10) { 923 /* 0xf00 is only handled for 32-bit writes. */ 924 goto bad_reg; 925 } else if (offset < 0xf20) { 926 /* GICD_CPENDSGIRn */ 927 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 928 goto bad_reg; 929 } 930 irq = (offset - 0xf10); 931 932 s->sgi_pending[irq][cpu] &= ~value; 933 if (s->sgi_pending[irq][cpu] == 0) { 934 GIC_CLEAR_PENDING(irq, 1 << cpu); 935 } 936 } else if (offset < 0xf30) { 937 /* GICD_SPENDSGIRn */ 938 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 939 goto bad_reg; 940 } 941 irq = (offset - 0xf20); 942 943 GIC_SET_PENDING(irq, 1 << cpu); 944 s->sgi_pending[irq][cpu] |= value; 945 } else { 946 goto bad_reg; 947 } 948 gic_update(s); 949 return; 950 bad_reg: 951 qemu_log_mask(LOG_GUEST_ERROR, 952 "gic_dist_writeb: Bad offset %x\n", (int)offset); 953 } 954 955 static void gic_dist_writew(void *opaque, hwaddr offset, 956 uint32_t value, MemTxAttrs attrs) 957 { 958 gic_dist_writeb(opaque, offset, value & 0xff, attrs); 959 gic_dist_writeb(opaque, offset + 1, value >> 8, attrs); 960 } 961 962 static void gic_dist_writel(void *opaque, hwaddr offset, 963 uint32_t value, MemTxAttrs attrs) 964 { 965 GICState *s = (GICState *)opaque; 966 if (offset == 0xf00) { 967 int cpu; 968 int irq; 969 int mask; 970 int target_cpu; 971 972 cpu = gic_get_current_cpu(s); 973 irq = value & 0x3ff; 974 switch ((value >> 24) & 3) { 975 case 0: 976 mask = (value >> 16) & ALL_CPU_MASK; 977 break; 978 case 1: 979 mask = ALL_CPU_MASK ^ (1 << cpu); 980 break; 981 case 2: 982 mask = 1 << cpu; 983 break; 984 default: 985 DPRINTF("Bad Soft Int target filter\n"); 986 mask = ALL_CPU_MASK; 987 break; 988 } 989 GIC_SET_PENDING(irq, mask); 990 target_cpu = ctz32(mask); 991 while (target_cpu < GIC_NCPU) { 992 s->sgi_pending[irq][target_cpu] |= (1 << cpu); 993 mask &= ~(1 << target_cpu); 994 target_cpu = ctz32(mask); 995 } 996 gic_update(s); 997 return; 998 } 999 gic_dist_writew(opaque, offset, value & 0xffff, attrs); 1000 gic_dist_writew(opaque, offset + 2, value >> 16, attrs); 1001 } 1002 1003 static MemTxResult gic_dist_write(void *opaque, hwaddr offset, uint64_t data, 1004 unsigned size, MemTxAttrs attrs) 1005 { 1006 switch (size) { 1007 case 1: 1008 gic_dist_writeb(opaque, offset, data, attrs); 1009 return MEMTX_OK; 1010 case 2: 1011 gic_dist_writew(opaque, offset, data, attrs); 1012 return MEMTX_OK; 1013 case 4: 1014 gic_dist_writel(opaque, offset, data, attrs); 1015 return MEMTX_OK; 1016 default: 1017 return MEMTX_ERROR; 1018 } 1019 } 1020 1021 static inline uint32_t gic_apr_ns_view(GICState *s, int cpu, int regno) 1022 { 1023 /* Return the Nonsecure view of GICC_APR<regno>. This is the 1024 * second half of GICC_NSAPR. 1025 */ 1026 switch (GIC_MIN_BPR) { 1027 case 0: 1028 if (regno < 2) { 1029 return s->nsapr[regno + 2][cpu]; 1030 } 1031 break; 1032 case 1: 1033 if (regno == 0) { 1034 return s->nsapr[regno + 1][cpu]; 1035 } 1036 break; 1037 case 2: 1038 if (regno == 0) { 1039 return extract32(s->nsapr[0][cpu], 16, 16); 1040 } 1041 break; 1042 case 3: 1043 if (regno == 0) { 1044 return extract32(s->nsapr[0][cpu], 8, 8); 1045 } 1046 break; 1047 default: 1048 g_assert_not_reached(); 1049 } 1050 return 0; 1051 } 1052 1053 static inline void gic_apr_write_ns_view(GICState *s, int cpu, int regno, 1054 uint32_t value) 1055 { 1056 /* Write the Nonsecure view of GICC_APR<regno>. */ 1057 switch (GIC_MIN_BPR) { 1058 case 0: 1059 if (regno < 2) { 1060 s->nsapr[regno + 2][cpu] = value; 1061 } 1062 break; 1063 case 1: 1064 if (regno == 0) { 1065 s->nsapr[regno + 1][cpu] = value; 1066 } 1067 break; 1068 case 2: 1069 if (regno == 0) { 1070 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 16, 16, value); 1071 } 1072 break; 1073 case 3: 1074 if (regno == 0) { 1075 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 8, 8, value); 1076 } 1077 break; 1078 default: 1079 g_assert_not_reached(); 1080 } 1081 } 1082 1083 static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset, 1084 uint64_t *data, MemTxAttrs attrs) 1085 { 1086 switch (offset) { 1087 case 0x00: /* Control */ 1088 *data = gic_get_cpu_control(s, cpu, attrs); 1089 break; 1090 case 0x04: /* Priority mask */ 1091 *data = gic_get_priority_mask(s, cpu, attrs); 1092 break; 1093 case 0x08: /* Binary Point */ 1094 if (s->security_extn && !attrs.secure) { 1095 /* BPR is banked. Non-secure copy stored in ABPR. */ 1096 *data = s->abpr[cpu]; 1097 } else { 1098 *data = s->bpr[cpu]; 1099 } 1100 break; 1101 case 0x0c: /* Acknowledge */ 1102 *data = gic_acknowledge_irq(s, cpu, attrs); 1103 break; 1104 case 0x14: /* Running Priority */ 1105 *data = gic_get_running_priority(s, cpu, attrs); 1106 break; 1107 case 0x18: /* Highest Pending Interrupt */ 1108 *data = gic_get_current_pending_irq(s, cpu, attrs); 1109 break; 1110 case 0x1c: /* Aliased Binary Point */ 1111 /* GIC v2, no security: ABPR 1112 * GIC v1, no security: not implemented (RAZ/WI) 1113 * With security extensions, secure access: ABPR (alias of NS BPR) 1114 * With security extensions, nonsecure access: RAZ/WI 1115 */ 1116 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 1117 *data = 0; 1118 } else { 1119 *data = s->abpr[cpu]; 1120 } 1121 break; 1122 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 1123 { 1124 int regno = (offset - 0xd0) / 4; 1125 1126 if (regno >= GIC_NR_APRS || s->revision != 2) { 1127 *data = 0; 1128 } else if (s->security_extn && !attrs.secure) { 1129 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ 1130 *data = gic_apr_ns_view(s, regno, cpu); 1131 } else { 1132 *data = s->apr[regno][cpu]; 1133 } 1134 break; 1135 } 1136 case 0xe0: case 0xe4: case 0xe8: case 0xec: 1137 { 1138 int regno = (offset - 0xe0) / 4; 1139 1140 if (regno >= GIC_NR_APRS || s->revision != 2 || !gic_has_groups(s) || 1141 (s->security_extn && !attrs.secure)) { 1142 *data = 0; 1143 } else { 1144 *data = s->nsapr[regno][cpu]; 1145 } 1146 break; 1147 } 1148 default: 1149 qemu_log_mask(LOG_GUEST_ERROR, 1150 "gic_cpu_read: Bad offset %x\n", (int)offset); 1151 return MEMTX_ERROR; 1152 } 1153 return MEMTX_OK; 1154 } 1155 1156 static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset, 1157 uint32_t value, MemTxAttrs attrs) 1158 { 1159 switch (offset) { 1160 case 0x00: /* Control */ 1161 gic_set_cpu_control(s, cpu, value, attrs); 1162 break; 1163 case 0x04: /* Priority mask */ 1164 gic_set_priority_mask(s, cpu, value, attrs); 1165 break; 1166 case 0x08: /* Binary Point */ 1167 if (s->security_extn && !attrs.secure) { 1168 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 1169 } else { 1170 s->bpr[cpu] = MAX(value & 0x7, GIC_MIN_BPR); 1171 } 1172 break; 1173 case 0x10: /* End Of Interrupt */ 1174 gic_complete_irq(s, cpu, value & 0x3ff, attrs); 1175 return MEMTX_OK; 1176 case 0x1c: /* Aliased Binary Point */ 1177 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 1178 /* unimplemented, or NS access: RAZ/WI */ 1179 return MEMTX_OK; 1180 } else { 1181 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 1182 } 1183 break; 1184 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 1185 { 1186 int regno = (offset - 0xd0) / 4; 1187 1188 if (regno >= GIC_NR_APRS || s->revision != 2) { 1189 return MEMTX_OK; 1190 } 1191 if (s->security_extn && !attrs.secure) { 1192 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ 1193 gic_apr_write_ns_view(s, regno, cpu, value); 1194 } else { 1195 s->apr[regno][cpu] = value; 1196 } 1197 break; 1198 } 1199 case 0xe0: case 0xe4: case 0xe8: case 0xec: 1200 { 1201 int regno = (offset - 0xe0) / 4; 1202 1203 if (regno >= GIC_NR_APRS || s->revision != 2) { 1204 return MEMTX_OK; 1205 } 1206 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 1207 return MEMTX_OK; 1208 } 1209 s->nsapr[regno][cpu] = value; 1210 break; 1211 } 1212 default: 1213 qemu_log_mask(LOG_GUEST_ERROR, 1214 "gic_cpu_write: Bad offset %x\n", (int)offset); 1215 return MEMTX_ERROR; 1216 } 1217 gic_update(s); 1218 return MEMTX_OK; 1219 } 1220 1221 /* Wrappers to read/write the GIC CPU interface for the current CPU */ 1222 static MemTxResult gic_thiscpu_read(void *opaque, hwaddr addr, uint64_t *data, 1223 unsigned size, MemTxAttrs attrs) 1224 { 1225 GICState *s = (GICState *)opaque; 1226 return gic_cpu_read(s, gic_get_current_cpu(s), addr, data, attrs); 1227 } 1228 1229 static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, 1230 uint64_t value, unsigned size, 1231 MemTxAttrs attrs) 1232 { 1233 GICState *s = (GICState *)opaque; 1234 return gic_cpu_write(s, gic_get_current_cpu(s), addr, value, attrs); 1235 } 1236 1237 /* Wrappers to read/write the GIC CPU interface for a specific CPU. 1238 * These just decode the opaque pointer into GICState* + cpu id. 1239 */ 1240 static MemTxResult gic_do_cpu_read(void *opaque, hwaddr addr, uint64_t *data, 1241 unsigned size, MemTxAttrs attrs) 1242 { 1243 GICState **backref = (GICState **)opaque; 1244 GICState *s = *backref; 1245 int id = (backref - s->backref); 1246 return gic_cpu_read(s, id, addr, data, attrs); 1247 } 1248 1249 static MemTxResult gic_do_cpu_write(void *opaque, hwaddr addr, 1250 uint64_t value, unsigned size, 1251 MemTxAttrs attrs) 1252 { 1253 GICState **backref = (GICState **)opaque; 1254 GICState *s = *backref; 1255 int id = (backref - s->backref); 1256 return gic_cpu_write(s, id, addr, value, attrs); 1257 } 1258 1259 static const MemoryRegionOps gic_ops[2] = { 1260 { 1261 .read_with_attrs = gic_dist_read, 1262 .write_with_attrs = gic_dist_write, 1263 .endianness = DEVICE_NATIVE_ENDIAN, 1264 }, 1265 { 1266 .read_with_attrs = gic_thiscpu_read, 1267 .write_with_attrs = gic_thiscpu_write, 1268 .endianness = DEVICE_NATIVE_ENDIAN, 1269 } 1270 }; 1271 1272 static const MemoryRegionOps gic_cpu_ops = { 1273 .read_with_attrs = gic_do_cpu_read, 1274 .write_with_attrs = gic_do_cpu_write, 1275 .endianness = DEVICE_NATIVE_ENDIAN, 1276 }; 1277 1278 /* This function is used by nvic model */ 1279 void gic_init_irqs_and_distributor(GICState *s) 1280 { 1281 gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops); 1282 } 1283 1284 static void arm_gic_realize(DeviceState *dev, Error **errp) 1285 { 1286 /* Device instance realize function for the GIC sysbus device */ 1287 int i; 1288 GICState *s = ARM_GIC(dev); 1289 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1290 ARMGICClass *agc = ARM_GIC_GET_CLASS(s); 1291 Error *local_err = NULL; 1292 1293 agc->parent_realize(dev, &local_err); 1294 if (local_err) { 1295 error_propagate(errp, local_err); 1296 return; 1297 } 1298 1299 /* This creates distributor and main CPU interface (s->cpuiomem[0]) */ 1300 gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops); 1301 1302 /* Extra core-specific regions for the CPU interfaces. This is 1303 * necessary for "franken-GIC" implementations, for example on 1304 * Exynos 4. 1305 * NB that the memory region size of 0x100 applies for the 11MPCore 1306 * and also cores following the GIC v1 spec (ie A9). 1307 * GIC v2 defines a larger memory region (0x1000) so this will need 1308 * to be extended when we implement A15. 1309 */ 1310 for (i = 0; i < s->num_cpu; i++) { 1311 s->backref[i] = s; 1312 memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops, 1313 &s->backref[i], "gic_cpu", 0x100); 1314 sysbus_init_mmio(sbd, &s->cpuiomem[i+1]); 1315 } 1316 } 1317 1318 static void arm_gic_class_init(ObjectClass *klass, void *data) 1319 { 1320 DeviceClass *dc = DEVICE_CLASS(klass); 1321 ARMGICClass *agc = ARM_GIC_CLASS(klass); 1322 1323 agc->parent_realize = dc->realize; 1324 dc->realize = arm_gic_realize; 1325 } 1326 1327 static const TypeInfo arm_gic_info = { 1328 .name = TYPE_ARM_GIC, 1329 .parent = TYPE_ARM_GIC_COMMON, 1330 .instance_size = sizeof(GICState), 1331 .class_init = arm_gic_class_init, 1332 .class_size = sizeof(ARMGICClass), 1333 }; 1334 1335 static void arm_gic_register_types(void) 1336 { 1337 type_register_static(&arm_gic_info); 1338 } 1339 1340 type_init(arm_gic_register_types) 1341