1 /* 2 * ARM Generic/Distributed Interrupt Controller 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 /* This file contains implementation code for the RealView EB interrupt 11 * controller, MPCore distributed interrupt controller and ARMv7-M 12 * Nested Vectored Interrupt Controller. 13 * It is compiled in two ways: 14 * (1) as a standalone file to produce a sysbus device which is a GIC 15 * that can be used on the realview board and as one of the builtin 16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc) 17 * (2) by being directly #included into armv7m_nvic.c to produce the 18 * armv7m_nvic device. 19 */ 20 21 #include "hw/sysbus.h" 22 #include "gic_internal.h" 23 #include "qom/cpu.h" 24 25 //#define DEBUG_GIC 26 27 #ifdef DEBUG_GIC 28 #define DPRINTF(fmt, ...) \ 29 do { fprintf(stderr, "arm_gic: " fmt , ## __VA_ARGS__); } while (0) 30 #else 31 #define DPRINTF(fmt, ...) do {} while(0) 32 #endif 33 34 static const uint8_t gic_id[] = { 35 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 36 }; 37 38 #define NUM_CPU(s) ((s)->num_cpu) 39 40 static inline int gic_get_current_cpu(GICState *s) 41 { 42 if (s->num_cpu > 1) { 43 return current_cpu->cpu_index; 44 } 45 return 0; 46 } 47 48 /* Return true if this GIC config has interrupt groups, which is 49 * true if we're a GICv2, or a GICv1 with the security extensions. 50 */ 51 static inline bool gic_has_groups(GICState *s) 52 { 53 return s->revision == 2 || s->security_extn; 54 } 55 56 /* TODO: Many places that call this routine could be optimized. */ 57 /* Update interrupt status after enabled or pending bits have been changed. */ 58 void gic_update(GICState *s) 59 { 60 int best_irq; 61 int best_prio; 62 int irq; 63 int level; 64 int cpu; 65 int cm; 66 67 for (cpu = 0; cpu < NUM_CPU(s); cpu++) { 68 cm = 1 << cpu; 69 s->current_pending[cpu] = 1023; 70 if (!(s->ctlr & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1)) 71 || !(s->cpu_ctlr[cpu] & (GICC_CTLR_EN_GRP0 | GICC_CTLR_EN_GRP1))) { 72 qemu_irq_lower(s->parent_irq[cpu]); 73 return; 74 } 75 best_prio = 0x100; 76 best_irq = 1023; 77 for (irq = 0; irq < s->num_irq; irq++) { 78 if (GIC_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm) && 79 (irq < GIC_INTERNAL || GIC_TARGET(irq) & cm)) { 80 if (GIC_GET_PRIORITY(irq, cpu) < best_prio) { 81 best_prio = GIC_GET_PRIORITY(irq, cpu); 82 best_irq = irq; 83 } 84 } 85 } 86 level = 0; 87 if (best_prio < s->priority_mask[cpu]) { 88 s->current_pending[cpu] = best_irq; 89 if (best_prio < s->running_priority[cpu]) { 90 DPRINTF("Raised pending IRQ %d (cpu %d)\n", best_irq, cpu); 91 level = 1; 92 } 93 } 94 qemu_set_irq(s->parent_irq[cpu], level); 95 } 96 } 97 98 void gic_set_pending_private(GICState *s, int cpu, int irq) 99 { 100 int cm = 1 << cpu; 101 102 if (gic_test_pending(s, irq, cm)) { 103 return; 104 } 105 106 DPRINTF("Set %d pending cpu %d\n", irq, cpu); 107 GIC_SET_PENDING(irq, cm); 108 gic_update(s); 109 } 110 111 static void gic_set_irq_11mpcore(GICState *s, int irq, int level, 112 int cm, int target) 113 { 114 if (level) { 115 GIC_SET_LEVEL(irq, cm); 116 if (GIC_TEST_EDGE_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) { 117 DPRINTF("Set %d pending mask %x\n", irq, target); 118 GIC_SET_PENDING(irq, target); 119 } 120 } else { 121 GIC_CLEAR_LEVEL(irq, cm); 122 } 123 } 124 125 static void gic_set_irq_generic(GICState *s, int irq, int level, 126 int cm, int target) 127 { 128 if (level) { 129 GIC_SET_LEVEL(irq, cm); 130 DPRINTF("Set %d pending mask %x\n", irq, target); 131 if (GIC_TEST_EDGE_TRIGGER(irq)) { 132 GIC_SET_PENDING(irq, target); 133 } 134 } else { 135 GIC_CLEAR_LEVEL(irq, cm); 136 } 137 } 138 139 /* Process a change in an external IRQ input. */ 140 static void gic_set_irq(void *opaque, int irq, int level) 141 { 142 /* Meaning of the 'irq' parameter: 143 * [0..N-1] : external interrupts 144 * [N..N+31] : PPI (internal) interrupts for CPU 0 145 * [N+32..N+63] : PPI (internal interrupts for CPU 1 146 * ... 147 */ 148 GICState *s = (GICState *)opaque; 149 int cm, target; 150 if (irq < (s->num_irq - GIC_INTERNAL)) { 151 /* The first external input line is internal interrupt 32. */ 152 cm = ALL_CPU_MASK; 153 irq += GIC_INTERNAL; 154 target = GIC_TARGET(irq); 155 } else { 156 int cpu; 157 irq -= (s->num_irq - GIC_INTERNAL); 158 cpu = irq / GIC_INTERNAL; 159 irq %= GIC_INTERNAL; 160 cm = 1 << cpu; 161 target = cm; 162 } 163 164 assert(irq >= GIC_NR_SGIS); 165 166 if (level == GIC_TEST_LEVEL(irq, cm)) { 167 return; 168 } 169 170 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 171 gic_set_irq_11mpcore(s, irq, level, cm, target); 172 } else { 173 gic_set_irq_generic(s, irq, level, cm, target); 174 } 175 176 gic_update(s); 177 } 178 179 static uint16_t gic_get_current_pending_irq(GICState *s, int cpu, 180 MemTxAttrs attrs) 181 { 182 uint16_t pending_irq = s->current_pending[cpu]; 183 184 if (pending_irq < GIC_MAXIRQ && gic_has_groups(s)) { 185 int group = GIC_TEST_GROUP(pending_irq, (1 << cpu)); 186 /* On a GIC without the security extensions, reading this register 187 * behaves in the same way as a secure access to a GIC with them. 188 */ 189 bool secure = !s->security_extn || attrs.secure; 190 191 if (group == 0 && !secure) { 192 /* Group0 interrupts hidden from Non-secure access */ 193 return 1023; 194 } 195 if (group == 1 && secure && !(s->cpu_ctlr[cpu] & GICC_CTLR_ACK_CTL)) { 196 /* Group1 interrupts only seen by Secure access if 197 * AckCtl bit set. 198 */ 199 return 1022; 200 } 201 } 202 return pending_irq; 203 } 204 205 static void gic_set_running_irq(GICState *s, int cpu, int irq) 206 { 207 s->running_irq[cpu] = irq; 208 if (irq == 1023) { 209 s->running_priority[cpu] = 0x100; 210 } else { 211 s->running_priority[cpu] = GIC_GET_PRIORITY(irq, cpu); 212 } 213 gic_update(s); 214 } 215 216 uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs) 217 { 218 int ret, irq, src; 219 int cm = 1 << cpu; 220 221 /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately 222 * for the case where this GIC supports grouping and the pending interrupt 223 * is in the wrong group. 224 */ 225 irq = gic_get_current_pending_irq(s, cpu, attrs);; 226 227 if (irq >= GIC_MAXIRQ) { 228 DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq); 229 return irq; 230 } 231 232 if (GIC_GET_PRIORITY(irq, cpu) >= s->running_priority[cpu]) { 233 DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq); 234 return 1023; 235 } 236 s->last_active[irq][cpu] = s->running_irq[cpu]; 237 238 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 239 /* Clear pending flags for both level and edge triggered interrupts. 240 * Level triggered IRQs will be reasserted once they become inactive. 241 */ 242 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 243 ret = irq; 244 } else { 245 if (irq < GIC_NR_SGIS) { 246 /* Lookup the source CPU for the SGI and clear this in the 247 * sgi_pending map. Return the src and clear the overall pending 248 * state on this CPU if the SGI is not pending from any CPUs. 249 */ 250 assert(s->sgi_pending[irq][cpu] != 0); 251 src = ctz32(s->sgi_pending[irq][cpu]); 252 s->sgi_pending[irq][cpu] &= ~(1 << src); 253 if (s->sgi_pending[irq][cpu] == 0) { 254 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 255 } 256 ret = irq | ((src & 0x7) << 10); 257 } else { 258 /* Clear pending state for both level and edge triggered 259 * interrupts. (level triggered interrupts with an active line 260 * remain pending, see gic_test_pending) 261 */ 262 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 263 ret = irq; 264 } 265 } 266 267 gic_set_running_irq(s, cpu, irq); 268 DPRINTF("ACK %d\n", irq); 269 return ret; 270 } 271 272 void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val, 273 MemTxAttrs attrs) 274 { 275 if (s->security_extn && !attrs.secure) { 276 if (!GIC_TEST_GROUP(irq, (1 << cpu))) { 277 return; /* Ignore Non-secure access of Group0 IRQ */ 278 } 279 val = 0x80 | (val >> 1); /* Non-secure view */ 280 } 281 282 if (irq < GIC_INTERNAL) { 283 s->priority1[irq][cpu] = val; 284 } else { 285 s->priority2[(irq) - GIC_INTERNAL] = val; 286 } 287 } 288 289 static uint32_t gic_get_priority(GICState *s, int cpu, int irq, 290 MemTxAttrs attrs) 291 { 292 uint32_t prio = GIC_GET_PRIORITY(irq, cpu); 293 294 if (s->security_extn && !attrs.secure) { 295 if (!GIC_TEST_GROUP(irq, (1 << cpu))) { 296 return 0; /* Non-secure access cannot read priority of Group0 IRQ */ 297 } 298 prio = (prio << 1) & 0xff; /* Non-secure view */ 299 } 300 return prio; 301 } 302 303 static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, 304 MemTxAttrs attrs) 305 { 306 if (s->security_extn && !attrs.secure) { 307 if (s->priority_mask[cpu] & 0x80) { 308 /* Priority Mask in upper half */ 309 pmask = 0x80 | (pmask >> 1); 310 } else { 311 /* Non-secure write ignored if priority mask is in lower half */ 312 return; 313 } 314 } 315 s->priority_mask[cpu] = pmask; 316 } 317 318 static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs) 319 { 320 uint32_t pmask = s->priority_mask[cpu]; 321 322 if (s->security_extn && !attrs.secure) { 323 if (pmask & 0x80) { 324 /* Priority Mask in upper half, return Non-secure view */ 325 pmask = (pmask << 1) & 0xff; 326 } else { 327 /* Priority Mask in lower half, RAZ */ 328 pmask = 0; 329 } 330 } 331 return pmask; 332 } 333 334 static uint32_t gic_get_cpu_control(GICState *s, int cpu, MemTxAttrs attrs) 335 { 336 uint32_t ret = s->cpu_ctlr[cpu]; 337 338 if (s->security_extn && !attrs.secure) { 339 /* Construct the NS banked view of GICC_CTLR from the correct 340 * bits of the S banked view. We don't need to move the bypass 341 * control bits because we don't implement that (IMPDEF) part 342 * of the GIC architecture. 343 */ 344 ret = (ret & (GICC_CTLR_EN_GRP1 | GICC_CTLR_EOIMODE_NS)) >> 1; 345 } 346 return ret; 347 } 348 349 static void gic_set_cpu_control(GICState *s, int cpu, uint32_t value, 350 MemTxAttrs attrs) 351 { 352 uint32_t mask; 353 354 if (s->security_extn && !attrs.secure) { 355 /* The NS view can only write certain bits in the register; 356 * the rest are unchanged 357 */ 358 mask = GICC_CTLR_EN_GRP1; 359 if (s->revision == 2) { 360 mask |= GICC_CTLR_EOIMODE_NS; 361 } 362 s->cpu_ctlr[cpu] &= ~mask; 363 s->cpu_ctlr[cpu] |= (value << 1) & mask; 364 } else { 365 if (s->revision == 2) { 366 mask = s->security_extn ? GICC_CTLR_V2_S_MASK : GICC_CTLR_V2_MASK; 367 } else { 368 mask = s->security_extn ? GICC_CTLR_V1_S_MASK : GICC_CTLR_V1_MASK; 369 } 370 s->cpu_ctlr[cpu] = value & mask; 371 } 372 DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, " 373 "Group1 Interrupts %sabled\n", cpu, 374 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP0) ? "En" : "Dis", 375 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP1) ? "En" : "Dis"); 376 } 377 378 static uint8_t gic_get_running_priority(GICState *s, int cpu, MemTxAttrs attrs) 379 { 380 if (s->security_extn && !attrs.secure) { 381 if (s->running_priority[cpu] & 0x80) { 382 /* Running priority in upper half of range: return the Non-secure 383 * view of the priority. 384 */ 385 return s->running_priority[cpu] << 1; 386 } else { 387 /* Running priority in lower half of range: RAZ */ 388 return 0; 389 } 390 } else { 391 return s->running_priority[cpu]; 392 } 393 } 394 395 void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) 396 { 397 int update = 0; 398 int cm = 1 << cpu; 399 DPRINTF("EOI %d\n", irq); 400 if (irq >= s->num_irq) { 401 /* This handles two cases: 402 * 1. If software writes the ID of a spurious interrupt [ie 1023] 403 * to the GICC_EOIR, the GIC ignores that write. 404 * 2. If software writes the number of a non-existent interrupt 405 * this must be a subcase of "value written does not match the last 406 * valid interrupt value read from the Interrupt Acknowledge 407 * register" and so this is UNPREDICTABLE. We choose to ignore it. 408 */ 409 return; 410 } 411 if (s->running_irq[cpu] == 1023) 412 return; /* No active IRQ. */ 413 414 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 415 /* Mark level triggered interrupts as pending if they are still 416 raised. */ 417 if (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm) 418 && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) { 419 DPRINTF("Set %d pending mask %x\n", irq, cm); 420 GIC_SET_PENDING(irq, cm); 421 update = 1; 422 } 423 } 424 425 if (s->security_extn && !attrs.secure && !GIC_TEST_GROUP(irq, cm)) { 426 DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq); 427 return; 428 } 429 430 /* Secure EOI with GICC_CTLR.AckCtl == 0 when the IRQ is a Group 1 431 * interrupt is UNPREDICTABLE. We choose to handle it as if AckCtl == 1, 432 * i.e. go ahead and complete the irq anyway. 433 */ 434 435 if (irq != s->running_irq[cpu]) { 436 /* Complete an IRQ that is not currently running. */ 437 int tmp = s->running_irq[cpu]; 438 while (s->last_active[tmp][cpu] != 1023) { 439 if (s->last_active[tmp][cpu] == irq) { 440 s->last_active[tmp][cpu] = s->last_active[irq][cpu]; 441 break; 442 } 443 tmp = s->last_active[tmp][cpu]; 444 } 445 if (update) { 446 gic_update(s); 447 } 448 } else { 449 /* Complete the current running IRQ. */ 450 gic_set_running_irq(s, cpu, s->last_active[s->running_irq[cpu]][cpu]); 451 } 452 } 453 454 static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) 455 { 456 GICState *s = (GICState *)opaque; 457 uint32_t res; 458 int irq; 459 int i; 460 int cpu; 461 int cm; 462 int mask; 463 464 cpu = gic_get_current_cpu(s); 465 cm = 1 << cpu; 466 if (offset < 0x100) { 467 if (offset == 0) { /* GICD_CTLR */ 468 if (s->security_extn && !attrs.secure) { 469 /* The NS bank of this register is just an alias of the 470 * EnableGrp1 bit in the S bank version. 471 */ 472 return extract32(s->ctlr, 1, 1); 473 } else { 474 return s->ctlr; 475 } 476 } 477 if (offset == 4) 478 /* Interrupt Controller Type Register */ 479 return ((s->num_irq / 32) - 1) 480 | ((NUM_CPU(s) - 1) << 5) 481 | (s->security_extn << 10); 482 if (offset < 0x08) 483 return 0; 484 if (offset >= 0x80) { 485 /* Interrupt Group Registers: these RAZ/WI if this is an NS 486 * access to a GIC with the security extensions, or if the GIC 487 * doesn't have groups at all. 488 */ 489 res = 0; 490 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 491 /* Every byte offset holds 8 group status bits */ 492 irq = (offset - 0x080) * 8 + GIC_BASE_IRQ; 493 if (irq >= s->num_irq) { 494 goto bad_reg; 495 } 496 for (i = 0; i < 8; i++) { 497 if (GIC_TEST_GROUP(irq + i, cm)) { 498 res |= (1 << i); 499 } 500 } 501 } 502 return res; 503 } 504 goto bad_reg; 505 } else if (offset < 0x200) { 506 /* Interrupt Set/Clear Enable. */ 507 if (offset < 0x180) 508 irq = (offset - 0x100) * 8; 509 else 510 irq = (offset - 0x180) * 8; 511 irq += GIC_BASE_IRQ; 512 if (irq >= s->num_irq) 513 goto bad_reg; 514 res = 0; 515 for (i = 0; i < 8; i++) { 516 if (GIC_TEST_ENABLED(irq + i, cm)) { 517 res |= (1 << i); 518 } 519 } 520 } else if (offset < 0x300) { 521 /* Interrupt Set/Clear Pending. */ 522 if (offset < 0x280) 523 irq = (offset - 0x200) * 8; 524 else 525 irq = (offset - 0x280) * 8; 526 irq += GIC_BASE_IRQ; 527 if (irq >= s->num_irq) 528 goto bad_reg; 529 res = 0; 530 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 531 for (i = 0; i < 8; i++) { 532 if (gic_test_pending(s, irq + i, mask)) { 533 res |= (1 << i); 534 } 535 } 536 } else if (offset < 0x400) { 537 /* Interrupt Active. */ 538 irq = (offset - 0x300) * 8 + GIC_BASE_IRQ; 539 if (irq >= s->num_irq) 540 goto bad_reg; 541 res = 0; 542 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 543 for (i = 0; i < 8; i++) { 544 if (GIC_TEST_ACTIVE(irq + i, mask)) { 545 res |= (1 << i); 546 } 547 } 548 } else if (offset < 0x800) { 549 /* Interrupt Priority. */ 550 irq = (offset - 0x400) + GIC_BASE_IRQ; 551 if (irq >= s->num_irq) 552 goto bad_reg; 553 res = gic_get_priority(s, cpu, irq, attrs); 554 } else if (offset < 0xc00) { 555 /* Interrupt CPU Target. */ 556 if (s->num_cpu == 1 && s->revision != REV_11MPCORE) { 557 /* For uniprocessor GICs these RAZ/WI */ 558 res = 0; 559 } else { 560 irq = (offset - 0x800) + GIC_BASE_IRQ; 561 if (irq >= s->num_irq) { 562 goto bad_reg; 563 } 564 if (irq >= 29 && irq <= 31) { 565 res = cm; 566 } else { 567 res = GIC_TARGET(irq); 568 } 569 } 570 } else if (offset < 0xf00) { 571 /* Interrupt Configuration. */ 572 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 573 if (irq >= s->num_irq) 574 goto bad_reg; 575 res = 0; 576 for (i = 0; i < 4; i++) { 577 if (GIC_TEST_MODEL(irq + i)) 578 res |= (1 << (i * 2)); 579 if (GIC_TEST_EDGE_TRIGGER(irq + i)) 580 res |= (2 << (i * 2)); 581 } 582 } else if (offset < 0xf10) { 583 goto bad_reg; 584 } else if (offset < 0xf30) { 585 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 586 goto bad_reg; 587 } 588 589 if (offset < 0xf20) { 590 /* GICD_CPENDSGIRn */ 591 irq = (offset - 0xf10); 592 } else { 593 irq = (offset - 0xf20); 594 /* GICD_SPENDSGIRn */ 595 } 596 597 res = s->sgi_pending[irq][cpu]; 598 } else if (offset < 0xfe0) { 599 goto bad_reg; 600 } else /* offset >= 0xfe0 */ { 601 if (offset & 3) { 602 res = 0; 603 } else { 604 res = gic_id[(offset - 0xfe0) >> 2]; 605 } 606 } 607 return res; 608 bad_reg: 609 qemu_log_mask(LOG_GUEST_ERROR, 610 "gic_dist_readb: Bad offset %x\n", (int)offset); 611 return 0; 612 } 613 614 static MemTxResult gic_dist_read(void *opaque, hwaddr offset, uint64_t *data, 615 unsigned size, MemTxAttrs attrs) 616 { 617 switch (size) { 618 case 1: 619 *data = gic_dist_readb(opaque, offset, attrs); 620 return MEMTX_OK; 621 case 2: 622 *data = gic_dist_readb(opaque, offset, attrs); 623 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 624 return MEMTX_OK; 625 case 4: 626 *data = gic_dist_readb(opaque, offset, attrs); 627 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 628 *data |= gic_dist_readb(opaque, offset + 2, attrs) << 16; 629 *data |= gic_dist_readb(opaque, offset + 3, attrs) << 24; 630 return MEMTX_OK; 631 default: 632 return MEMTX_ERROR; 633 } 634 } 635 636 static void gic_dist_writeb(void *opaque, hwaddr offset, 637 uint32_t value, MemTxAttrs attrs) 638 { 639 GICState *s = (GICState *)opaque; 640 int irq; 641 int i; 642 int cpu; 643 644 cpu = gic_get_current_cpu(s); 645 if (offset < 0x100) { 646 if (offset == 0) { 647 if (s->security_extn && !attrs.secure) { 648 /* NS version is just an alias of the S version's bit 1 */ 649 s->ctlr = deposit32(s->ctlr, 1, 1, value); 650 } else if (gic_has_groups(s)) { 651 s->ctlr = value & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1); 652 } else { 653 s->ctlr = value & GICD_CTLR_EN_GRP0; 654 } 655 DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n", 656 s->ctlr & GICD_CTLR_EN_GRP0 ? "En" : "Dis", 657 s->ctlr & GICD_CTLR_EN_GRP1 ? "En" : "Dis"); 658 } else if (offset < 4) { 659 /* ignored. */ 660 } else if (offset >= 0x80) { 661 /* Interrupt Group Registers: RAZ/WI for NS access to secure 662 * GIC, or for GICs without groups. 663 */ 664 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 665 /* Every byte offset holds 8 group status bits */ 666 irq = (offset - 0x80) * 8 + GIC_BASE_IRQ; 667 if (irq >= s->num_irq) { 668 goto bad_reg; 669 } 670 for (i = 0; i < 8; i++) { 671 /* Group bits are banked for private interrupts */ 672 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 673 if (value & (1 << i)) { 674 /* Group1 (Non-secure) */ 675 GIC_SET_GROUP(irq + i, cm); 676 } else { 677 /* Group0 (Secure) */ 678 GIC_CLEAR_GROUP(irq + i, cm); 679 } 680 } 681 } 682 } else { 683 goto bad_reg; 684 } 685 } else if (offset < 0x180) { 686 /* Interrupt Set Enable. */ 687 irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; 688 if (irq >= s->num_irq) 689 goto bad_reg; 690 if (irq < GIC_NR_SGIS) { 691 value = 0xff; 692 } 693 694 for (i = 0; i < 8; i++) { 695 if (value & (1 << i)) { 696 int mask = 697 (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq + i); 698 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 699 700 if (!GIC_TEST_ENABLED(irq + i, cm)) { 701 DPRINTF("Enabled IRQ %d\n", irq + i); 702 } 703 GIC_SET_ENABLED(irq + i, cm); 704 /* If a raised level triggered IRQ enabled then mark 705 is as pending. */ 706 if (GIC_TEST_LEVEL(irq + i, mask) 707 && !GIC_TEST_EDGE_TRIGGER(irq + i)) { 708 DPRINTF("Set %d pending mask %x\n", irq + i, mask); 709 GIC_SET_PENDING(irq + i, mask); 710 } 711 } 712 } 713 } else if (offset < 0x200) { 714 /* Interrupt Clear Enable. */ 715 irq = (offset - 0x180) * 8 + GIC_BASE_IRQ; 716 if (irq >= s->num_irq) 717 goto bad_reg; 718 if (irq < GIC_NR_SGIS) { 719 value = 0; 720 } 721 722 for (i = 0; i < 8; i++) { 723 if (value & (1 << i)) { 724 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 725 726 if (GIC_TEST_ENABLED(irq + i, cm)) { 727 DPRINTF("Disabled IRQ %d\n", irq + i); 728 } 729 GIC_CLEAR_ENABLED(irq + i, cm); 730 } 731 } 732 } else if (offset < 0x280) { 733 /* Interrupt Set Pending. */ 734 irq = (offset - 0x200) * 8 + GIC_BASE_IRQ; 735 if (irq >= s->num_irq) 736 goto bad_reg; 737 if (irq < GIC_NR_SGIS) { 738 value = 0; 739 } 740 741 for (i = 0; i < 8; i++) { 742 if (value & (1 << i)) { 743 GIC_SET_PENDING(irq + i, GIC_TARGET(irq + i)); 744 } 745 } 746 } else if (offset < 0x300) { 747 /* Interrupt Clear Pending. */ 748 irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; 749 if (irq >= s->num_irq) 750 goto bad_reg; 751 if (irq < GIC_NR_SGIS) { 752 value = 0; 753 } 754 755 for (i = 0; i < 8; i++) { 756 /* ??? This currently clears the pending bit for all CPUs, even 757 for per-CPU interrupts. It's unclear whether this is the 758 corect behavior. */ 759 if (value & (1 << i)) { 760 GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK); 761 } 762 } 763 } else if (offset < 0x400) { 764 /* Interrupt Active. */ 765 goto bad_reg; 766 } else if (offset < 0x800) { 767 /* Interrupt Priority. */ 768 irq = (offset - 0x400) + GIC_BASE_IRQ; 769 if (irq >= s->num_irq) 770 goto bad_reg; 771 gic_set_priority(s, cpu, irq, value, attrs); 772 } else if (offset < 0xc00) { 773 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the 774 * annoying exception of the 11MPCore's GIC. 775 */ 776 if (s->num_cpu != 1 || s->revision == REV_11MPCORE) { 777 irq = (offset - 0x800) + GIC_BASE_IRQ; 778 if (irq >= s->num_irq) { 779 goto bad_reg; 780 } 781 if (irq < 29) { 782 value = 0; 783 } else if (irq < GIC_INTERNAL) { 784 value = ALL_CPU_MASK; 785 } 786 s->irq_target[irq] = value & ALL_CPU_MASK; 787 } 788 } else if (offset < 0xf00) { 789 /* Interrupt Configuration. */ 790 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 791 if (irq >= s->num_irq) 792 goto bad_reg; 793 if (irq < GIC_NR_SGIS) 794 value |= 0xaa; 795 for (i = 0; i < 4; i++) { 796 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 797 if (value & (1 << (i * 2))) { 798 GIC_SET_MODEL(irq + i); 799 } else { 800 GIC_CLEAR_MODEL(irq + i); 801 } 802 } 803 if (value & (2 << (i * 2))) { 804 GIC_SET_EDGE_TRIGGER(irq + i); 805 } else { 806 GIC_CLEAR_EDGE_TRIGGER(irq + i); 807 } 808 } 809 } else if (offset < 0xf10) { 810 /* 0xf00 is only handled for 32-bit writes. */ 811 goto bad_reg; 812 } else if (offset < 0xf20) { 813 /* GICD_CPENDSGIRn */ 814 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 815 goto bad_reg; 816 } 817 irq = (offset - 0xf10); 818 819 s->sgi_pending[irq][cpu] &= ~value; 820 if (s->sgi_pending[irq][cpu] == 0) { 821 GIC_CLEAR_PENDING(irq, 1 << cpu); 822 } 823 } else if (offset < 0xf30) { 824 /* GICD_SPENDSGIRn */ 825 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 826 goto bad_reg; 827 } 828 irq = (offset - 0xf20); 829 830 GIC_SET_PENDING(irq, 1 << cpu); 831 s->sgi_pending[irq][cpu] |= value; 832 } else { 833 goto bad_reg; 834 } 835 gic_update(s); 836 return; 837 bad_reg: 838 qemu_log_mask(LOG_GUEST_ERROR, 839 "gic_dist_writeb: Bad offset %x\n", (int)offset); 840 } 841 842 static void gic_dist_writew(void *opaque, hwaddr offset, 843 uint32_t value, MemTxAttrs attrs) 844 { 845 gic_dist_writeb(opaque, offset, value & 0xff, attrs); 846 gic_dist_writeb(opaque, offset + 1, value >> 8, attrs); 847 } 848 849 static void gic_dist_writel(void *opaque, hwaddr offset, 850 uint32_t value, MemTxAttrs attrs) 851 { 852 GICState *s = (GICState *)opaque; 853 if (offset == 0xf00) { 854 int cpu; 855 int irq; 856 int mask; 857 int target_cpu; 858 859 cpu = gic_get_current_cpu(s); 860 irq = value & 0x3ff; 861 switch ((value >> 24) & 3) { 862 case 0: 863 mask = (value >> 16) & ALL_CPU_MASK; 864 break; 865 case 1: 866 mask = ALL_CPU_MASK ^ (1 << cpu); 867 break; 868 case 2: 869 mask = 1 << cpu; 870 break; 871 default: 872 DPRINTF("Bad Soft Int target filter\n"); 873 mask = ALL_CPU_MASK; 874 break; 875 } 876 GIC_SET_PENDING(irq, mask); 877 target_cpu = ctz32(mask); 878 while (target_cpu < GIC_NCPU) { 879 s->sgi_pending[irq][target_cpu] |= (1 << cpu); 880 mask &= ~(1 << target_cpu); 881 target_cpu = ctz32(mask); 882 } 883 gic_update(s); 884 return; 885 } 886 gic_dist_writew(opaque, offset, value & 0xffff, attrs); 887 gic_dist_writew(opaque, offset + 2, value >> 16, attrs); 888 } 889 890 static MemTxResult gic_dist_write(void *opaque, hwaddr offset, uint64_t data, 891 unsigned size, MemTxAttrs attrs) 892 { 893 switch (size) { 894 case 1: 895 gic_dist_writeb(opaque, offset, data, attrs); 896 return MEMTX_OK; 897 case 2: 898 gic_dist_writew(opaque, offset, data, attrs); 899 return MEMTX_OK; 900 case 4: 901 gic_dist_writel(opaque, offset, data, attrs); 902 return MEMTX_OK; 903 default: 904 return MEMTX_ERROR; 905 } 906 } 907 908 static const MemoryRegionOps gic_dist_ops = { 909 .read_with_attrs = gic_dist_read, 910 .write_with_attrs = gic_dist_write, 911 .endianness = DEVICE_NATIVE_ENDIAN, 912 }; 913 914 static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset, 915 uint64_t *data, MemTxAttrs attrs) 916 { 917 switch (offset) { 918 case 0x00: /* Control */ 919 *data = gic_get_cpu_control(s, cpu, attrs); 920 break; 921 case 0x04: /* Priority mask */ 922 *data = gic_get_priority_mask(s, cpu, attrs); 923 break; 924 case 0x08: /* Binary Point */ 925 if (s->security_extn && !attrs.secure) { 926 /* BPR is banked. Non-secure copy stored in ABPR. */ 927 *data = s->abpr[cpu]; 928 } else { 929 *data = s->bpr[cpu]; 930 } 931 break; 932 case 0x0c: /* Acknowledge */ 933 *data = gic_acknowledge_irq(s, cpu, attrs); 934 break; 935 case 0x14: /* Running Priority */ 936 *data = gic_get_running_priority(s, cpu, attrs); 937 break; 938 case 0x18: /* Highest Pending Interrupt */ 939 *data = gic_get_current_pending_irq(s, cpu, attrs); 940 break; 941 case 0x1c: /* Aliased Binary Point */ 942 /* GIC v2, no security: ABPR 943 * GIC v1, no security: not implemented (RAZ/WI) 944 * With security extensions, secure access: ABPR (alias of NS BPR) 945 * With security extensions, nonsecure access: RAZ/WI 946 */ 947 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 948 *data = 0; 949 } else { 950 *data = s->abpr[cpu]; 951 } 952 break; 953 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 954 *data = s->apr[(offset - 0xd0) / 4][cpu]; 955 break; 956 default: 957 qemu_log_mask(LOG_GUEST_ERROR, 958 "gic_cpu_read: Bad offset %x\n", (int)offset); 959 return MEMTX_ERROR; 960 } 961 return MEMTX_OK; 962 } 963 964 static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset, 965 uint32_t value, MemTxAttrs attrs) 966 { 967 switch (offset) { 968 case 0x00: /* Control */ 969 gic_set_cpu_control(s, cpu, value, attrs); 970 break; 971 case 0x04: /* Priority mask */ 972 gic_set_priority_mask(s, cpu, value, attrs); 973 break; 974 case 0x08: /* Binary Point */ 975 if (s->security_extn && !attrs.secure) { 976 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 977 } else { 978 s->bpr[cpu] = MAX(value & 0x7, GIC_MIN_BPR); 979 } 980 break; 981 case 0x10: /* End Of Interrupt */ 982 gic_complete_irq(s, cpu, value & 0x3ff, attrs); 983 return MEMTX_OK; 984 case 0x1c: /* Aliased Binary Point */ 985 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 986 /* unimplemented, or NS access: RAZ/WI */ 987 return MEMTX_OK; 988 } else { 989 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 990 } 991 break; 992 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 993 qemu_log_mask(LOG_UNIMP, "Writing APR not implemented\n"); 994 break; 995 default: 996 qemu_log_mask(LOG_GUEST_ERROR, 997 "gic_cpu_write: Bad offset %x\n", (int)offset); 998 return MEMTX_ERROR; 999 } 1000 gic_update(s); 1001 return MEMTX_OK; 1002 } 1003 1004 /* Wrappers to read/write the GIC CPU interface for the current CPU */ 1005 static MemTxResult gic_thiscpu_read(void *opaque, hwaddr addr, uint64_t *data, 1006 unsigned size, MemTxAttrs attrs) 1007 { 1008 GICState *s = (GICState *)opaque; 1009 return gic_cpu_read(s, gic_get_current_cpu(s), addr, data, attrs); 1010 } 1011 1012 static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, 1013 uint64_t value, unsigned size, 1014 MemTxAttrs attrs) 1015 { 1016 GICState *s = (GICState *)opaque; 1017 return gic_cpu_write(s, gic_get_current_cpu(s), addr, value, attrs); 1018 } 1019 1020 /* Wrappers to read/write the GIC CPU interface for a specific CPU. 1021 * These just decode the opaque pointer into GICState* + cpu id. 1022 */ 1023 static MemTxResult gic_do_cpu_read(void *opaque, hwaddr addr, uint64_t *data, 1024 unsigned size, MemTxAttrs attrs) 1025 { 1026 GICState **backref = (GICState **)opaque; 1027 GICState *s = *backref; 1028 int id = (backref - s->backref); 1029 return gic_cpu_read(s, id, addr, data, attrs); 1030 } 1031 1032 static MemTxResult gic_do_cpu_write(void *opaque, hwaddr addr, 1033 uint64_t value, unsigned size, 1034 MemTxAttrs attrs) 1035 { 1036 GICState **backref = (GICState **)opaque; 1037 GICState *s = *backref; 1038 int id = (backref - s->backref); 1039 return gic_cpu_write(s, id, addr, value, attrs); 1040 } 1041 1042 static const MemoryRegionOps gic_thiscpu_ops = { 1043 .read_with_attrs = gic_thiscpu_read, 1044 .write_with_attrs = gic_thiscpu_write, 1045 .endianness = DEVICE_NATIVE_ENDIAN, 1046 }; 1047 1048 static const MemoryRegionOps gic_cpu_ops = { 1049 .read_with_attrs = gic_do_cpu_read, 1050 .write_with_attrs = gic_do_cpu_write, 1051 .endianness = DEVICE_NATIVE_ENDIAN, 1052 }; 1053 1054 void gic_init_irqs_and_distributor(GICState *s) 1055 { 1056 SysBusDevice *sbd = SYS_BUS_DEVICE(s); 1057 int i; 1058 1059 i = s->num_irq - GIC_INTERNAL; 1060 /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU. 1061 * GPIO array layout is thus: 1062 * [0..N-1] SPIs 1063 * [N..N+31] PPIs for CPU 0 1064 * [N+32..N+63] PPIs for CPU 1 1065 * ... 1066 */ 1067 if (s->revision != REV_NVIC) { 1068 i += (GIC_INTERNAL * s->num_cpu); 1069 } 1070 qdev_init_gpio_in(DEVICE(s), gic_set_irq, i); 1071 for (i = 0; i < NUM_CPU(s); i++) { 1072 sysbus_init_irq(sbd, &s->parent_irq[i]); 1073 } 1074 for (i = 0; i < NUM_CPU(s); i++) { 1075 sysbus_init_irq(sbd, &s->parent_fiq[i]); 1076 } 1077 memory_region_init_io(&s->iomem, OBJECT(s), &gic_dist_ops, s, 1078 "gic_dist", 0x1000); 1079 } 1080 1081 static void arm_gic_realize(DeviceState *dev, Error **errp) 1082 { 1083 /* Device instance realize function for the GIC sysbus device */ 1084 int i; 1085 GICState *s = ARM_GIC(dev); 1086 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1087 ARMGICClass *agc = ARM_GIC_GET_CLASS(s); 1088 Error *local_err = NULL; 1089 1090 agc->parent_realize(dev, &local_err); 1091 if (local_err) { 1092 error_propagate(errp, local_err); 1093 return; 1094 } 1095 1096 gic_init_irqs_and_distributor(s); 1097 1098 /* Memory regions for the CPU interfaces (NVIC doesn't have these): 1099 * a region for "CPU interface for this core", then a region for 1100 * "CPU interface for core 0", "for core 1", ... 1101 * NB that the memory region size of 0x100 applies for the 11MPCore 1102 * and also cores following the GIC v1 spec (ie A9). 1103 * GIC v2 defines a larger memory region (0x1000) so this will need 1104 * to be extended when we implement A15. 1105 */ 1106 memory_region_init_io(&s->cpuiomem[0], OBJECT(s), &gic_thiscpu_ops, s, 1107 "gic_cpu", 0x100); 1108 for (i = 0; i < NUM_CPU(s); i++) { 1109 s->backref[i] = s; 1110 memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops, 1111 &s->backref[i], "gic_cpu", 0x100); 1112 } 1113 /* Distributor */ 1114 sysbus_init_mmio(sbd, &s->iomem); 1115 /* cpu interfaces (one for "current cpu" plus one per cpu) */ 1116 for (i = 0; i <= NUM_CPU(s); i++) { 1117 sysbus_init_mmio(sbd, &s->cpuiomem[i]); 1118 } 1119 } 1120 1121 static void arm_gic_class_init(ObjectClass *klass, void *data) 1122 { 1123 DeviceClass *dc = DEVICE_CLASS(klass); 1124 ARMGICClass *agc = ARM_GIC_CLASS(klass); 1125 1126 agc->parent_realize = dc->realize; 1127 dc->realize = arm_gic_realize; 1128 } 1129 1130 static const TypeInfo arm_gic_info = { 1131 .name = TYPE_ARM_GIC, 1132 .parent = TYPE_ARM_GIC_COMMON, 1133 .instance_size = sizeof(GICState), 1134 .class_init = arm_gic_class_init, 1135 .class_size = sizeof(ARMGICClass), 1136 }; 1137 1138 static void arm_gic_register_types(void) 1139 { 1140 type_register_static(&arm_gic_info); 1141 } 1142 1143 type_init(arm_gic_register_types) 1144