1 /* 2 * ARM Generic/Distributed Interrupt Controller 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 /* This file contains implementation code for the RealView EB interrupt 11 * controller, MPCore distributed interrupt controller and ARMv7-M 12 * Nested Vectored Interrupt Controller. 13 * It is compiled in two ways: 14 * (1) as a standalone file to produce a sysbus device which is a GIC 15 * that can be used on the realview board and as one of the builtin 16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc) 17 * (2) by being directly #included into armv7m_nvic.c to produce the 18 * armv7m_nvic device. 19 */ 20 21 #include "hw/sysbus.h" 22 #include "gic_internal.h" 23 #include "qom/cpu.h" 24 25 //#define DEBUG_GIC 26 27 #ifdef DEBUG_GIC 28 #define DPRINTF(fmt, ...) \ 29 do { fprintf(stderr, "arm_gic: " fmt , ## __VA_ARGS__); } while (0) 30 #else 31 #define DPRINTF(fmt, ...) do {} while(0) 32 #endif 33 34 static const uint8_t gic_id[] = { 35 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 36 }; 37 38 #define NUM_CPU(s) ((s)->num_cpu) 39 40 static inline int gic_get_current_cpu(GICState *s) 41 { 42 if (s->num_cpu > 1) { 43 return current_cpu->cpu_index; 44 } 45 return 0; 46 } 47 48 /* TODO: Many places that call this routine could be optimized. */ 49 /* Update interrupt status after enabled or pending bits have been changed. */ 50 void gic_update(GICState *s) 51 { 52 int best_irq; 53 int best_prio; 54 int irq; 55 int level; 56 int cpu; 57 int cm; 58 59 for (cpu = 0; cpu < NUM_CPU(s); cpu++) { 60 cm = 1 << cpu; 61 s->current_pending[cpu] = 1023; 62 if (!s->enabled || !s->cpu_enabled[cpu]) { 63 qemu_irq_lower(s->parent_irq[cpu]); 64 return; 65 } 66 best_prio = 0x100; 67 best_irq = 1023; 68 for (irq = 0; irq < s->num_irq; irq++) { 69 if (GIC_TEST_ENABLED(irq, cm) && GIC_TEST_PENDING(irq, cm)) { 70 if (GIC_GET_PRIORITY(irq, cpu) < best_prio) { 71 best_prio = GIC_GET_PRIORITY(irq, cpu); 72 best_irq = irq; 73 } 74 } 75 } 76 level = 0; 77 if (best_prio < s->priority_mask[cpu]) { 78 s->current_pending[cpu] = best_irq; 79 if (best_prio < s->running_priority[cpu]) { 80 DPRINTF("Raised pending IRQ %d (cpu %d)\n", best_irq, cpu); 81 level = 1; 82 } 83 } 84 qemu_set_irq(s->parent_irq[cpu], level); 85 } 86 } 87 88 void gic_set_pending_private(GICState *s, int cpu, int irq) 89 { 90 int cm = 1 << cpu; 91 92 if (GIC_TEST_PENDING(irq, cm)) 93 return; 94 95 DPRINTF("Set %d pending cpu %d\n", irq, cpu); 96 GIC_SET_PENDING(irq, cm); 97 gic_update(s); 98 } 99 100 /* Process a change in an external IRQ input. */ 101 static void gic_set_irq(void *opaque, int irq, int level) 102 { 103 /* Meaning of the 'irq' parameter: 104 * [0..N-1] : external interrupts 105 * [N..N+31] : PPI (internal) interrupts for CPU 0 106 * [N+32..N+63] : PPI (internal interrupts for CPU 1 107 * ... 108 */ 109 GICState *s = (GICState *)opaque; 110 int cm, target; 111 if (irq < (s->num_irq - GIC_INTERNAL)) { 112 /* The first external input line is internal interrupt 32. */ 113 cm = ALL_CPU_MASK; 114 irq += GIC_INTERNAL; 115 target = GIC_TARGET(irq); 116 } else { 117 int cpu; 118 irq -= (s->num_irq - GIC_INTERNAL); 119 cpu = irq / GIC_INTERNAL; 120 irq %= GIC_INTERNAL; 121 cm = 1 << cpu; 122 target = cm; 123 } 124 125 if (level == GIC_TEST_LEVEL(irq, cm)) { 126 return; 127 } 128 129 if (level) { 130 GIC_SET_LEVEL(irq, cm); 131 if (GIC_TEST_EDGE_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) { 132 DPRINTF("Set %d pending mask %x\n", irq, target); 133 GIC_SET_PENDING(irq, target); 134 } 135 } else { 136 GIC_CLEAR_LEVEL(irq, cm); 137 } 138 gic_update(s); 139 } 140 141 static void gic_set_running_irq(GICState *s, int cpu, int irq) 142 { 143 s->running_irq[cpu] = irq; 144 if (irq == 1023) { 145 s->running_priority[cpu] = 0x100; 146 } else { 147 s->running_priority[cpu] = GIC_GET_PRIORITY(irq, cpu); 148 } 149 gic_update(s); 150 } 151 152 uint32_t gic_acknowledge_irq(GICState *s, int cpu) 153 { 154 int new_irq; 155 int cm = 1 << cpu; 156 new_irq = s->current_pending[cpu]; 157 if (new_irq == 1023 158 || GIC_GET_PRIORITY(new_irq, cpu) >= s->running_priority[cpu]) { 159 DPRINTF("ACK no pending IRQ\n"); 160 return 1023; 161 } 162 s->last_active[new_irq][cpu] = s->running_irq[cpu]; 163 /* Clear pending flags for both level and edge triggered interrupts. 164 Level triggered IRQs will be reasserted once they become inactive. */ 165 GIC_CLEAR_PENDING(new_irq, GIC_TEST_MODEL(new_irq) ? ALL_CPU_MASK : cm); 166 gic_set_running_irq(s, cpu, new_irq); 167 DPRINTF("ACK %d\n", new_irq); 168 return new_irq; 169 } 170 171 void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val) 172 { 173 if (irq < GIC_INTERNAL) { 174 s->priority1[irq][cpu] = val; 175 } else { 176 s->priority2[(irq) - GIC_INTERNAL] = val; 177 } 178 } 179 180 void gic_complete_irq(GICState *s, int cpu, int irq) 181 { 182 int update = 0; 183 int cm = 1 << cpu; 184 DPRINTF("EOI %d\n", irq); 185 if (irq >= s->num_irq) { 186 /* This handles two cases: 187 * 1. If software writes the ID of a spurious interrupt [ie 1023] 188 * to the GICC_EOIR, the GIC ignores that write. 189 * 2. If software writes the number of a non-existent interrupt 190 * this must be a subcase of "value written does not match the last 191 * valid interrupt value read from the Interrupt Acknowledge 192 * register" and so this is UNPREDICTABLE. We choose to ignore it. 193 */ 194 return; 195 } 196 if (s->running_irq[cpu] == 1023) 197 return; /* No active IRQ. */ 198 /* Mark level triggered interrupts as pending if they are still 199 raised. */ 200 if (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm) 201 && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) { 202 DPRINTF("Set %d pending mask %x\n", irq, cm); 203 GIC_SET_PENDING(irq, cm); 204 update = 1; 205 } 206 if (irq != s->running_irq[cpu]) { 207 /* Complete an IRQ that is not currently running. */ 208 int tmp = s->running_irq[cpu]; 209 while (s->last_active[tmp][cpu] != 1023) { 210 if (s->last_active[tmp][cpu] == irq) { 211 s->last_active[tmp][cpu] = s->last_active[irq][cpu]; 212 break; 213 } 214 tmp = s->last_active[tmp][cpu]; 215 } 216 if (update) { 217 gic_update(s); 218 } 219 } else { 220 /* Complete the current running IRQ. */ 221 gic_set_running_irq(s, cpu, s->last_active[s->running_irq[cpu]][cpu]); 222 } 223 } 224 225 static uint32_t gic_dist_readb(void *opaque, hwaddr offset) 226 { 227 GICState *s = (GICState *)opaque; 228 uint32_t res; 229 int irq; 230 int i; 231 int cpu; 232 int cm; 233 int mask; 234 235 cpu = gic_get_current_cpu(s); 236 cm = 1 << cpu; 237 if (offset < 0x100) { 238 if (offset == 0) 239 return s->enabled; 240 if (offset == 4) 241 return ((s->num_irq / 32) - 1) | ((NUM_CPU(s) - 1) << 5); 242 if (offset < 0x08) 243 return 0; 244 if (offset >= 0x80) { 245 /* Interrupt Security , RAZ/WI */ 246 return 0; 247 } 248 goto bad_reg; 249 } else if (offset < 0x200) { 250 /* Interrupt Set/Clear Enable. */ 251 if (offset < 0x180) 252 irq = (offset - 0x100) * 8; 253 else 254 irq = (offset - 0x180) * 8; 255 irq += GIC_BASE_IRQ; 256 if (irq >= s->num_irq) 257 goto bad_reg; 258 res = 0; 259 for (i = 0; i < 8; i++) { 260 if (GIC_TEST_ENABLED(irq + i, cm)) { 261 res |= (1 << i); 262 } 263 } 264 } else if (offset < 0x300) { 265 /* Interrupt Set/Clear Pending. */ 266 if (offset < 0x280) 267 irq = (offset - 0x200) * 8; 268 else 269 irq = (offset - 0x280) * 8; 270 irq += GIC_BASE_IRQ; 271 if (irq >= s->num_irq) 272 goto bad_reg; 273 res = 0; 274 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 275 for (i = 0; i < 8; i++) { 276 if (GIC_TEST_PENDING(irq + i, mask)) { 277 res |= (1 << i); 278 } 279 } 280 } else if (offset < 0x400) { 281 /* Interrupt Active. */ 282 irq = (offset - 0x300) * 8 + GIC_BASE_IRQ; 283 if (irq >= s->num_irq) 284 goto bad_reg; 285 res = 0; 286 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 287 for (i = 0; i < 8; i++) { 288 if (GIC_TEST_ACTIVE(irq + i, mask)) { 289 res |= (1 << i); 290 } 291 } 292 } else if (offset < 0x800) { 293 /* Interrupt Priority. */ 294 irq = (offset - 0x400) + GIC_BASE_IRQ; 295 if (irq >= s->num_irq) 296 goto bad_reg; 297 res = GIC_GET_PRIORITY(irq, cpu); 298 } else if (offset < 0xc00) { 299 /* Interrupt CPU Target. */ 300 if (s->num_cpu == 1 && s->revision != REV_11MPCORE) { 301 /* For uniprocessor GICs these RAZ/WI */ 302 res = 0; 303 } else { 304 irq = (offset - 0x800) + GIC_BASE_IRQ; 305 if (irq >= s->num_irq) { 306 goto bad_reg; 307 } 308 if (irq >= 29 && irq <= 31) { 309 res = cm; 310 } else { 311 res = GIC_TARGET(irq); 312 } 313 } 314 } else if (offset < 0xf00) { 315 /* Interrupt Configuration. */ 316 irq = (offset - 0xc00) * 2 + GIC_BASE_IRQ; 317 if (irq >= s->num_irq) 318 goto bad_reg; 319 res = 0; 320 for (i = 0; i < 4; i++) { 321 if (GIC_TEST_MODEL(irq + i)) 322 res |= (1 << (i * 2)); 323 if (GIC_TEST_EDGE_TRIGGER(irq + i)) 324 res |= (2 << (i * 2)); 325 } 326 } else if (offset < 0xfe0) { 327 goto bad_reg; 328 } else /* offset >= 0xfe0 */ { 329 if (offset & 3) { 330 res = 0; 331 } else { 332 res = gic_id[(offset - 0xfe0) >> 2]; 333 } 334 } 335 return res; 336 bad_reg: 337 qemu_log_mask(LOG_GUEST_ERROR, 338 "gic_dist_readb: Bad offset %x\n", (int)offset); 339 return 0; 340 } 341 342 static uint32_t gic_dist_readw(void *opaque, hwaddr offset) 343 { 344 uint32_t val; 345 val = gic_dist_readb(opaque, offset); 346 val |= gic_dist_readb(opaque, offset + 1) << 8; 347 return val; 348 } 349 350 static uint32_t gic_dist_readl(void *opaque, hwaddr offset) 351 { 352 uint32_t val; 353 val = gic_dist_readw(opaque, offset); 354 val |= gic_dist_readw(opaque, offset + 2) << 16; 355 return val; 356 } 357 358 static void gic_dist_writeb(void *opaque, hwaddr offset, 359 uint32_t value) 360 { 361 GICState *s = (GICState *)opaque; 362 int irq; 363 int i; 364 int cpu; 365 366 cpu = gic_get_current_cpu(s); 367 if (offset < 0x100) { 368 if (offset == 0) { 369 s->enabled = (value & 1); 370 DPRINTF("Distribution %sabled\n", s->enabled ? "En" : "Dis"); 371 } else if (offset < 4) { 372 /* ignored. */ 373 } else if (offset >= 0x80) { 374 /* Interrupt Security Registers, RAZ/WI */ 375 } else { 376 goto bad_reg; 377 } 378 } else if (offset < 0x180) { 379 /* Interrupt Set Enable. */ 380 irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; 381 if (irq >= s->num_irq) 382 goto bad_reg; 383 if (irq < 16) 384 value = 0xff; 385 for (i = 0; i < 8; i++) { 386 if (value & (1 << i)) { 387 int mask = 388 (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq + i); 389 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 390 391 if (!GIC_TEST_ENABLED(irq + i, cm)) { 392 DPRINTF("Enabled IRQ %d\n", irq + i); 393 } 394 GIC_SET_ENABLED(irq + i, cm); 395 /* If a raised level triggered IRQ enabled then mark 396 is as pending. */ 397 if (GIC_TEST_LEVEL(irq + i, mask) 398 && !GIC_TEST_EDGE_TRIGGER(irq + i)) { 399 DPRINTF("Set %d pending mask %x\n", irq + i, mask); 400 GIC_SET_PENDING(irq + i, mask); 401 } 402 } 403 } 404 } else if (offset < 0x200) { 405 /* Interrupt Clear Enable. */ 406 irq = (offset - 0x180) * 8 + GIC_BASE_IRQ; 407 if (irq >= s->num_irq) 408 goto bad_reg; 409 if (irq < 16) 410 value = 0; 411 for (i = 0; i < 8; i++) { 412 if (value & (1 << i)) { 413 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 414 415 if (GIC_TEST_ENABLED(irq + i, cm)) { 416 DPRINTF("Disabled IRQ %d\n", irq + i); 417 } 418 GIC_CLEAR_ENABLED(irq + i, cm); 419 } 420 } 421 } else if (offset < 0x280) { 422 /* Interrupt Set Pending. */ 423 irq = (offset - 0x200) * 8 + GIC_BASE_IRQ; 424 if (irq >= s->num_irq) 425 goto bad_reg; 426 if (irq < 16) 427 irq = 0; 428 429 for (i = 0; i < 8; i++) { 430 if (value & (1 << i)) { 431 GIC_SET_PENDING(irq + i, GIC_TARGET(irq + i)); 432 } 433 } 434 } else if (offset < 0x300) { 435 /* Interrupt Clear Pending. */ 436 irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; 437 if (irq >= s->num_irq) 438 goto bad_reg; 439 for (i = 0; i < 8; i++) { 440 /* ??? This currently clears the pending bit for all CPUs, even 441 for per-CPU interrupts. It's unclear whether this is the 442 corect behavior. */ 443 if (value & (1 << i)) { 444 GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK); 445 } 446 } 447 } else if (offset < 0x400) { 448 /* Interrupt Active. */ 449 goto bad_reg; 450 } else if (offset < 0x800) { 451 /* Interrupt Priority. */ 452 irq = (offset - 0x400) + GIC_BASE_IRQ; 453 if (irq >= s->num_irq) 454 goto bad_reg; 455 gic_set_priority(s, cpu, irq, value); 456 } else if (offset < 0xc00) { 457 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the 458 * annoying exception of the 11MPCore's GIC. 459 */ 460 if (s->num_cpu != 1 || s->revision == REV_11MPCORE) { 461 irq = (offset - 0x800) + GIC_BASE_IRQ; 462 if (irq >= s->num_irq) { 463 goto bad_reg; 464 } 465 if (irq < 29) { 466 value = 0; 467 } else if (irq < GIC_INTERNAL) { 468 value = ALL_CPU_MASK; 469 } 470 s->irq_target[irq] = value & ALL_CPU_MASK; 471 } 472 } else if (offset < 0xf00) { 473 /* Interrupt Configuration. */ 474 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 475 if (irq >= s->num_irq) 476 goto bad_reg; 477 if (irq < GIC_INTERNAL) 478 value |= 0xaa; 479 for (i = 0; i < 4; i++) { 480 if (value & (1 << (i * 2))) { 481 GIC_SET_MODEL(irq + i); 482 } else { 483 GIC_CLEAR_MODEL(irq + i); 484 } 485 if (value & (2 << (i * 2))) { 486 GIC_SET_EDGE_TRIGGER(irq + i); 487 } else { 488 GIC_CLEAR_EDGE_TRIGGER(irq + i); 489 } 490 } 491 } else { 492 /* 0xf00 is only handled for 32-bit writes. */ 493 goto bad_reg; 494 } 495 gic_update(s); 496 return; 497 bad_reg: 498 qemu_log_mask(LOG_GUEST_ERROR, 499 "gic_dist_writeb: Bad offset %x\n", (int)offset); 500 } 501 502 static void gic_dist_writew(void *opaque, hwaddr offset, 503 uint32_t value) 504 { 505 gic_dist_writeb(opaque, offset, value & 0xff); 506 gic_dist_writeb(opaque, offset + 1, value >> 8); 507 } 508 509 static void gic_dist_writel(void *opaque, hwaddr offset, 510 uint32_t value) 511 { 512 GICState *s = (GICState *)opaque; 513 if (offset == 0xf00) { 514 int cpu; 515 int irq; 516 int mask; 517 518 cpu = gic_get_current_cpu(s); 519 irq = value & 0x3ff; 520 switch ((value >> 24) & 3) { 521 case 0: 522 mask = (value >> 16) & ALL_CPU_MASK; 523 break; 524 case 1: 525 mask = ALL_CPU_MASK ^ (1 << cpu); 526 break; 527 case 2: 528 mask = 1 << cpu; 529 break; 530 default: 531 DPRINTF("Bad Soft Int target filter\n"); 532 mask = ALL_CPU_MASK; 533 break; 534 } 535 GIC_SET_PENDING(irq, mask); 536 gic_update(s); 537 return; 538 } 539 gic_dist_writew(opaque, offset, value & 0xffff); 540 gic_dist_writew(opaque, offset + 2, value >> 16); 541 } 542 543 static const MemoryRegionOps gic_dist_ops = { 544 .old_mmio = { 545 .read = { gic_dist_readb, gic_dist_readw, gic_dist_readl, }, 546 .write = { gic_dist_writeb, gic_dist_writew, gic_dist_writel, }, 547 }, 548 .endianness = DEVICE_NATIVE_ENDIAN, 549 }; 550 551 static uint32_t gic_cpu_read(GICState *s, int cpu, int offset) 552 { 553 switch (offset) { 554 case 0x00: /* Control */ 555 return s->cpu_enabled[cpu]; 556 case 0x04: /* Priority mask */ 557 return s->priority_mask[cpu]; 558 case 0x08: /* Binary Point */ 559 /* ??? Not implemented. */ 560 return 0; 561 case 0x0c: /* Acknowledge */ 562 return gic_acknowledge_irq(s, cpu); 563 case 0x14: /* Running Priority */ 564 return s->running_priority[cpu]; 565 case 0x18: /* Highest Pending Interrupt */ 566 return s->current_pending[cpu]; 567 default: 568 qemu_log_mask(LOG_GUEST_ERROR, 569 "gic_cpu_read: Bad offset %x\n", (int)offset); 570 return 0; 571 } 572 } 573 574 static void gic_cpu_write(GICState *s, int cpu, int offset, uint32_t value) 575 { 576 switch (offset) { 577 case 0x00: /* Control */ 578 s->cpu_enabled[cpu] = (value & 1); 579 DPRINTF("CPU %d %sabled\n", cpu, s->cpu_enabled[cpu] ? "En" : "Dis"); 580 break; 581 case 0x04: /* Priority mask */ 582 s->priority_mask[cpu] = (value & 0xff); 583 break; 584 case 0x08: /* Binary Point */ 585 /* ??? Not implemented. */ 586 break; 587 case 0x10: /* End Of Interrupt */ 588 return gic_complete_irq(s, cpu, value & 0x3ff); 589 default: 590 qemu_log_mask(LOG_GUEST_ERROR, 591 "gic_cpu_write: Bad offset %x\n", (int)offset); 592 return; 593 } 594 gic_update(s); 595 } 596 597 /* Wrappers to read/write the GIC CPU interface for the current CPU */ 598 static uint64_t gic_thiscpu_read(void *opaque, hwaddr addr, 599 unsigned size) 600 { 601 GICState *s = (GICState *)opaque; 602 return gic_cpu_read(s, gic_get_current_cpu(s), addr); 603 } 604 605 static void gic_thiscpu_write(void *opaque, hwaddr addr, 606 uint64_t value, unsigned size) 607 { 608 GICState *s = (GICState *)opaque; 609 gic_cpu_write(s, gic_get_current_cpu(s), addr, value); 610 } 611 612 /* Wrappers to read/write the GIC CPU interface for a specific CPU. 613 * These just decode the opaque pointer into GICState* + cpu id. 614 */ 615 static uint64_t gic_do_cpu_read(void *opaque, hwaddr addr, 616 unsigned size) 617 { 618 GICState **backref = (GICState **)opaque; 619 GICState *s = *backref; 620 int id = (backref - s->backref); 621 return gic_cpu_read(s, id, addr); 622 } 623 624 static void gic_do_cpu_write(void *opaque, hwaddr addr, 625 uint64_t value, unsigned size) 626 { 627 GICState **backref = (GICState **)opaque; 628 GICState *s = *backref; 629 int id = (backref - s->backref); 630 gic_cpu_write(s, id, addr, value); 631 } 632 633 static const MemoryRegionOps gic_thiscpu_ops = { 634 .read = gic_thiscpu_read, 635 .write = gic_thiscpu_write, 636 .endianness = DEVICE_NATIVE_ENDIAN, 637 }; 638 639 static const MemoryRegionOps gic_cpu_ops = { 640 .read = gic_do_cpu_read, 641 .write = gic_do_cpu_write, 642 .endianness = DEVICE_NATIVE_ENDIAN, 643 }; 644 645 void gic_init_irqs_and_distributor(GICState *s, int num_irq) 646 { 647 SysBusDevice *sbd = SYS_BUS_DEVICE(s); 648 int i; 649 650 i = s->num_irq - GIC_INTERNAL; 651 /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU. 652 * GPIO array layout is thus: 653 * [0..N-1] SPIs 654 * [N..N+31] PPIs for CPU 0 655 * [N+32..N+63] PPIs for CPU 1 656 * ... 657 */ 658 if (s->revision != REV_NVIC) { 659 i += (GIC_INTERNAL * s->num_cpu); 660 } 661 qdev_init_gpio_in(DEVICE(s), gic_set_irq, i); 662 for (i = 0; i < NUM_CPU(s); i++) { 663 sysbus_init_irq(sbd, &s->parent_irq[i]); 664 } 665 memory_region_init_io(&s->iomem, OBJECT(s), &gic_dist_ops, s, 666 "gic_dist", 0x1000); 667 } 668 669 static void arm_gic_realize(DeviceState *dev, Error **errp) 670 { 671 /* Device instance realize function for the GIC sysbus device */ 672 int i; 673 GICState *s = ARM_GIC(dev); 674 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 675 ARMGICClass *agc = ARM_GIC_GET_CLASS(s); 676 677 agc->parent_realize(dev, errp); 678 if (error_is_set(errp)) { 679 return; 680 } 681 682 gic_init_irqs_and_distributor(s, s->num_irq); 683 684 /* Memory regions for the CPU interfaces (NVIC doesn't have these): 685 * a region for "CPU interface for this core", then a region for 686 * "CPU interface for core 0", "for core 1", ... 687 * NB that the memory region size of 0x100 applies for the 11MPCore 688 * and also cores following the GIC v1 spec (ie A9). 689 * GIC v2 defines a larger memory region (0x1000) so this will need 690 * to be extended when we implement A15. 691 */ 692 memory_region_init_io(&s->cpuiomem[0], OBJECT(s), &gic_thiscpu_ops, s, 693 "gic_cpu", 0x100); 694 for (i = 0; i < NUM_CPU(s); i++) { 695 s->backref[i] = s; 696 memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops, 697 &s->backref[i], "gic_cpu", 0x100); 698 } 699 /* Distributor */ 700 sysbus_init_mmio(sbd, &s->iomem); 701 /* cpu interfaces (one for "current cpu" plus one per cpu) */ 702 for (i = 0; i <= NUM_CPU(s); i++) { 703 sysbus_init_mmio(sbd, &s->cpuiomem[i]); 704 } 705 } 706 707 static void arm_gic_class_init(ObjectClass *klass, void *data) 708 { 709 DeviceClass *dc = DEVICE_CLASS(klass); 710 ARMGICClass *agc = ARM_GIC_CLASS(klass); 711 712 agc->parent_realize = dc->realize; 713 dc->realize = arm_gic_realize; 714 } 715 716 static const TypeInfo arm_gic_info = { 717 .name = TYPE_ARM_GIC, 718 .parent = TYPE_ARM_GIC_COMMON, 719 .instance_size = sizeof(GICState), 720 .class_init = arm_gic_class_init, 721 .class_size = sizeof(ARMGICClass), 722 }; 723 724 static void arm_gic_register_types(void) 725 { 726 type_register_static(&arm_gic_info); 727 } 728 729 type_init(arm_gic_register_types) 730