1 /* 2 * ARM Generic/Distributed Interrupt Controller 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 /* This file contains implementation code for the RealView EB interrupt 11 * controller, MPCore distributed interrupt controller and ARMv7-M 12 * Nested Vectored Interrupt Controller. 13 * It is compiled in two ways: 14 * (1) as a standalone file to produce a sysbus device which is a GIC 15 * that can be used on the realview board and as one of the builtin 16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc) 17 * (2) by being directly #included into armv7m_nvic.c to produce the 18 * armv7m_nvic device. 19 */ 20 21 #include "hw/sysbus.h" 22 #include "gic_internal.h" 23 #include "qom/cpu.h" 24 25 //#define DEBUG_GIC 26 27 #ifdef DEBUG_GIC 28 #define DPRINTF(fmt, ...) \ 29 do { fprintf(stderr, "arm_gic: " fmt , ## __VA_ARGS__); } while (0) 30 #else 31 #define DPRINTF(fmt, ...) do {} while(0) 32 #endif 33 34 static const uint8_t gic_id[] = { 35 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 36 }; 37 38 #define NUM_CPU(s) ((s)->num_cpu) 39 40 static inline int gic_get_current_cpu(GICState *s) 41 { 42 if (s->num_cpu > 1) { 43 return current_cpu->cpu_index; 44 } 45 return 0; 46 } 47 48 /* TODO: Many places that call this routine could be optimized. */ 49 /* Update interrupt status after enabled or pending bits have been changed. */ 50 void gic_update(GICState *s) 51 { 52 int best_irq; 53 int best_prio; 54 int irq; 55 int level; 56 int cpu; 57 int cm; 58 59 for (cpu = 0; cpu < NUM_CPU(s); cpu++) { 60 cm = 1 << cpu; 61 s->current_pending[cpu] = 1023; 62 if (!s->enabled || !s->cpu_enabled[cpu]) { 63 qemu_irq_lower(s->parent_irq[cpu]); 64 return; 65 } 66 best_prio = 0x100; 67 best_irq = 1023; 68 for (irq = 0; irq < s->num_irq; irq++) { 69 if (GIC_TEST_ENABLED(irq, cm) && GIC_TEST_PENDING(irq, cm)) { 70 if (GIC_GET_PRIORITY(irq, cpu) < best_prio) { 71 best_prio = GIC_GET_PRIORITY(irq, cpu); 72 best_irq = irq; 73 } 74 } 75 } 76 level = 0; 77 if (best_prio < s->priority_mask[cpu]) { 78 s->current_pending[cpu] = best_irq; 79 if (best_prio < s->running_priority[cpu]) { 80 DPRINTF("Raised pending IRQ %d (cpu %d)\n", best_irq, cpu); 81 level = 1; 82 } 83 } 84 qemu_set_irq(s->parent_irq[cpu], level); 85 } 86 } 87 88 void gic_set_pending_private(GICState *s, int cpu, int irq) 89 { 90 int cm = 1 << cpu; 91 92 if (GIC_TEST_PENDING(irq, cm)) 93 return; 94 95 DPRINTF("Set %d pending cpu %d\n", irq, cpu); 96 GIC_SET_PENDING(irq, cm); 97 gic_update(s); 98 } 99 100 /* Process a change in an external IRQ input. */ 101 static void gic_set_irq(void *opaque, int irq, int level) 102 { 103 /* Meaning of the 'irq' parameter: 104 * [0..N-1] : external interrupts 105 * [N..N+31] : PPI (internal) interrupts for CPU 0 106 * [N+32..N+63] : PPI (internal interrupts for CPU 1 107 * ... 108 */ 109 GICState *s = (GICState *)opaque; 110 int cm, target; 111 if (irq < (s->num_irq - GIC_INTERNAL)) { 112 /* The first external input line is internal interrupt 32. */ 113 cm = ALL_CPU_MASK; 114 irq += GIC_INTERNAL; 115 target = GIC_TARGET(irq); 116 } else { 117 int cpu; 118 irq -= (s->num_irq - GIC_INTERNAL); 119 cpu = irq / GIC_INTERNAL; 120 irq %= GIC_INTERNAL; 121 cm = 1 << cpu; 122 target = cm; 123 } 124 125 if (level == GIC_TEST_LEVEL(irq, cm)) { 126 return; 127 } 128 129 if (level) { 130 GIC_SET_LEVEL(irq, cm); 131 if (GIC_TEST_EDGE_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) { 132 DPRINTF("Set %d pending mask %x\n", irq, target); 133 GIC_SET_PENDING(irq, target); 134 } 135 } else { 136 GIC_CLEAR_LEVEL(irq, cm); 137 } 138 gic_update(s); 139 } 140 141 static void gic_set_running_irq(GICState *s, int cpu, int irq) 142 { 143 s->running_irq[cpu] = irq; 144 if (irq == 1023) { 145 s->running_priority[cpu] = 0x100; 146 } else { 147 s->running_priority[cpu] = GIC_GET_PRIORITY(irq, cpu); 148 } 149 gic_update(s); 150 } 151 152 uint32_t gic_acknowledge_irq(GICState *s, int cpu) 153 { 154 int new_irq; 155 int cm = 1 << cpu; 156 new_irq = s->current_pending[cpu]; 157 if (new_irq == 1023 158 || GIC_GET_PRIORITY(new_irq, cpu) >= s->running_priority[cpu]) { 159 DPRINTF("ACK no pending IRQ\n"); 160 return 1023; 161 } 162 s->last_active[new_irq][cpu] = s->running_irq[cpu]; 163 /* Clear pending flags for both level and edge triggered interrupts. 164 Level triggered IRQs will be reasserted once they become inactive. */ 165 GIC_CLEAR_PENDING(new_irq, GIC_TEST_MODEL(new_irq) ? ALL_CPU_MASK : cm); 166 gic_set_running_irq(s, cpu, new_irq); 167 DPRINTF("ACK %d\n", new_irq); 168 return new_irq; 169 } 170 171 void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val) 172 { 173 if (irq < GIC_INTERNAL) { 174 s->priority1[irq][cpu] = val; 175 } else { 176 s->priority2[(irq) - GIC_INTERNAL] = val; 177 } 178 } 179 180 void gic_complete_irq(GICState *s, int cpu, int irq) 181 { 182 int update = 0; 183 int cm = 1 << cpu; 184 DPRINTF("EOI %d\n", irq); 185 if (irq >= s->num_irq) { 186 /* This handles two cases: 187 * 1. If software writes the ID of a spurious interrupt [ie 1023] 188 * to the GICC_EOIR, the GIC ignores that write. 189 * 2. If software writes the number of a non-existent interrupt 190 * this must be a subcase of "value written does not match the last 191 * valid interrupt value read from the Interrupt Acknowledge 192 * register" and so this is UNPREDICTABLE. We choose to ignore it. 193 */ 194 return; 195 } 196 if (s->running_irq[cpu] == 1023) 197 return; /* No active IRQ. */ 198 /* Mark level triggered interrupts as pending if they are still 199 raised. */ 200 if (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm) 201 && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) { 202 DPRINTF("Set %d pending mask %x\n", irq, cm); 203 GIC_SET_PENDING(irq, cm); 204 update = 1; 205 } 206 if (irq != s->running_irq[cpu]) { 207 /* Complete an IRQ that is not currently running. */ 208 int tmp = s->running_irq[cpu]; 209 while (s->last_active[tmp][cpu] != 1023) { 210 if (s->last_active[tmp][cpu] == irq) { 211 s->last_active[tmp][cpu] = s->last_active[irq][cpu]; 212 break; 213 } 214 tmp = s->last_active[tmp][cpu]; 215 } 216 if (update) { 217 gic_update(s); 218 } 219 } else { 220 /* Complete the current running IRQ. */ 221 gic_set_running_irq(s, cpu, s->last_active[s->running_irq[cpu]][cpu]); 222 } 223 } 224 225 static uint32_t gic_dist_readb(void *opaque, hwaddr offset) 226 { 227 GICState *s = (GICState *)opaque; 228 uint32_t res; 229 int irq; 230 int i; 231 int cpu; 232 int cm; 233 int mask; 234 235 cpu = gic_get_current_cpu(s); 236 cm = 1 << cpu; 237 if (offset < 0x100) { 238 if (offset == 0) 239 return s->enabled; 240 if (offset == 4) 241 return ((s->num_irq / 32) - 1) | ((NUM_CPU(s) - 1) << 5); 242 if (offset < 0x08) 243 return 0; 244 if (offset >= 0x80) { 245 /* Interrupt Security , RAZ/WI */ 246 return 0; 247 } 248 goto bad_reg; 249 } else if (offset < 0x200) { 250 /* Interrupt Set/Clear Enable. */ 251 if (offset < 0x180) 252 irq = (offset - 0x100) * 8; 253 else 254 irq = (offset - 0x180) * 8; 255 irq += GIC_BASE_IRQ; 256 if (irq >= s->num_irq) 257 goto bad_reg; 258 res = 0; 259 for (i = 0; i < 8; i++) { 260 if (GIC_TEST_ENABLED(irq + i, cm)) { 261 res |= (1 << i); 262 } 263 } 264 } else if (offset < 0x300) { 265 /* Interrupt Set/Clear Pending. */ 266 if (offset < 0x280) 267 irq = (offset - 0x200) * 8; 268 else 269 irq = (offset - 0x280) * 8; 270 irq += GIC_BASE_IRQ; 271 if (irq >= s->num_irq) 272 goto bad_reg; 273 res = 0; 274 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 275 for (i = 0; i < 8; i++) { 276 if (GIC_TEST_PENDING(irq + i, mask)) { 277 res |= (1 << i); 278 } 279 } 280 } else if (offset < 0x400) { 281 /* Interrupt Active. */ 282 irq = (offset - 0x300) * 8 + GIC_BASE_IRQ; 283 if (irq >= s->num_irq) 284 goto bad_reg; 285 res = 0; 286 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 287 for (i = 0; i < 8; i++) { 288 if (GIC_TEST_ACTIVE(irq + i, mask)) { 289 res |= (1 << i); 290 } 291 } 292 } else if (offset < 0x800) { 293 /* Interrupt Priority. */ 294 irq = (offset - 0x400) + GIC_BASE_IRQ; 295 if (irq >= s->num_irq) 296 goto bad_reg; 297 res = GIC_GET_PRIORITY(irq, cpu); 298 } else if (offset < 0xc00) { 299 /* Interrupt CPU Target. */ 300 if (s->num_cpu == 1 && s->revision != REV_11MPCORE) { 301 /* For uniprocessor GICs these RAZ/WI */ 302 res = 0; 303 } else { 304 irq = (offset - 0x800) + GIC_BASE_IRQ; 305 if (irq >= s->num_irq) { 306 goto bad_reg; 307 } 308 if (irq >= 29 && irq <= 31) { 309 res = cm; 310 } else { 311 res = GIC_TARGET(irq); 312 } 313 } 314 } else if (offset < 0xf00) { 315 /* Interrupt Configuration. */ 316 irq = (offset - 0xc00) * 2 + GIC_BASE_IRQ; 317 if (irq >= s->num_irq) 318 goto bad_reg; 319 res = 0; 320 for (i = 0; i < 4; i++) { 321 if (GIC_TEST_MODEL(irq + i)) 322 res |= (1 << (i * 2)); 323 if (GIC_TEST_EDGE_TRIGGER(irq + i)) 324 res |= (2 << (i * 2)); 325 } 326 } else if (offset < 0xfe0) { 327 goto bad_reg; 328 } else /* offset >= 0xfe0 */ { 329 if (offset & 3) { 330 res = 0; 331 } else { 332 res = gic_id[(offset - 0xfe0) >> 2]; 333 } 334 } 335 return res; 336 bad_reg: 337 qemu_log_mask(LOG_GUEST_ERROR, 338 "gic_dist_readb: Bad offset %x\n", (int)offset); 339 return 0; 340 } 341 342 static uint32_t gic_dist_readw(void *opaque, hwaddr offset) 343 { 344 uint32_t val; 345 val = gic_dist_readb(opaque, offset); 346 val |= gic_dist_readb(opaque, offset + 1) << 8; 347 return val; 348 } 349 350 static uint32_t gic_dist_readl(void *opaque, hwaddr offset) 351 { 352 uint32_t val; 353 val = gic_dist_readw(opaque, offset); 354 val |= gic_dist_readw(opaque, offset + 2) << 16; 355 return val; 356 } 357 358 static void gic_dist_writeb(void *opaque, hwaddr offset, 359 uint32_t value) 360 { 361 GICState *s = (GICState *)opaque; 362 int irq; 363 int i; 364 int cpu; 365 366 cpu = gic_get_current_cpu(s); 367 if (offset < 0x100) { 368 if (offset == 0) { 369 s->enabled = (value & 1); 370 DPRINTF("Distribution %sabled\n", s->enabled ? "En" : "Dis"); 371 } else if (offset < 4) { 372 /* ignored. */ 373 } else if (offset >= 0x80) { 374 /* Interrupt Security Registers, RAZ/WI */ 375 } else { 376 goto bad_reg; 377 } 378 } else if (offset < 0x180) { 379 /* Interrupt Set Enable. */ 380 irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; 381 if (irq >= s->num_irq) 382 goto bad_reg; 383 if (irq < GIC_NR_SGIS) { 384 value = 0xff; 385 } 386 387 for (i = 0; i < 8; i++) { 388 if (value & (1 << i)) { 389 int mask = 390 (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq + i); 391 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 392 393 if (!GIC_TEST_ENABLED(irq + i, cm)) { 394 DPRINTF("Enabled IRQ %d\n", irq + i); 395 } 396 GIC_SET_ENABLED(irq + i, cm); 397 /* If a raised level triggered IRQ enabled then mark 398 is as pending. */ 399 if (GIC_TEST_LEVEL(irq + i, mask) 400 && !GIC_TEST_EDGE_TRIGGER(irq + i)) { 401 DPRINTF("Set %d pending mask %x\n", irq + i, mask); 402 GIC_SET_PENDING(irq + i, mask); 403 } 404 } 405 } 406 } else if (offset < 0x200) { 407 /* Interrupt Clear Enable. */ 408 irq = (offset - 0x180) * 8 + GIC_BASE_IRQ; 409 if (irq >= s->num_irq) 410 goto bad_reg; 411 if (irq < GIC_NR_SGIS) { 412 value = 0; 413 } 414 415 for (i = 0; i < 8; i++) { 416 if (value & (1 << i)) { 417 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 418 419 if (GIC_TEST_ENABLED(irq + i, cm)) { 420 DPRINTF("Disabled IRQ %d\n", irq + i); 421 } 422 GIC_CLEAR_ENABLED(irq + i, cm); 423 } 424 } 425 } else if (offset < 0x280) { 426 /* Interrupt Set Pending. */ 427 irq = (offset - 0x200) * 8 + GIC_BASE_IRQ; 428 if (irq >= s->num_irq) 429 goto bad_reg; 430 if (irq < GIC_NR_SGIS) { 431 value = 0; 432 } 433 434 for (i = 0; i < 8; i++) { 435 if (value & (1 << i)) { 436 GIC_SET_PENDING(irq + i, GIC_TARGET(irq + i)); 437 } 438 } 439 } else if (offset < 0x300) { 440 /* Interrupt Clear Pending. */ 441 irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; 442 if (irq >= s->num_irq) 443 goto bad_reg; 444 if (irq < GIC_NR_SGIS) { 445 value = 0; 446 } 447 448 for (i = 0; i < 8; i++) { 449 /* ??? This currently clears the pending bit for all CPUs, even 450 for per-CPU interrupts. It's unclear whether this is the 451 corect behavior. */ 452 if (value & (1 << i)) { 453 GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK); 454 } 455 } 456 } else if (offset < 0x400) { 457 /* Interrupt Active. */ 458 goto bad_reg; 459 } else if (offset < 0x800) { 460 /* Interrupt Priority. */ 461 irq = (offset - 0x400) + GIC_BASE_IRQ; 462 if (irq >= s->num_irq) 463 goto bad_reg; 464 gic_set_priority(s, cpu, irq, value); 465 } else if (offset < 0xc00) { 466 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the 467 * annoying exception of the 11MPCore's GIC. 468 */ 469 if (s->num_cpu != 1 || s->revision == REV_11MPCORE) { 470 irq = (offset - 0x800) + GIC_BASE_IRQ; 471 if (irq >= s->num_irq) { 472 goto bad_reg; 473 } 474 if (irq < 29) { 475 value = 0; 476 } else if (irq < GIC_INTERNAL) { 477 value = ALL_CPU_MASK; 478 } 479 s->irq_target[irq] = value & ALL_CPU_MASK; 480 } 481 } else if (offset < 0xf00) { 482 /* Interrupt Configuration. */ 483 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 484 if (irq >= s->num_irq) 485 goto bad_reg; 486 if (irq < GIC_INTERNAL) 487 value |= 0xaa; 488 for (i = 0; i < 4; i++) { 489 if (value & (1 << (i * 2))) { 490 GIC_SET_MODEL(irq + i); 491 } else { 492 GIC_CLEAR_MODEL(irq + i); 493 } 494 if (value & (2 << (i * 2))) { 495 GIC_SET_EDGE_TRIGGER(irq + i); 496 } else { 497 GIC_CLEAR_EDGE_TRIGGER(irq + i); 498 } 499 } 500 } else { 501 /* 0xf00 is only handled for 32-bit writes. */ 502 goto bad_reg; 503 } 504 gic_update(s); 505 return; 506 bad_reg: 507 qemu_log_mask(LOG_GUEST_ERROR, 508 "gic_dist_writeb: Bad offset %x\n", (int)offset); 509 } 510 511 static void gic_dist_writew(void *opaque, hwaddr offset, 512 uint32_t value) 513 { 514 gic_dist_writeb(opaque, offset, value & 0xff); 515 gic_dist_writeb(opaque, offset + 1, value >> 8); 516 } 517 518 static void gic_dist_writel(void *opaque, hwaddr offset, 519 uint32_t value) 520 { 521 GICState *s = (GICState *)opaque; 522 if (offset == 0xf00) { 523 int cpu; 524 int irq; 525 int mask; 526 527 cpu = gic_get_current_cpu(s); 528 irq = value & 0x3ff; 529 switch ((value >> 24) & 3) { 530 case 0: 531 mask = (value >> 16) & ALL_CPU_MASK; 532 break; 533 case 1: 534 mask = ALL_CPU_MASK ^ (1 << cpu); 535 break; 536 case 2: 537 mask = 1 << cpu; 538 break; 539 default: 540 DPRINTF("Bad Soft Int target filter\n"); 541 mask = ALL_CPU_MASK; 542 break; 543 } 544 GIC_SET_PENDING(irq, mask); 545 gic_update(s); 546 return; 547 } 548 gic_dist_writew(opaque, offset, value & 0xffff); 549 gic_dist_writew(opaque, offset + 2, value >> 16); 550 } 551 552 static const MemoryRegionOps gic_dist_ops = { 553 .old_mmio = { 554 .read = { gic_dist_readb, gic_dist_readw, gic_dist_readl, }, 555 .write = { gic_dist_writeb, gic_dist_writew, gic_dist_writel, }, 556 }, 557 .endianness = DEVICE_NATIVE_ENDIAN, 558 }; 559 560 static uint32_t gic_cpu_read(GICState *s, int cpu, int offset) 561 { 562 switch (offset) { 563 case 0x00: /* Control */ 564 return s->cpu_enabled[cpu]; 565 case 0x04: /* Priority mask */ 566 return s->priority_mask[cpu]; 567 case 0x08: /* Binary Point */ 568 /* ??? Not implemented. */ 569 return 0; 570 case 0x0c: /* Acknowledge */ 571 return gic_acknowledge_irq(s, cpu); 572 case 0x14: /* Running Priority */ 573 return s->running_priority[cpu]; 574 case 0x18: /* Highest Pending Interrupt */ 575 return s->current_pending[cpu]; 576 default: 577 qemu_log_mask(LOG_GUEST_ERROR, 578 "gic_cpu_read: Bad offset %x\n", (int)offset); 579 return 0; 580 } 581 } 582 583 static void gic_cpu_write(GICState *s, int cpu, int offset, uint32_t value) 584 { 585 switch (offset) { 586 case 0x00: /* Control */ 587 s->cpu_enabled[cpu] = (value & 1); 588 DPRINTF("CPU %d %sabled\n", cpu, s->cpu_enabled[cpu] ? "En" : "Dis"); 589 break; 590 case 0x04: /* Priority mask */ 591 s->priority_mask[cpu] = (value & 0xff); 592 break; 593 case 0x08: /* Binary Point */ 594 /* ??? Not implemented. */ 595 break; 596 case 0x10: /* End Of Interrupt */ 597 return gic_complete_irq(s, cpu, value & 0x3ff); 598 default: 599 qemu_log_mask(LOG_GUEST_ERROR, 600 "gic_cpu_write: Bad offset %x\n", (int)offset); 601 return; 602 } 603 gic_update(s); 604 } 605 606 /* Wrappers to read/write the GIC CPU interface for the current CPU */ 607 static uint64_t gic_thiscpu_read(void *opaque, hwaddr addr, 608 unsigned size) 609 { 610 GICState *s = (GICState *)opaque; 611 return gic_cpu_read(s, gic_get_current_cpu(s), addr); 612 } 613 614 static void gic_thiscpu_write(void *opaque, hwaddr addr, 615 uint64_t value, unsigned size) 616 { 617 GICState *s = (GICState *)opaque; 618 gic_cpu_write(s, gic_get_current_cpu(s), addr, value); 619 } 620 621 /* Wrappers to read/write the GIC CPU interface for a specific CPU. 622 * These just decode the opaque pointer into GICState* + cpu id. 623 */ 624 static uint64_t gic_do_cpu_read(void *opaque, hwaddr addr, 625 unsigned size) 626 { 627 GICState **backref = (GICState **)opaque; 628 GICState *s = *backref; 629 int id = (backref - s->backref); 630 return gic_cpu_read(s, id, addr); 631 } 632 633 static void gic_do_cpu_write(void *opaque, hwaddr addr, 634 uint64_t value, unsigned size) 635 { 636 GICState **backref = (GICState **)opaque; 637 GICState *s = *backref; 638 int id = (backref - s->backref); 639 gic_cpu_write(s, id, addr, value); 640 } 641 642 static const MemoryRegionOps gic_thiscpu_ops = { 643 .read = gic_thiscpu_read, 644 .write = gic_thiscpu_write, 645 .endianness = DEVICE_NATIVE_ENDIAN, 646 }; 647 648 static const MemoryRegionOps gic_cpu_ops = { 649 .read = gic_do_cpu_read, 650 .write = gic_do_cpu_write, 651 .endianness = DEVICE_NATIVE_ENDIAN, 652 }; 653 654 void gic_init_irqs_and_distributor(GICState *s, int num_irq) 655 { 656 SysBusDevice *sbd = SYS_BUS_DEVICE(s); 657 int i; 658 659 i = s->num_irq - GIC_INTERNAL; 660 /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU. 661 * GPIO array layout is thus: 662 * [0..N-1] SPIs 663 * [N..N+31] PPIs for CPU 0 664 * [N+32..N+63] PPIs for CPU 1 665 * ... 666 */ 667 if (s->revision != REV_NVIC) { 668 i += (GIC_INTERNAL * s->num_cpu); 669 } 670 qdev_init_gpio_in(DEVICE(s), gic_set_irq, i); 671 for (i = 0; i < NUM_CPU(s); i++) { 672 sysbus_init_irq(sbd, &s->parent_irq[i]); 673 } 674 memory_region_init_io(&s->iomem, OBJECT(s), &gic_dist_ops, s, 675 "gic_dist", 0x1000); 676 } 677 678 static void arm_gic_realize(DeviceState *dev, Error **errp) 679 { 680 /* Device instance realize function for the GIC sysbus device */ 681 int i; 682 GICState *s = ARM_GIC(dev); 683 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 684 ARMGICClass *agc = ARM_GIC_GET_CLASS(s); 685 686 agc->parent_realize(dev, errp); 687 if (error_is_set(errp)) { 688 return; 689 } 690 691 gic_init_irqs_and_distributor(s, s->num_irq); 692 693 /* Memory regions for the CPU interfaces (NVIC doesn't have these): 694 * a region for "CPU interface for this core", then a region for 695 * "CPU interface for core 0", "for core 1", ... 696 * NB that the memory region size of 0x100 applies for the 11MPCore 697 * and also cores following the GIC v1 spec (ie A9). 698 * GIC v2 defines a larger memory region (0x1000) so this will need 699 * to be extended when we implement A15. 700 */ 701 memory_region_init_io(&s->cpuiomem[0], OBJECT(s), &gic_thiscpu_ops, s, 702 "gic_cpu", 0x100); 703 for (i = 0; i < NUM_CPU(s); i++) { 704 s->backref[i] = s; 705 memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops, 706 &s->backref[i], "gic_cpu", 0x100); 707 } 708 /* Distributor */ 709 sysbus_init_mmio(sbd, &s->iomem); 710 /* cpu interfaces (one for "current cpu" plus one per cpu) */ 711 for (i = 0; i <= NUM_CPU(s); i++) { 712 sysbus_init_mmio(sbd, &s->cpuiomem[i]); 713 } 714 } 715 716 static void arm_gic_class_init(ObjectClass *klass, void *data) 717 { 718 DeviceClass *dc = DEVICE_CLASS(klass); 719 ARMGICClass *agc = ARM_GIC_CLASS(klass); 720 721 agc->parent_realize = dc->realize; 722 dc->realize = arm_gic_realize; 723 } 724 725 static const TypeInfo arm_gic_info = { 726 .name = TYPE_ARM_GIC, 727 .parent = TYPE_ARM_GIC_COMMON, 728 .instance_size = sizeof(GICState), 729 .class_init = arm_gic_class_init, 730 .class_size = sizeof(ARMGICClass), 731 }; 732 733 static void arm_gic_register_types(void) 734 { 735 type_register_static(&arm_gic_info); 736 } 737 738 type_init(arm_gic_register_types) 739