1 /* 2 * ARM Generic/Distributed Interrupt Controller 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 /* This file contains implementation code for the RealView EB interrupt 11 * controller, MPCore distributed interrupt controller and ARMv7-M 12 * Nested Vectored Interrupt Controller. 13 * It is compiled in two ways: 14 * (1) as a standalone file to produce a sysbus device which is a GIC 15 * that can be used on the realview board and as one of the builtin 16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc) 17 * (2) by being directly #included into armv7m_nvic.c to produce the 18 * armv7m_nvic device. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/sysbus.h" 23 #include "gic_internal.h" 24 #include "qapi/error.h" 25 #include "qom/cpu.h" 26 #include "qemu/log.h" 27 #include "trace.h" 28 #include "sysemu/kvm.h" 29 30 /* #define DEBUG_GIC */ 31 32 #ifdef DEBUG_GIC 33 #define DEBUG_GIC_GATE 1 34 #else 35 #define DEBUG_GIC_GATE 0 36 #endif 37 38 #define DPRINTF(fmt, ...) do { \ 39 if (DEBUG_GIC_GATE) { \ 40 fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \ 41 } \ 42 } while (0) 43 44 static const uint8_t gic_id_11mpcore[] = { 45 0x00, 0x00, 0x00, 0x00, 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 46 }; 47 48 static const uint8_t gic_id_gicv1[] = { 49 0x04, 0x00, 0x00, 0x00, 0x90, 0xb3, 0x1b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 50 }; 51 52 static const uint8_t gic_id_gicv2[] = { 53 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 54 }; 55 56 static inline int gic_get_current_cpu(GICState *s) 57 { 58 if (s->num_cpu > 1) { 59 return current_cpu->cpu_index; 60 } 61 return 0; 62 } 63 64 /* Return true if this GIC config has interrupt groups, which is 65 * true if we're a GICv2, or a GICv1 with the security extensions. 66 */ 67 static inline bool gic_has_groups(GICState *s) 68 { 69 return s->revision == 2 || s->security_extn; 70 } 71 72 /* TODO: Many places that call this routine could be optimized. */ 73 /* Update interrupt status after enabled or pending bits have been changed. */ 74 void gic_update(GICState *s) 75 { 76 int best_irq; 77 int best_prio; 78 int irq; 79 int irq_level, fiq_level; 80 int cpu; 81 int cm; 82 83 for (cpu = 0; cpu < s->num_cpu; cpu++) { 84 cm = 1 << cpu; 85 s->current_pending[cpu] = 1023; 86 if (!(s->ctlr & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1)) 87 || !(s->cpu_ctlr[cpu] & (GICC_CTLR_EN_GRP0 | GICC_CTLR_EN_GRP1))) { 88 qemu_irq_lower(s->parent_irq[cpu]); 89 qemu_irq_lower(s->parent_fiq[cpu]); 90 continue; 91 } 92 best_prio = 0x100; 93 best_irq = 1023; 94 for (irq = 0; irq < s->num_irq; irq++) { 95 if (GIC_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm) && 96 (!GIC_TEST_ACTIVE(irq, cm)) && 97 (irq < GIC_INTERNAL || GIC_TARGET(irq) & cm)) { 98 if (GIC_GET_PRIORITY(irq, cpu) < best_prio) { 99 best_prio = GIC_GET_PRIORITY(irq, cpu); 100 best_irq = irq; 101 } 102 } 103 } 104 105 if (best_irq != 1023) { 106 trace_gic_update_bestirq(cpu, best_irq, best_prio, 107 s->priority_mask[cpu], s->running_priority[cpu]); 108 } 109 110 irq_level = fiq_level = 0; 111 112 if (best_prio < s->priority_mask[cpu]) { 113 s->current_pending[cpu] = best_irq; 114 if (best_prio < s->running_priority[cpu]) { 115 int group = GIC_TEST_GROUP(best_irq, cm); 116 117 if (extract32(s->ctlr, group, 1) && 118 extract32(s->cpu_ctlr[cpu], group, 1)) { 119 if (group == 0 && s->cpu_ctlr[cpu] & GICC_CTLR_FIQ_EN) { 120 DPRINTF("Raised pending FIQ %d (cpu %d)\n", 121 best_irq, cpu); 122 fiq_level = 1; 123 trace_gic_update_set_irq(cpu, "fiq", fiq_level); 124 } else { 125 DPRINTF("Raised pending IRQ %d (cpu %d)\n", 126 best_irq, cpu); 127 irq_level = 1; 128 trace_gic_update_set_irq(cpu, "irq", irq_level); 129 } 130 } 131 } 132 } 133 134 qemu_set_irq(s->parent_irq[cpu], irq_level); 135 qemu_set_irq(s->parent_fiq[cpu], fiq_level); 136 } 137 } 138 139 void gic_set_pending_private(GICState *s, int cpu, int irq) 140 { 141 int cm = 1 << cpu; 142 143 if (gic_test_pending(s, irq, cm)) { 144 return; 145 } 146 147 DPRINTF("Set %d pending cpu %d\n", irq, cpu); 148 GIC_SET_PENDING(irq, cm); 149 gic_update(s); 150 } 151 152 static void gic_set_irq_11mpcore(GICState *s, int irq, int level, 153 int cm, int target) 154 { 155 if (level) { 156 GIC_SET_LEVEL(irq, cm); 157 if (GIC_TEST_EDGE_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) { 158 DPRINTF("Set %d pending mask %x\n", irq, target); 159 GIC_SET_PENDING(irq, target); 160 } 161 } else { 162 GIC_CLEAR_LEVEL(irq, cm); 163 } 164 } 165 166 static void gic_set_irq_generic(GICState *s, int irq, int level, 167 int cm, int target) 168 { 169 if (level) { 170 GIC_SET_LEVEL(irq, cm); 171 DPRINTF("Set %d pending mask %x\n", irq, target); 172 if (GIC_TEST_EDGE_TRIGGER(irq)) { 173 GIC_SET_PENDING(irq, target); 174 } 175 } else { 176 GIC_CLEAR_LEVEL(irq, cm); 177 } 178 } 179 180 /* Process a change in an external IRQ input. */ 181 static void gic_set_irq(void *opaque, int irq, int level) 182 { 183 /* Meaning of the 'irq' parameter: 184 * [0..N-1] : external interrupts 185 * [N..N+31] : PPI (internal) interrupts for CPU 0 186 * [N+32..N+63] : PPI (internal interrupts for CPU 1 187 * ... 188 */ 189 GICState *s = (GICState *)opaque; 190 int cm, target; 191 if (irq < (s->num_irq - GIC_INTERNAL)) { 192 /* The first external input line is internal interrupt 32. */ 193 cm = ALL_CPU_MASK; 194 irq += GIC_INTERNAL; 195 target = GIC_TARGET(irq); 196 } else { 197 int cpu; 198 irq -= (s->num_irq - GIC_INTERNAL); 199 cpu = irq / GIC_INTERNAL; 200 irq %= GIC_INTERNAL; 201 cm = 1 << cpu; 202 target = cm; 203 } 204 205 assert(irq >= GIC_NR_SGIS); 206 207 if (level == GIC_TEST_LEVEL(irq, cm)) { 208 return; 209 } 210 211 if (s->revision == REV_11MPCORE) { 212 gic_set_irq_11mpcore(s, irq, level, cm, target); 213 } else { 214 gic_set_irq_generic(s, irq, level, cm, target); 215 } 216 trace_gic_set_irq(irq, level, cm, target); 217 218 gic_update(s); 219 } 220 221 static uint16_t gic_get_current_pending_irq(GICState *s, int cpu, 222 MemTxAttrs attrs) 223 { 224 uint16_t pending_irq = s->current_pending[cpu]; 225 226 if (pending_irq < GIC_MAXIRQ && gic_has_groups(s)) { 227 int group = GIC_TEST_GROUP(pending_irq, (1 << cpu)); 228 /* On a GIC without the security extensions, reading this register 229 * behaves in the same way as a secure access to a GIC with them. 230 */ 231 bool secure = !s->security_extn || attrs.secure; 232 233 if (group == 0 && !secure) { 234 /* Group0 interrupts hidden from Non-secure access */ 235 return 1023; 236 } 237 if (group == 1 && secure && !(s->cpu_ctlr[cpu] & GICC_CTLR_ACK_CTL)) { 238 /* Group1 interrupts only seen by Secure access if 239 * AckCtl bit set. 240 */ 241 return 1022; 242 } 243 } 244 return pending_irq; 245 } 246 247 static int gic_get_group_priority(GICState *s, int cpu, int irq) 248 { 249 /* Return the group priority of the specified interrupt 250 * (which is the top bits of its priority, with the number 251 * of bits masked determined by the applicable binary point register). 252 */ 253 int bpr; 254 uint32_t mask; 255 256 if (gic_has_groups(s) && 257 !(s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) && 258 GIC_TEST_GROUP(irq, (1 << cpu))) { 259 bpr = s->abpr[cpu] - 1; 260 assert(bpr >= 0); 261 } else { 262 bpr = s->bpr[cpu]; 263 } 264 265 /* a BPR of 0 means the group priority bits are [7:1]; 266 * a BPR of 1 means they are [7:2], and so on down to 267 * a BPR of 7 meaning no group priority bits at all. 268 */ 269 mask = ~0U << ((bpr & 7) + 1); 270 271 return GIC_GET_PRIORITY(irq, cpu) & mask; 272 } 273 274 static void gic_activate_irq(GICState *s, int cpu, int irq) 275 { 276 /* Set the appropriate Active Priority Register bit for this IRQ, 277 * and update the running priority. 278 */ 279 int prio = gic_get_group_priority(s, cpu, irq); 280 int preemption_level = prio >> (GIC_MIN_BPR + 1); 281 int regno = preemption_level / 32; 282 int bitno = preemption_level % 32; 283 284 if (gic_has_groups(s) && GIC_TEST_GROUP(irq, (1 << cpu))) { 285 s->nsapr[regno][cpu] |= (1 << bitno); 286 } else { 287 s->apr[regno][cpu] |= (1 << bitno); 288 } 289 290 s->running_priority[cpu] = prio; 291 GIC_SET_ACTIVE(irq, 1 << cpu); 292 } 293 294 static int gic_get_prio_from_apr_bits(GICState *s, int cpu) 295 { 296 /* Recalculate the current running priority for this CPU based 297 * on the set bits in the Active Priority Registers. 298 */ 299 int i; 300 for (i = 0; i < GIC_NR_APRS; i++) { 301 uint32_t apr = s->apr[i][cpu] | s->nsapr[i][cpu]; 302 if (!apr) { 303 continue; 304 } 305 return (i * 32 + ctz32(apr)) << (GIC_MIN_BPR + 1); 306 } 307 return 0x100; 308 } 309 310 static void gic_drop_prio(GICState *s, int cpu, int group) 311 { 312 /* Drop the priority of the currently active interrupt in the 313 * specified group. 314 * 315 * Note that we can guarantee (because of the requirement to nest 316 * GICC_IAR reads [which activate an interrupt and raise priority] 317 * with GICC_EOIR writes [which drop the priority for the interrupt]) 318 * that the interrupt we're being called for is the highest priority 319 * active interrupt, meaning that it has the lowest set bit in the 320 * APR registers. 321 * 322 * If the guest does not honour the ordering constraints then the 323 * behaviour of the GIC is UNPREDICTABLE, which for us means that 324 * the values of the APR registers might become incorrect and the 325 * running priority will be wrong, so interrupts that should preempt 326 * might not do so, and interrupts that should not preempt might do so. 327 */ 328 int i; 329 330 for (i = 0; i < GIC_NR_APRS; i++) { 331 uint32_t *papr = group ? &s->nsapr[i][cpu] : &s->apr[i][cpu]; 332 if (!*papr) { 333 continue; 334 } 335 /* Clear lowest set bit */ 336 *papr &= *papr - 1; 337 break; 338 } 339 340 s->running_priority[cpu] = gic_get_prio_from_apr_bits(s, cpu); 341 } 342 343 uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs) 344 { 345 int ret, irq, src; 346 int cm = 1 << cpu; 347 348 /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately 349 * for the case where this GIC supports grouping and the pending interrupt 350 * is in the wrong group. 351 */ 352 irq = gic_get_current_pending_irq(s, cpu, attrs); 353 trace_gic_acknowledge_irq(cpu, irq); 354 355 if (irq >= GIC_MAXIRQ) { 356 DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq); 357 return irq; 358 } 359 360 if (GIC_GET_PRIORITY(irq, cpu) >= s->running_priority[cpu]) { 361 DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq); 362 return 1023; 363 } 364 365 if (s->revision == REV_11MPCORE) { 366 /* Clear pending flags for both level and edge triggered interrupts. 367 * Level triggered IRQs will be reasserted once they become inactive. 368 */ 369 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 370 ret = irq; 371 } else { 372 if (irq < GIC_NR_SGIS) { 373 /* Lookup the source CPU for the SGI and clear this in the 374 * sgi_pending map. Return the src and clear the overall pending 375 * state on this CPU if the SGI is not pending from any CPUs. 376 */ 377 assert(s->sgi_pending[irq][cpu] != 0); 378 src = ctz32(s->sgi_pending[irq][cpu]); 379 s->sgi_pending[irq][cpu] &= ~(1 << src); 380 if (s->sgi_pending[irq][cpu] == 0) { 381 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 382 } 383 ret = irq | ((src & 0x7) << 10); 384 } else { 385 /* Clear pending state for both level and edge triggered 386 * interrupts. (level triggered interrupts with an active line 387 * remain pending, see gic_test_pending) 388 */ 389 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 390 ret = irq; 391 } 392 } 393 394 gic_activate_irq(s, cpu, irq); 395 gic_update(s); 396 DPRINTF("ACK %d\n", irq); 397 return ret; 398 } 399 400 void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val, 401 MemTxAttrs attrs) 402 { 403 if (s->security_extn && !attrs.secure) { 404 if (!GIC_TEST_GROUP(irq, (1 << cpu))) { 405 return; /* Ignore Non-secure access of Group0 IRQ */ 406 } 407 val = 0x80 | (val >> 1); /* Non-secure view */ 408 } 409 410 if (irq < GIC_INTERNAL) { 411 s->priority1[irq][cpu] = val; 412 } else { 413 s->priority2[(irq) - GIC_INTERNAL] = val; 414 } 415 } 416 417 static uint32_t gic_get_priority(GICState *s, int cpu, int irq, 418 MemTxAttrs attrs) 419 { 420 uint32_t prio = GIC_GET_PRIORITY(irq, cpu); 421 422 if (s->security_extn && !attrs.secure) { 423 if (!GIC_TEST_GROUP(irq, (1 << cpu))) { 424 return 0; /* Non-secure access cannot read priority of Group0 IRQ */ 425 } 426 prio = (prio << 1) & 0xff; /* Non-secure view */ 427 } 428 return prio; 429 } 430 431 static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, 432 MemTxAttrs attrs) 433 { 434 if (s->security_extn && !attrs.secure) { 435 if (s->priority_mask[cpu] & 0x80) { 436 /* Priority Mask in upper half */ 437 pmask = 0x80 | (pmask >> 1); 438 } else { 439 /* Non-secure write ignored if priority mask is in lower half */ 440 return; 441 } 442 } 443 s->priority_mask[cpu] = pmask; 444 } 445 446 static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs) 447 { 448 uint32_t pmask = s->priority_mask[cpu]; 449 450 if (s->security_extn && !attrs.secure) { 451 if (pmask & 0x80) { 452 /* Priority Mask in upper half, return Non-secure view */ 453 pmask = (pmask << 1) & 0xff; 454 } else { 455 /* Priority Mask in lower half, RAZ */ 456 pmask = 0; 457 } 458 } 459 return pmask; 460 } 461 462 static uint32_t gic_get_cpu_control(GICState *s, int cpu, MemTxAttrs attrs) 463 { 464 uint32_t ret = s->cpu_ctlr[cpu]; 465 466 if (s->security_extn && !attrs.secure) { 467 /* Construct the NS banked view of GICC_CTLR from the correct 468 * bits of the S banked view. We don't need to move the bypass 469 * control bits because we don't implement that (IMPDEF) part 470 * of the GIC architecture. 471 */ 472 ret = (ret & (GICC_CTLR_EN_GRP1 | GICC_CTLR_EOIMODE_NS)) >> 1; 473 } 474 return ret; 475 } 476 477 static void gic_set_cpu_control(GICState *s, int cpu, uint32_t value, 478 MemTxAttrs attrs) 479 { 480 uint32_t mask; 481 482 if (s->security_extn && !attrs.secure) { 483 /* The NS view can only write certain bits in the register; 484 * the rest are unchanged 485 */ 486 mask = GICC_CTLR_EN_GRP1; 487 if (s->revision == 2) { 488 mask |= GICC_CTLR_EOIMODE_NS; 489 } 490 s->cpu_ctlr[cpu] &= ~mask; 491 s->cpu_ctlr[cpu] |= (value << 1) & mask; 492 } else { 493 if (s->revision == 2) { 494 mask = s->security_extn ? GICC_CTLR_V2_S_MASK : GICC_CTLR_V2_MASK; 495 } else { 496 mask = s->security_extn ? GICC_CTLR_V1_S_MASK : GICC_CTLR_V1_MASK; 497 } 498 s->cpu_ctlr[cpu] = value & mask; 499 } 500 DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, " 501 "Group1 Interrupts %sabled\n", cpu, 502 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP0) ? "En" : "Dis", 503 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP1) ? "En" : "Dis"); 504 } 505 506 static uint8_t gic_get_running_priority(GICState *s, int cpu, MemTxAttrs attrs) 507 { 508 if ((s->revision != REV_11MPCORE) && (s->running_priority[cpu] > 0xff)) { 509 /* Idle priority */ 510 return 0xff; 511 } 512 513 if (s->security_extn && !attrs.secure) { 514 if (s->running_priority[cpu] & 0x80) { 515 /* Running priority in upper half of range: return the Non-secure 516 * view of the priority. 517 */ 518 return s->running_priority[cpu] << 1; 519 } else { 520 /* Running priority in lower half of range: RAZ */ 521 return 0; 522 } 523 } else { 524 return s->running_priority[cpu]; 525 } 526 } 527 528 /* Return true if we should split priority drop and interrupt deactivation, 529 * ie whether the relevant EOIMode bit is set. 530 */ 531 static bool gic_eoi_split(GICState *s, int cpu, MemTxAttrs attrs) 532 { 533 if (s->revision != 2) { 534 /* Before GICv2 prio-drop and deactivate are not separable */ 535 return false; 536 } 537 if (s->security_extn && !attrs.secure) { 538 return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE_NS; 539 } 540 return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE; 541 } 542 543 static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) 544 { 545 int cm = 1 << cpu; 546 int group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm); 547 548 if (!gic_eoi_split(s, cpu, attrs)) { 549 /* This is UNPREDICTABLE; we choose to ignore it */ 550 qemu_log_mask(LOG_GUEST_ERROR, 551 "gic_deactivate_irq: GICC_DIR write when EOIMode clear"); 552 return; 553 } 554 555 if (s->security_extn && !attrs.secure && !group) { 556 DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq); 557 return; 558 } 559 560 GIC_CLEAR_ACTIVE(irq, cm); 561 } 562 563 void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) 564 { 565 int cm = 1 << cpu; 566 int group; 567 568 DPRINTF("EOI %d\n", irq); 569 if (irq >= s->num_irq) { 570 /* This handles two cases: 571 * 1. If software writes the ID of a spurious interrupt [ie 1023] 572 * to the GICC_EOIR, the GIC ignores that write. 573 * 2. If software writes the number of a non-existent interrupt 574 * this must be a subcase of "value written does not match the last 575 * valid interrupt value read from the Interrupt Acknowledge 576 * register" and so this is UNPREDICTABLE. We choose to ignore it. 577 */ 578 return; 579 } 580 if (s->running_priority[cpu] == 0x100) { 581 return; /* No active IRQ. */ 582 } 583 584 if (s->revision == REV_11MPCORE) { 585 /* Mark level triggered interrupts as pending if they are still 586 raised. */ 587 if (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm) 588 && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) { 589 DPRINTF("Set %d pending mask %x\n", irq, cm); 590 GIC_SET_PENDING(irq, cm); 591 } 592 } 593 594 group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm); 595 596 if (s->security_extn && !attrs.secure && !group) { 597 DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq); 598 return; 599 } 600 601 /* Secure EOI with GICC_CTLR.AckCtl == 0 when the IRQ is a Group 1 602 * interrupt is UNPREDICTABLE. We choose to handle it as if AckCtl == 1, 603 * i.e. go ahead and complete the irq anyway. 604 */ 605 606 gic_drop_prio(s, cpu, group); 607 608 /* In GICv2 the guest can choose to split priority-drop and deactivate */ 609 if (!gic_eoi_split(s, cpu, attrs)) { 610 GIC_CLEAR_ACTIVE(irq, cm); 611 } 612 gic_update(s); 613 } 614 615 static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) 616 { 617 GICState *s = (GICState *)opaque; 618 uint32_t res; 619 int irq; 620 int i; 621 int cpu; 622 int cm; 623 int mask; 624 625 cpu = gic_get_current_cpu(s); 626 cm = 1 << cpu; 627 if (offset < 0x100) { 628 if (offset == 0) { /* GICD_CTLR */ 629 if (s->security_extn && !attrs.secure) { 630 /* The NS bank of this register is just an alias of the 631 * EnableGrp1 bit in the S bank version. 632 */ 633 return extract32(s->ctlr, 1, 1); 634 } else { 635 return s->ctlr; 636 } 637 } 638 if (offset == 4) 639 /* Interrupt Controller Type Register */ 640 return ((s->num_irq / 32) - 1) 641 | ((s->num_cpu - 1) << 5) 642 | (s->security_extn << 10); 643 if (offset < 0x08) 644 return 0; 645 if (offset >= 0x80) { 646 /* Interrupt Group Registers: these RAZ/WI if this is an NS 647 * access to a GIC with the security extensions, or if the GIC 648 * doesn't have groups at all. 649 */ 650 res = 0; 651 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 652 /* Every byte offset holds 8 group status bits */ 653 irq = (offset - 0x080) * 8 + GIC_BASE_IRQ; 654 if (irq >= s->num_irq) { 655 goto bad_reg; 656 } 657 for (i = 0; i < 8; i++) { 658 if (GIC_TEST_GROUP(irq + i, cm)) { 659 res |= (1 << i); 660 } 661 } 662 } 663 return res; 664 } 665 goto bad_reg; 666 } else if (offset < 0x200) { 667 /* Interrupt Set/Clear Enable. */ 668 if (offset < 0x180) 669 irq = (offset - 0x100) * 8; 670 else 671 irq = (offset - 0x180) * 8; 672 irq += GIC_BASE_IRQ; 673 if (irq >= s->num_irq) 674 goto bad_reg; 675 res = 0; 676 for (i = 0; i < 8; i++) { 677 if (s->security_extn && !attrs.secure && 678 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 679 continue; /* Ignore Non-secure access of Group0 IRQ */ 680 } 681 682 if (GIC_TEST_ENABLED(irq + i, cm)) { 683 res |= (1 << i); 684 } 685 } 686 } else if (offset < 0x300) { 687 /* Interrupt Set/Clear Pending. */ 688 if (offset < 0x280) 689 irq = (offset - 0x200) * 8; 690 else 691 irq = (offset - 0x280) * 8; 692 irq += GIC_BASE_IRQ; 693 if (irq >= s->num_irq) 694 goto bad_reg; 695 res = 0; 696 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 697 for (i = 0; i < 8; i++) { 698 if (s->security_extn && !attrs.secure && 699 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 700 continue; /* Ignore Non-secure access of Group0 IRQ */ 701 } 702 703 if (gic_test_pending(s, irq + i, mask)) { 704 res |= (1 << i); 705 } 706 } 707 } else if (offset < 0x400) { 708 /* Interrupt Active. */ 709 irq = (offset - 0x300) * 8 + GIC_BASE_IRQ; 710 if (irq >= s->num_irq) 711 goto bad_reg; 712 res = 0; 713 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 714 for (i = 0; i < 8; i++) { 715 if (s->security_extn && !attrs.secure && 716 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 717 continue; /* Ignore Non-secure access of Group0 IRQ */ 718 } 719 720 if (GIC_TEST_ACTIVE(irq + i, mask)) { 721 res |= (1 << i); 722 } 723 } 724 } else if (offset < 0x800) { 725 /* Interrupt Priority. */ 726 irq = (offset - 0x400) + GIC_BASE_IRQ; 727 if (irq >= s->num_irq) 728 goto bad_reg; 729 res = gic_get_priority(s, cpu, irq, attrs); 730 } else if (offset < 0xc00) { 731 /* Interrupt CPU Target. */ 732 if (s->num_cpu == 1 && s->revision != REV_11MPCORE) { 733 /* For uniprocessor GICs these RAZ/WI */ 734 res = 0; 735 } else { 736 irq = (offset - 0x800) + GIC_BASE_IRQ; 737 if (irq >= s->num_irq) { 738 goto bad_reg; 739 } 740 if (irq >= 29 && irq <= 31) { 741 res = cm; 742 } else { 743 res = GIC_TARGET(irq); 744 } 745 } 746 } else if (offset < 0xf00) { 747 /* Interrupt Configuration. */ 748 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 749 if (irq >= s->num_irq) 750 goto bad_reg; 751 res = 0; 752 for (i = 0; i < 4; i++) { 753 if (s->security_extn && !attrs.secure && 754 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 755 continue; /* Ignore Non-secure access of Group0 IRQ */ 756 } 757 758 if (GIC_TEST_MODEL(irq + i)) 759 res |= (1 << (i * 2)); 760 if (GIC_TEST_EDGE_TRIGGER(irq + i)) 761 res |= (2 << (i * 2)); 762 } 763 } else if (offset < 0xf10) { 764 goto bad_reg; 765 } else if (offset < 0xf30) { 766 if (s->revision == REV_11MPCORE) { 767 goto bad_reg; 768 } 769 770 if (offset < 0xf20) { 771 /* GICD_CPENDSGIRn */ 772 irq = (offset - 0xf10); 773 } else { 774 irq = (offset - 0xf20); 775 /* GICD_SPENDSGIRn */ 776 } 777 778 if (s->security_extn && !attrs.secure && 779 !GIC_TEST_GROUP(irq, 1 << cpu)) { 780 res = 0; /* Ignore Non-secure access of Group0 IRQ */ 781 } else { 782 res = s->sgi_pending[irq][cpu]; 783 } 784 } else if (offset < 0xfd0) { 785 goto bad_reg; 786 } else if (offset < 0x1000) { 787 if (offset & 3) { 788 res = 0; 789 } else { 790 switch (s->revision) { 791 case REV_11MPCORE: 792 res = gic_id_11mpcore[(offset - 0xfd0) >> 2]; 793 break; 794 case 1: 795 res = gic_id_gicv1[(offset - 0xfd0) >> 2]; 796 break; 797 case 2: 798 res = gic_id_gicv2[(offset - 0xfd0) >> 2]; 799 break; 800 default: 801 res = 0; 802 } 803 } 804 } else { 805 g_assert_not_reached(); 806 } 807 return res; 808 bad_reg: 809 qemu_log_mask(LOG_GUEST_ERROR, 810 "gic_dist_readb: Bad offset %x\n", (int)offset); 811 return 0; 812 } 813 814 static MemTxResult gic_dist_read(void *opaque, hwaddr offset, uint64_t *data, 815 unsigned size, MemTxAttrs attrs) 816 { 817 switch (size) { 818 case 1: 819 *data = gic_dist_readb(opaque, offset, attrs); 820 return MEMTX_OK; 821 case 2: 822 *data = gic_dist_readb(opaque, offset, attrs); 823 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 824 return MEMTX_OK; 825 case 4: 826 *data = gic_dist_readb(opaque, offset, attrs); 827 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 828 *data |= gic_dist_readb(opaque, offset + 2, attrs) << 16; 829 *data |= gic_dist_readb(opaque, offset + 3, attrs) << 24; 830 return MEMTX_OK; 831 default: 832 return MEMTX_ERROR; 833 } 834 } 835 836 static void gic_dist_writeb(void *opaque, hwaddr offset, 837 uint32_t value, MemTxAttrs attrs) 838 { 839 GICState *s = (GICState *)opaque; 840 int irq; 841 int i; 842 int cpu; 843 844 cpu = gic_get_current_cpu(s); 845 if (offset < 0x100) { 846 if (offset == 0) { 847 if (s->security_extn && !attrs.secure) { 848 /* NS version is just an alias of the S version's bit 1 */ 849 s->ctlr = deposit32(s->ctlr, 1, 1, value); 850 } else if (gic_has_groups(s)) { 851 s->ctlr = value & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1); 852 } else { 853 s->ctlr = value & GICD_CTLR_EN_GRP0; 854 } 855 DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n", 856 s->ctlr & GICD_CTLR_EN_GRP0 ? "En" : "Dis", 857 s->ctlr & GICD_CTLR_EN_GRP1 ? "En" : "Dis"); 858 } else if (offset < 4) { 859 /* ignored. */ 860 } else if (offset >= 0x80) { 861 /* Interrupt Group Registers: RAZ/WI for NS access to secure 862 * GIC, or for GICs without groups. 863 */ 864 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 865 /* Every byte offset holds 8 group status bits */ 866 irq = (offset - 0x80) * 8 + GIC_BASE_IRQ; 867 if (irq >= s->num_irq) { 868 goto bad_reg; 869 } 870 for (i = 0; i < 8; i++) { 871 /* Group bits are banked for private interrupts */ 872 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 873 if (value & (1 << i)) { 874 /* Group1 (Non-secure) */ 875 GIC_SET_GROUP(irq + i, cm); 876 } else { 877 /* Group0 (Secure) */ 878 GIC_CLEAR_GROUP(irq + i, cm); 879 } 880 } 881 } 882 } else { 883 goto bad_reg; 884 } 885 } else if (offset < 0x180) { 886 /* Interrupt Set Enable. */ 887 irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; 888 if (irq >= s->num_irq) 889 goto bad_reg; 890 if (irq < GIC_NR_SGIS) { 891 value = 0xff; 892 } 893 894 for (i = 0; i < 8; i++) { 895 if (value & (1 << i)) { 896 int mask = 897 (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq + i); 898 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 899 900 if (s->security_extn && !attrs.secure && 901 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 902 continue; /* Ignore Non-secure access of Group0 IRQ */ 903 } 904 905 if (!GIC_TEST_ENABLED(irq + i, cm)) { 906 DPRINTF("Enabled IRQ %d\n", irq + i); 907 trace_gic_enable_irq(irq + i); 908 } 909 GIC_SET_ENABLED(irq + i, cm); 910 /* If a raised level triggered IRQ enabled then mark 911 is as pending. */ 912 if (GIC_TEST_LEVEL(irq + i, mask) 913 && !GIC_TEST_EDGE_TRIGGER(irq + i)) { 914 DPRINTF("Set %d pending mask %x\n", irq + i, mask); 915 GIC_SET_PENDING(irq + i, mask); 916 } 917 } 918 } 919 } else if (offset < 0x200) { 920 /* Interrupt Clear Enable. */ 921 irq = (offset - 0x180) * 8 + GIC_BASE_IRQ; 922 if (irq >= s->num_irq) 923 goto bad_reg; 924 if (irq < GIC_NR_SGIS) { 925 value = 0; 926 } 927 928 for (i = 0; i < 8; i++) { 929 if (value & (1 << i)) { 930 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 931 932 if (s->security_extn && !attrs.secure && 933 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 934 continue; /* Ignore Non-secure access of Group0 IRQ */ 935 } 936 937 if (GIC_TEST_ENABLED(irq + i, cm)) { 938 DPRINTF("Disabled IRQ %d\n", irq + i); 939 trace_gic_disable_irq(irq + i); 940 } 941 GIC_CLEAR_ENABLED(irq + i, cm); 942 } 943 } 944 } else if (offset < 0x280) { 945 /* Interrupt Set Pending. */ 946 irq = (offset - 0x200) * 8 + GIC_BASE_IRQ; 947 if (irq >= s->num_irq) 948 goto bad_reg; 949 if (irq < GIC_NR_SGIS) { 950 value = 0; 951 } 952 953 for (i = 0; i < 8; i++) { 954 if (value & (1 << i)) { 955 if (s->security_extn && !attrs.secure && 956 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 957 continue; /* Ignore Non-secure access of Group0 IRQ */ 958 } 959 960 GIC_SET_PENDING(irq + i, GIC_TARGET(irq + i)); 961 } 962 } 963 } else if (offset < 0x300) { 964 /* Interrupt Clear Pending. */ 965 irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; 966 if (irq >= s->num_irq) 967 goto bad_reg; 968 if (irq < GIC_NR_SGIS) { 969 value = 0; 970 } 971 972 for (i = 0; i < 8; i++) { 973 if (s->security_extn && !attrs.secure && 974 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 975 continue; /* Ignore Non-secure access of Group0 IRQ */ 976 } 977 978 /* ??? This currently clears the pending bit for all CPUs, even 979 for per-CPU interrupts. It's unclear whether this is the 980 corect behavior. */ 981 if (value & (1 << i)) { 982 GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK); 983 } 984 } 985 } else if (offset < 0x400) { 986 /* Interrupt Active. */ 987 goto bad_reg; 988 } else if (offset < 0x800) { 989 /* Interrupt Priority. */ 990 irq = (offset - 0x400) + GIC_BASE_IRQ; 991 if (irq >= s->num_irq) 992 goto bad_reg; 993 gic_set_priority(s, cpu, irq, value, attrs); 994 } else if (offset < 0xc00) { 995 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the 996 * annoying exception of the 11MPCore's GIC. 997 */ 998 if (s->num_cpu != 1 || s->revision == REV_11MPCORE) { 999 irq = (offset - 0x800) + GIC_BASE_IRQ; 1000 if (irq >= s->num_irq) { 1001 goto bad_reg; 1002 } 1003 if (irq < 29) { 1004 value = 0; 1005 } else if (irq < GIC_INTERNAL) { 1006 value = ALL_CPU_MASK; 1007 } 1008 s->irq_target[irq] = value & ALL_CPU_MASK; 1009 } 1010 } else if (offset < 0xf00) { 1011 /* Interrupt Configuration. */ 1012 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 1013 if (irq >= s->num_irq) 1014 goto bad_reg; 1015 if (irq < GIC_NR_SGIS) 1016 value |= 0xaa; 1017 for (i = 0; i < 4; i++) { 1018 if (s->security_extn && !attrs.secure && 1019 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 1020 continue; /* Ignore Non-secure access of Group0 IRQ */ 1021 } 1022 1023 if (s->revision == REV_11MPCORE) { 1024 if (value & (1 << (i * 2))) { 1025 GIC_SET_MODEL(irq + i); 1026 } else { 1027 GIC_CLEAR_MODEL(irq + i); 1028 } 1029 } 1030 if (value & (2 << (i * 2))) { 1031 GIC_SET_EDGE_TRIGGER(irq + i); 1032 } else { 1033 GIC_CLEAR_EDGE_TRIGGER(irq + i); 1034 } 1035 } 1036 } else if (offset < 0xf10) { 1037 /* 0xf00 is only handled for 32-bit writes. */ 1038 goto bad_reg; 1039 } else if (offset < 0xf20) { 1040 /* GICD_CPENDSGIRn */ 1041 if (s->revision == REV_11MPCORE) { 1042 goto bad_reg; 1043 } 1044 irq = (offset - 0xf10); 1045 1046 if (!s->security_extn || attrs.secure || 1047 GIC_TEST_GROUP(irq, 1 << cpu)) { 1048 s->sgi_pending[irq][cpu] &= ~value; 1049 if (s->sgi_pending[irq][cpu] == 0) { 1050 GIC_CLEAR_PENDING(irq, 1 << cpu); 1051 } 1052 } 1053 } else if (offset < 0xf30) { 1054 /* GICD_SPENDSGIRn */ 1055 if (s->revision == REV_11MPCORE) { 1056 goto bad_reg; 1057 } 1058 irq = (offset - 0xf20); 1059 1060 if (!s->security_extn || attrs.secure || 1061 GIC_TEST_GROUP(irq, 1 << cpu)) { 1062 GIC_SET_PENDING(irq, 1 << cpu); 1063 s->sgi_pending[irq][cpu] |= value; 1064 } 1065 } else { 1066 goto bad_reg; 1067 } 1068 gic_update(s); 1069 return; 1070 bad_reg: 1071 qemu_log_mask(LOG_GUEST_ERROR, 1072 "gic_dist_writeb: Bad offset %x\n", (int)offset); 1073 } 1074 1075 static void gic_dist_writew(void *opaque, hwaddr offset, 1076 uint32_t value, MemTxAttrs attrs) 1077 { 1078 gic_dist_writeb(opaque, offset, value & 0xff, attrs); 1079 gic_dist_writeb(opaque, offset + 1, value >> 8, attrs); 1080 } 1081 1082 static void gic_dist_writel(void *opaque, hwaddr offset, 1083 uint32_t value, MemTxAttrs attrs) 1084 { 1085 GICState *s = (GICState *)opaque; 1086 if (offset == 0xf00) { 1087 int cpu; 1088 int irq; 1089 int mask; 1090 int target_cpu; 1091 1092 cpu = gic_get_current_cpu(s); 1093 irq = value & 0x3ff; 1094 switch ((value >> 24) & 3) { 1095 case 0: 1096 mask = (value >> 16) & ALL_CPU_MASK; 1097 break; 1098 case 1: 1099 mask = ALL_CPU_MASK ^ (1 << cpu); 1100 break; 1101 case 2: 1102 mask = 1 << cpu; 1103 break; 1104 default: 1105 DPRINTF("Bad Soft Int target filter\n"); 1106 mask = ALL_CPU_MASK; 1107 break; 1108 } 1109 GIC_SET_PENDING(irq, mask); 1110 target_cpu = ctz32(mask); 1111 while (target_cpu < GIC_NCPU) { 1112 s->sgi_pending[irq][target_cpu] |= (1 << cpu); 1113 mask &= ~(1 << target_cpu); 1114 target_cpu = ctz32(mask); 1115 } 1116 gic_update(s); 1117 return; 1118 } 1119 gic_dist_writew(opaque, offset, value & 0xffff, attrs); 1120 gic_dist_writew(opaque, offset + 2, value >> 16, attrs); 1121 } 1122 1123 static MemTxResult gic_dist_write(void *opaque, hwaddr offset, uint64_t data, 1124 unsigned size, MemTxAttrs attrs) 1125 { 1126 switch (size) { 1127 case 1: 1128 gic_dist_writeb(opaque, offset, data, attrs); 1129 return MEMTX_OK; 1130 case 2: 1131 gic_dist_writew(opaque, offset, data, attrs); 1132 return MEMTX_OK; 1133 case 4: 1134 gic_dist_writel(opaque, offset, data, attrs); 1135 return MEMTX_OK; 1136 default: 1137 return MEMTX_ERROR; 1138 } 1139 } 1140 1141 static inline uint32_t gic_apr_ns_view(GICState *s, int cpu, int regno) 1142 { 1143 /* Return the Nonsecure view of GICC_APR<regno>. This is the 1144 * second half of GICC_NSAPR. 1145 */ 1146 switch (GIC_MIN_BPR) { 1147 case 0: 1148 if (regno < 2) { 1149 return s->nsapr[regno + 2][cpu]; 1150 } 1151 break; 1152 case 1: 1153 if (regno == 0) { 1154 return s->nsapr[regno + 1][cpu]; 1155 } 1156 break; 1157 case 2: 1158 if (regno == 0) { 1159 return extract32(s->nsapr[0][cpu], 16, 16); 1160 } 1161 break; 1162 case 3: 1163 if (regno == 0) { 1164 return extract32(s->nsapr[0][cpu], 8, 8); 1165 } 1166 break; 1167 default: 1168 g_assert_not_reached(); 1169 } 1170 return 0; 1171 } 1172 1173 static inline void gic_apr_write_ns_view(GICState *s, int cpu, int regno, 1174 uint32_t value) 1175 { 1176 /* Write the Nonsecure view of GICC_APR<regno>. */ 1177 switch (GIC_MIN_BPR) { 1178 case 0: 1179 if (regno < 2) { 1180 s->nsapr[regno + 2][cpu] = value; 1181 } 1182 break; 1183 case 1: 1184 if (regno == 0) { 1185 s->nsapr[regno + 1][cpu] = value; 1186 } 1187 break; 1188 case 2: 1189 if (regno == 0) { 1190 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 16, 16, value); 1191 } 1192 break; 1193 case 3: 1194 if (regno == 0) { 1195 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 8, 8, value); 1196 } 1197 break; 1198 default: 1199 g_assert_not_reached(); 1200 } 1201 } 1202 1203 static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset, 1204 uint64_t *data, MemTxAttrs attrs) 1205 { 1206 switch (offset) { 1207 case 0x00: /* Control */ 1208 *data = gic_get_cpu_control(s, cpu, attrs); 1209 break; 1210 case 0x04: /* Priority mask */ 1211 *data = gic_get_priority_mask(s, cpu, attrs); 1212 break; 1213 case 0x08: /* Binary Point */ 1214 if (s->security_extn && !attrs.secure) { 1215 if (s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) { 1216 /* NS view of BPR when CBPR is 1 */ 1217 *data = MIN(s->bpr[cpu] + 1, 7); 1218 } else { 1219 /* BPR is banked. Non-secure copy stored in ABPR. */ 1220 *data = s->abpr[cpu]; 1221 } 1222 } else { 1223 *data = s->bpr[cpu]; 1224 } 1225 break; 1226 case 0x0c: /* Acknowledge */ 1227 *data = gic_acknowledge_irq(s, cpu, attrs); 1228 break; 1229 case 0x14: /* Running Priority */ 1230 *data = gic_get_running_priority(s, cpu, attrs); 1231 break; 1232 case 0x18: /* Highest Pending Interrupt */ 1233 *data = gic_get_current_pending_irq(s, cpu, attrs); 1234 break; 1235 case 0x1c: /* Aliased Binary Point */ 1236 /* GIC v2, no security: ABPR 1237 * GIC v1, no security: not implemented (RAZ/WI) 1238 * With security extensions, secure access: ABPR (alias of NS BPR) 1239 * With security extensions, nonsecure access: RAZ/WI 1240 */ 1241 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 1242 *data = 0; 1243 } else { 1244 *data = s->abpr[cpu]; 1245 } 1246 break; 1247 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 1248 { 1249 int regno = (offset - 0xd0) / 4; 1250 1251 if (regno >= GIC_NR_APRS || s->revision != 2) { 1252 *data = 0; 1253 } else if (s->security_extn && !attrs.secure) { 1254 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ 1255 *data = gic_apr_ns_view(s, regno, cpu); 1256 } else { 1257 *data = s->apr[regno][cpu]; 1258 } 1259 break; 1260 } 1261 case 0xe0: case 0xe4: case 0xe8: case 0xec: 1262 { 1263 int regno = (offset - 0xe0) / 4; 1264 1265 if (regno >= GIC_NR_APRS || s->revision != 2 || !gic_has_groups(s) || 1266 (s->security_extn && !attrs.secure)) { 1267 *data = 0; 1268 } else { 1269 *data = s->nsapr[regno][cpu]; 1270 } 1271 break; 1272 } 1273 default: 1274 qemu_log_mask(LOG_GUEST_ERROR, 1275 "gic_cpu_read: Bad offset %x\n", (int)offset); 1276 *data = 0; 1277 break; 1278 } 1279 return MEMTX_OK; 1280 } 1281 1282 static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset, 1283 uint32_t value, MemTxAttrs attrs) 1284 { 1285 switch (offset) { 1286 case 0x00: /* Control */ 1287 gic_set_cpu_control(s, cpu, value, attrs); 1288 break; 1289 case 0x04: /* Priority mask */ 1290 gic_set_priority_mask(s, cpu, value, attrs); 1291 break; 1292 case 0x08: /* Binary Point */ 1293 if (s->security_extn && !attrs.secure) { 1294 if (s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) { 1295 /* WI when CBPR is 1 */ 1296 return MEMTX_OK; 1297 } else { 1298 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 1299 } 1300 } else { 1301 s->bpr[cpu] = MAX(value & 0x7, GIC_MIN_BPR); 1302 } 1303 break; 1304 case 0x10: /* End Of Interrupt */ 1305 gic_complete_irq(s, cpu, value & 0x3ff, attrs); 1306 return MEMTX_OK; 1307 case 0x1c: /* Aliased Binary Point */ 1308 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 1309 /* unimplemented, or NS access: RAZ/WI */ 1310 return MEMTX_OK; 1311 } else { 1312 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 1313 } 1314 break; 1315 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 1316 { 1317 int regno = (offset - 0xd0) / 4; 1318 1319 if (regno >= GIC_NR_APRS || s->revision != 2) { 1320 return MEMTX_OK; 1321 } 1322 if (s->security_extn && !attrs.secure) { 1323 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ 1324 gic_apr_write_ns_view(s, regno, cpu, value); 1325 } else { 1326 s->apr[regno][cpu] = value; 1327 } 1328 break; 1329 } 1330 case 0xe0: case 0xe4: case 0xe8: case 0xec: 1331 { 1332 int regno = (offset - 0xe0) / 4; 1333 1334 if (regno >= GIC_NR_APRS || s->revision != 2) { 1335 return MEMTX_OK; 1336 } 1337 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 1338 return MEMTX_OK; 1339 } 1340 s->nsapr[regno][cpu] = value; 1341 break; 1342 } 1343 case 0x1000: 1344 /* GICC_DIR */ 1345 gic_deactivate_irq(s, cpu, value & 0x3ff, attrs); 1346 break; 1347 default: 1348 qemu_log_mask(LOG_GUEST_ERROR, 1349 "gic_cpu_write: Bad offset %x\n", (int)offset); 1350 return MEMTX_OK; 1351 } 1352 gic_update(s); 1353 return MEMTX_OK; 1354 } 1355 1356 /* Wrappers to read/write the GIC CPU interface for the current CPU */ 1357 static MemTxResult gic_thiscpu_read(void *opaque, hwaddr addr, uint64_t *data, 1358 unsigned size, MemTxAttrs attrs) 1359 { 1360 GICState *s = (GICState *)opaque; 1361 return gic_cpu_read(s, gic_get_current_cpu(s), addr, data, attrs); 1362 } 1363 1364 static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, 1365 uint64_t value, unsigned size, 1366 MemTxAttrs attrs) 1367 { 1368 GICState *s = (GICState *)opaque; 1369 return gic_cpu_write(s, gic_get_current_cpu(s), addr, value, attrs); 1370 } 1371 1372 /* Wrappers to read/write the GIC CPU interface for a specific CPU. 1373 * These just decode the opaque pointer into GICState* + cpu id. 1374 */ 1375 static MemTxResult gic_do_cpu_read(void *opaque, hwaddr addr, uint64_t *data, 1376 unsigned size, MemTxAttrs attrs) 1377 { 1378 GICState **backref = (GICState **)opaque; 1379 GICState *s = *backref; 1380 int id = (backref - s->backref); 1381 return gic_cpu_read(s, id, addr, data, attrs); 1382 } 1383 1384 static MemTxResult gic_do_cpu_write(void *opaque, hwaddr addr, 1385 uint64_t value, unsigned size, 1386 MemTxAttrs attrs) 1387 { 1388 GICState **backref = (GICState **)opaque; 1389 GICState *s = *backref; 1390 int id = (backref - s->backref); 1391 return gic_cpu_write(s, id, addr, value, attrs); 1392 } 1393 1394 static const MemoryRegionOps gic_ops[2] = { 1395 { 1396 .read_with_attrs = gic_dist_read, 1397 .write_with_attrs = gic_dist_write, 1398 .endianness = DEVICE_NATIVE_ENDIAN, 1399 }, 1400 { 1401 .read_with_attrs = gic_thiscpu_read, 1402 .write_with_attrs = gic_thiscpu_write, 1403 .endianness = DEVICE_NATIVE_ENDIAN, 1404 } 1405 }; 1406 1407 static const MemoryRegionOps gic_cpu_ops = { 1408 .read_with_attrs = gic_do_cpu_read, 1409 .write_with_attrs = gic_do_cpu_write, 1410 .endianness = DEVICE_NATIVE_ENDIAN, 1411 }; 1412 1413 /* This function is used by nvic model */ 1414 void gic_init_irqs_and_distributor(GICState *s) 1415 { 1416 gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops); 1417 } 1418 1419 static void arm_gic_realize(DeviceState *dev, Error **errp) 1420 { 1421 /* Device instance realize function for the GIC sysbus device */ 1422 int i; 1423 GICState *s = ARM_GIC(dev); 1424 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1425 ARMGICClass *agc = ARM_GIC_GET_CLASS(s); 1426 Error *local_err = NULL; 1427 1428 agc->parent_realize(dev, &local_err); 1429 if (local_err) { 1430 error_propagate(errp, local_err); 1431 return; 1432 } 1433 1434 if (kvm_enabled() && !kvm_arm_supports_user_irq()) { 1435 error_setg(errp, "KVM with user space irqchip only works when the " 1436 "host kernel supports KVM_CAP_ARM_USER_IRQ"); 1437 return; 1438 } 1439 1440 /* This creates distributor and main CPU interface (s->cpuiomem[0]) */ 1441 gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops); 1442 1443 /* Extra core-specific regions for the CPU interfaces. This is 1444 * necessary for "franken-GIC" implementations, for example on 1445 * Exynos 4. 1446 * NB that the memory region size of 0x100 applies for the 11MPCore 1447 * and also cores following the GIC v1 spec (ie A9). 1448 * GIC v2 defines a larger memory region (0x1000) so this will need 1449 * to be extended when we implement A15. 1450 */ 1451 for (i = 0; i < s->num_cpu; i++) { 1452 s->backref[i] = s; 1453 memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops, 1454 &s->backref[i], "gic_cpu", 0x100); 1455 sysbus_init_mmio(sbd, &s->cpuiomem[i+1]); 1456 } 1457 } 1458 1459 static void arm_gic_class_init(ObjectClass *klass, void *data) 1460 { 1461 DeviceClass *dc = DEVICE_CLASS(klass); 1462 ARMGICClass *agc = ARM_GIC_CLASS(klass); 1463 1464 device_class_set_parent_realize(dc, arm_gic_realize, &agc->parent_realize); 1465 } 1466 1467 static const TypeInfo arm_gic_info = { 1468 .name = TYPE_ARM_GIC, 1469 .parent = TYPE_ARM_GIC_COMMON, 1470 .instance_size = sizeof(GICState), 1471 .class_init = arm_gic_class_init, 1472 .class_size = sizeof(ARMGICClass), 1473 }; 1474 1475 static void arm_gic_register_types(void) 1476 { 1477 type_register_static(&arm_gic_info); 1478 } 1479 1480 type_init(arm_gic_register_types) 1481