1 /* 2 * ARM Generic/Distributed Interrupt Controller 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 /* This file contains implementation code for the RealView EB interrupt 11 * controller, MPCore distributed interrupt controller and ARMv7-M 12 * Nested Vectored Interrupt Controller. 13 * It is compiled in two ways: 14 * (1) as a standalone file to produce a sysbus device which is a GIC 15 * that can be used on the realview board and as one of the builtin 16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc) 17 * (2) by being directly #included into armv7m_nvic.c to produce the 18 * armv7m_nvic device. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/sysbus.h" 23 #include "gic_internal.h" 24 #include "qapi/error.h" 25 #include "qom/cpu.h" 26 #include "qemu/log.h" 27 #include "trace.h" 28 #include "sysemu/kvm.h" 29 30 /* #define DEBUG_GIC */ 31 32 #ifdef DEBUG_GIC 33 #define DEBUG_GIC_GATE 1 34 #else 35 #define DEBUG_GIC_GATE 0 36 #endif 37 38 #define DPRINTF(fmt, ...) do { \ 39 if (DEBUG_GIC_GATE) { \ 40 fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \ 41 } \ 42 } while (0) 43 44 static const uint8_t gic_id_11mpcore[] = { 45 0x00, 0x00, 0x00, 0x00, 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 46 }; 47 48 static const uint8_t gic_id_gicv1[] = { 49 0x04, 0x00, 0x00, 0x00, 0x90, 0xb3, 0x1b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 50 }; 51 52 static const uint8_t gic_id_gicv2[] = { 53 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 54 }; 55 56 static inline int gic_get_current_cpu(GICState *s) 57 { 58 if (s->num_cpu > 1) { 59 return current_cpu->cpu_index; 60 } 61 return 0; 62 } 63 64 /* Return true if this GIC config has interrupt groups, which is 65 * true if we're a GICv2, or a GICv1 with the security extensions. 66 */ 67 static inline bool gic_has_groups(GICState *s) 68 { 69 return s->revision == 2 || s->security_extn; 70 } 71 72 /* TODO: Many places that call this routine could be optimized. */ 73 /* Update interrupt status after enabled or pending bits have been changed. */ 74 void gic_update(GICState *s) 75 { 76 int best_irq; 77 int best_prio; 78 int irq; 79 int irq_level, fiq_level; 80 int cpu; 81 int cm; 82 83 for (cpu = 0; cpu < s->num_cpu; cpu++) { 84 cm = 1 << cpu; 85 s->current_pending[cpu] = 1023; 86 if (!(s->ctlr & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1)) 87 || !(s->cpu_ctlr[cpu] & (GICC_CTLR_EN_GRP0 | GICC_CTLR_EN_GRP1))) { 88 qemu_irq_lower(s->parent_irq[cpu]); 89 qemu_irq_lower(s->parent_fiq[cpu]); 90 continue; 91 } 92 best_prio = 0x100; 93 best_irq = 1023; 94 for (irq = 0; irq < s->num_irq; irq++) { 95 if (GIC_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm) && 96 (!GIC_TEST_ACTIVE(irq, cm)) && 97 (irq < GIC_INTERNAL || GIC_TARGET(irq) & cm)) { 98 if (GIC_GET_PRIORITY(irq, cpu) < best_prio) { 99 best_prio = GIC_GET_PRIORITY(irq, cpu); 100 best_irq = irq; 101 } 102 } 103 } 104 105 if (best_irq != 1023) { 106 trace_gic_update_bestirq(cpu, best_irq, best_prio, 107 s->priority_mask[cpu], s->running_priority[cpu]); 108 } 109 110 irq_level = fiq_level = 0; 111 112 if (best_prio < s->priority_mask[cpu]) { 113 s->current_pending[cpu] = best_irq; 114 if (best_prio < s->running_priority[cpu]) { 115 int group = GIC_TEST_GROUP(best_irq, cm); 116 117 if (extract32(s->ctlr, group, 1) && 118 extract32(s->cpu_ctlr[cpu], group, 1)) { 119 if (group == 0 && s->cpu_ctlr[cpu] & GICC_CTLR_FIQ_EN) { 120 DPRINTF("Raised pending FIQ %d (cpu %d)\n", 121 best_irq, cpu); 122 fiq_level = 1; 123 trace_gic_update_set_irq(cpu, "fiq", fiq_level); 124 } else { 125 DPRINTF("Raised pending IRQ %d (cpu %d)\n", 126 best_irq, cpu); 127 irq_level = 1; 128 trace_gic_update_set_irq(cpu, "irq", irq_level); 129 } 130 } 131 } 132 } 133 134 qemu_set_irq(s->parent_irq[cpu], irq_level); 135 qemu_set_irq(s->parent_fiq[cpu], fiq_level); 136 } 137 } 138 139 void gic_set_pending_private(GICState *s, int cpu, int irq) 140 { 141 int cm = 1 << cpu; 142 143 if (gic_test_pending(s, irq, cm)) { 144 return; 145 } 146 147 DPRINTF("Set %d pending cpu %d\n", irq, cpu); 148 GIC_SET_PENDING(irq, cm); 149 gic_update(s); 150 } 151 152 static void gic_set_irq_11mpcore(GICState *s, int irq, int level, 153 int cm, int target) 154 { 155 if (level) { 156 GIC_SET_LEVEL(irq, cm); 157 if (GIC_TEST_EDGE_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) { 158 DPRINTF("Set %d pending mask %x\n", irq, target); 159 GIC_SET_PENDING(irq, target); 160 } 161 } else { 162 GIC_CLEAR_LEVEL(irq, cm); 163 } 164 } 165 166 static void gic_set_irq_generic(GICState *s, int irq, int level, 167 int cm, int target) 168 { 169 if (level) { 170 GIC_SET_LEVEL(irq, cm); 171 DPRINTF("Set %d pending mask %x\n", irq, target); 172 if (GIC_TEST_EDGE_TRIGGER(irq)) { 173 GIC_SET_PENDING(irq, target); 174 } 175 } else { 176 GIC_CLEAR_LEVEL(irq, cm); 177 } 178 } 179 180 /* Process a change in an external IRQ input. */ 181 static void gic_set_irq(void *opaque, int irq, int level) 182 { 183 /* Meaning of the 'irq' parameter: 184 * [0..N-1] : external interrupts 185 * [N..N+31] : PPI (internal) interrupts for CPU 0 186 * [N+32..N+63] : PPI (internal interrupts for CPU 1 187 * ... 188 */ 189 GICState *s = (GICState *)opaque; 190 int cm, target; 191 if (irq < (s->num_irq - GIC_INTERNAL)) { 192 /* The first external input line is internal interrupt 32. */ 193 cm = ALL_CPU_MASK; 194 irq += GIC_INTERNAL; 195 target = GIC_TARGET(irq); 196 } else { 197 int cpu; 198 irq -= (s->num_irq - GIC_INTERNAL); 199 cpu = irq / GIC_INTERNAL; 200 irq %= GIC_INTERNAL; 201 cm = 1 << cpu; 202 target = cm; 203 } 204 205 assert(irq >= GIC_NR_SGIS); 206 207 if (level == GIC_TEST_LEVEL(irq, cm)) { 208 return; 209 } 210 211 if (s->revision == REV_11MPCORE) { 212 gic_set_irq_11mpcore(s, irq, level, cm, target); 213 } else { 214 gic_set_irq_generic(s, irq, level, cm, target); 215 } 216 trace_gic_set_irq(irq, level, cm, target); 217 218 gic_update(s); 219 } 220 221 static uint16_t gic_get_current_pending_irq(GICState *s, int cpu, 222 MemTxAttrs attrs) 223 { 224 uint16_t pending_irq = s->current_pending[cpu]; 225 226 if (pending_irq < GIC_MAXIRQ && gic_has_groups(s)) { 227 int group = GIC_TEST_GROUP(pending_irq, (1 << cpu)); 228 /* On a GIC without the security extensions, reading this register 229 * behaves in the same way as a secure access to a GIC with them. 230 */ 231 bool secure = !s->security_extn || attrs.secure; 232 233 if (group == 0 && !secure) { 234 /* Group0 interrupts hidden from Non-secure access */ 235 return 1023; 236 } 237 if (group == 1 && secure && !(s->cpu_ctlr[cpu] & GICC_CTLR_ACK_CTL)) { 238 /* Group1 interrupts only seen by Secure access if 239 * AckCtl bit set. 240 */ 241 return 1022; 242 } 243 } 244 return pending_irq; 245 } 246 247 static int gic_get_group_priority(GICState *s, int cpu, int irq) 248 { 249 /* Return the group priority of the specified interrupt 250 * (which is the top bits of its priority, with the number 251 * of bits masked determined by the applicable binary point register). 252 */ 253 int bpr; 254 uint32_t mask; 255 256 if (gic_has_groups(s) && 257 !(s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) && 258 GIC_TEST_GROUP(irq, (1 << cpu))) { 259 bpr = s->abpr[cpu]; 260 } else { 261 bpr = s->bpr[cpu]; 262 } 263 264 /* a BPR of 0 means the group priority bits are [7:1]; 265 * a BPR of 1 means they are [7:2], and so on down to 266 * a BPR of 7 meaning no group priority bits at all. 267 */ 268 mask = ~0U << ((bpr & 7) + 1); 269 270 return GIC_GET_PRIORITY(irq, cpu) & mask; 271 } 272 273 static void gic_activate_irq(GICState *s, int cpu, int irq) 274 { 275 /* Set the appropriate Active Priority Register bit for this IRQ, 276 * and update the running priority. 277 */ 278 int prio = gic_get_group_priority(s, cpu, irq); 279 int preemption_level = prio >> (GIC_MIN_BPR + 1); 280 int regno = preemption_level / 32; 281 int bitno = preemption_level % 32; 282 283 if (gic_has_groups(s) && GIC_TEST_GROUP(irq, (1 << cpu))) { 284 s->nsapr[regno][cpu] |= (1 << bitno); 285 } else { 286 s->apr[regno][cpu] |= (1 << bitno); 287 } 288 289 s->running_priority[cpu] = prio; 290 GIC_SET_ACTIVE(irq, 1 << cpu); 291 } 292 293 static int gic_get_prio_from_apr_bits(GICState *s, int cpu) 294 { 295 /* Recalculate the current running priority for this CPU based 296 * on the set bits in the Active Priority Registers. 297 */ 298 int i; 299 for (i = 0; i < GIC_NR_APRS; i++) { 300 uint32_t apr = s->apr[i][cpu] | s->nsapr[i][cpu]; 301 if (!apr) { 302 continue; 303 } 304 return (i * 32 + ctz32(apr)) << (GIC_MIN_BPR + 1); 305 } 306 return 0x100; 307 } 308 309 static void gic_drop_prio(GICState *s, int cpu, int group) 310 { 311 /* Drop the priority of the currently active interrupt in the 312 * specified group. 313 * 314 * Note that we can guarantee (because of the requirement to nest 315 * GICC_IAR reads [which activate an interrupt and raise priority] 316 * with GICC_EOIR writes [which drop the priority for the interrupt]) 317 * that the interrupt we're being called for is the highest priority 318 * active interrupt, meaning that it has the lowest set bit in the 319 * APR registers. 320 * 321 * If the guest does not honour the ordering constraints then the 322 * behaviour of the GIC is UNPREDICTABLE, which for us means that 323 * the values of the APR registers might become incorrect and the 324 * running priority will be wrong, so interrupts that should preempt 325 * might not do so, and interrupts that should not preempt might do so. 326 */ 327 int i; 328 329 for (i = 0; i < GIC_NR_APRS; i++) { 330 uint32_t *papr = group ? &s->nsapr[i][cpu] : &s->apr[i][cpu]; 331 if (!*papr) { 332 continue; 333 } 334 /* Clear lowest set bit */ 335 *papr &= *papr - 1; 336 break; 337 } 338 339 s->running_priority[cpu] = gic_get_prio_from_apr_bits(s, cpu); 340 } 341 342 uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs) 343 { 344 int ret, irq, src; 345 int cm = 1 << cpu; 346 347 /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately 348 * for the case where this GIC supports grouping and the pending interrupt 349 * is in the wrong group. 350 */ 351 irq = gic_get_current_pending_irq(s, cpu, attrs); 352 trace_gic_acknowledge_irq(cpu, irq); 353 354 if (irq >= GIC_MAXIRQ) { 355 DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq); 356 return irq; 357 } 358 359 if (GIC_GET_PRIORITY(irq, cpu) >= s->running_priority[cpu]) { 360 DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq); 361 return 1023; 362 } 363 364 if (s->revision == REV_11MPCORE) { 365 /* Clear pending flags for both level and edge triggered interrupts. 366 * Level triggered IRQs will be reasserted once they become inactive. 367 */ 368 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 369 ret = irq; 370 } else { 371 if (irq < GIC_NR_SGIS) { 372 /* Lookup the source CPU for the SGI and clear this in the 373 * sgi_pending map. Return the src and clear the overall pending 374 * state on this CPU if the SGI is not pending from any CPUs. 375 */ 376 assert(s->sgi_pending[irq][cpu] != 0); 377 src = ctz32(s->sgi_pending[irq][cpu]); 378 s->sgi_pending[irq][cpu] &= ~(1 << src); 379 if (s->sgi_pending[irq][cpu] == 0) { 380 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 381 } 382 ret = irq | ((src & 0x7) << 10); 383 } else { 384 /* Clear pending state for both level and edge triggered 385 * interrupts. (level triggered interrupts with an active line 386 * remain pending, see gic_test_pending) 387 */ 388 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 389 ret = irq; 390 } 391 } 392 393 gic_activate_irq(s, cpu, irq); 394 gic_update(s); 395 DPRINTF("ACK %d\n", irq); 396 return ret; 397 } 398 399 void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val, 400 MemTxAttrs attrs) 401 { 402 if (s->security_extn && !attrs.secure) { 403 if (!GIC_TEST_GROUP(irq, (1 << cpu))) { 404 return; /* Ignore Non-secure access of Group0 IRQ */ 405 } 406 val = 0x80 | (val >> 1); /* Non-secure view */ 407 } 408 409 if (irq < GIC_INTERNAL) { 410 s->priority1[irq][cpu] = val; 411 } else { 412 s->priority2[(irq) - GIC_INTERNAL] = val; 413 } 414 } 415 416 static uint32_t gic_get_priority(GICState *s, int cpu, int irq, 417 MemTxAttrs attrs) 418 { 419 uint32_t prio = GIC_GET_PRIORITY(irq, cpu); 420 421 if (s->security_extn && !attrs.secure) { 422 if (!GIC_TEST_GROUP(irq, (1 << cpu))) { 423 return 0; /* Non-secure access cannot read priority of Group0 IRQ */ 424 } 425 prio = (prio << 1) & 0xff; /* Non-secure view */ 426 } 427 return prio; 428 } 429 430 static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, 431 MemTxAttrs attrs) 432 { 433 if (s->security_extn && !attrs.secure) { 434 if (s->priority_mask[cpu] & 0x80) { 435 /* Priority Mask in upper half */ 436 pmask = 0x80 | (pmask >> 1); 437 } else { 438 /* Non-secure write ignored if priority mask is in lower half */ 439 return; 440 } 441 } 442 s->priority_mask[cpu] = pmask; 443 } 444 445 static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs) 446 { 447 uint32_t pmask = s->priority_mask[cpu]; 448 449 if (s->security_extn && !attrs.secure) { 450 if (pmask & 0x80) { 451 /* Priority Mask in upper half, return Non-secure view */ 452 pmask = (pmask << 1) & 0xff; 453 } else { 454 /* Priority Mask in lower half, RAZ */ 455 pmask = 0; 456 } 457 } 458 return pmask; 459 } 460 461 static uint32_t gic_get_cpu_control(GICState *s, int cpu, MemTxAttrs attrs) 462 { 463 uint32_t ret = s->cpu_ctlr[cpu]; 464 465 if (s->security_extn && !attrs.secure) { 466 /* Construct the NS banked view of GICC_CTLR from the correct 467 * bits of the S banked view. We don't need to move the bypass 468 * control bits because we don't implement that (IMPDEF) part 469 * of the GIC architecture. 470 */ 471 ret = (ret & (GICC_CTLR_EN_GRP1 | GICC_CTLR_EOIMODE_NS)) >> 1; 472 } 473 return ret; 474 } 475 476 static void gic_set_cpu_control(GICState *s, int cpu, uint32_t value, 477 MemTxAttrs attrs) 478 { 479 uint32_t mask; 480 481 if (s->security_extn && !attrs.secure) { 482 /* The NS view can only write certain bits in the register; 483 * the rest are unchanged 484 */ 485 mask = GICC_CTLR_EN_GRP1; 486 if (s->revision == 2) { 487 mask |= GICC_CTLR_EOIMODE_NS; 488 } 489 s->cpu_ctlr[cpu] &= ~mask; 490 s->cpu_ctlr[cpu] |= (value << 1) & mask; 491 } else { 492 if (s->revision == 2) { 493 mask = s->security_extn ? GICC_CTLR_V2_S_MASK : GICC_CTLR_V2_MASK; 494 } else { 495 mask = s->security_extn ? GICC_CTLR_V1_S_MASK : GICC_CTLR_V1_MASK; 496 } 497 s->cpu_ctlr[cpu] = value & mask; 498 } 499 DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, " 500 "Group1 Interrupts %sabled\n", cpu, 501 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP0) ? "En" : "Dis", 502 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP1) ? "En" : "Dis"); 503 } 504 505 static uint8_t gic_get_running_priority(GICState *s, int cpu, MemTxAttrs attrs) 506 { 507 if (s->security_extn && !attrs.secure) { 508 if (s->running_priority[cpu] & 0x80) { 509 /* Running priority in upper half of range: return the Non-secure 510 * view of the priority. 511 */ 512 return s->running_priority[cpu] << 1; 513 } else { 514 /* Running priority in lower half of range: RAZ */ 515 return 0; 516 } 517 } else { 518 return s->running_priority[cpu]; 519 } 520 } 521 522 /* Return true if we should split priority drop and interrupt deactivation, 523 * ie whether the relevant EOIMode bit is set. 524 */ 525 static bool gic_eoi_split(GICState *s, int cpu, MemTxAttrs attrs) 526 { 527 if (s->revision != 2) { 528 /* Before GICv2 prio-drop and deactivate are not separable */ 529 return false; 530 } 531 if (s->security_extn && !attrs.secure) { 532 return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE_NS; 533 } 534 return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE; 535 } 536 537 static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) 538 { 539 int cm = 1 << cpu; 540 int group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm); 541 542 if (!gic_eoi_split(s, cpu, attrs)) { 543 /* This is UNPREDICTABLE; we choose to ignore it */ 544 qemu_log_mask(LOG_GUEST_ERROR, 545 "gic_deactivate_irq: GICC_DIR write when EOIMode clear"); 546 return; 547 } 548 549 if (s->security_extn && !attrs.secure && !group) { 550 DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq); 551 return; 552 } 553 554 GIC_CLEAR_ACTIVE(irq, cm); 555 } 556 557 void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) 558 { 559 int cm = 1 << cpu; 560 int group; 561 562 DPRINTF("EOI %d\n", irq); 563 if (irq >= s->num_irq) { 564 /* This handles two cases: 565 * 1. If software writes the ID of a spurious interrupt [ie 1023] 566 * to the GICC_EOIR, the GIC ignores that write. 567 * 2. If software writes the number of a non-existent interrupt 568 * this must be a subcase of "value written does not match the last 569 * valid interrupt value read from the Interrupt Acknowledge 570 * register" and so this is UNPREDICTABLE. We choose to ignore it. 571 */ 572 return; 573 } 574 if (s->running_priority[cpu] == 0x100) { 575 return; /* No active IRQ. */ 576 } 577 578 if (s->revision == REV_11MPCORE) { 579 /* Mark level triggered interrupts as pending if they are still 580 raised. */ 581 if (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm) 582 && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) { 583 DPRINTF("Set %d pending mask %x\n", irq, cm); 584 GIC_SET_PENDING(irq, cm); 585 } 586 } 587 588 group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm); 589 590 if (s->security_extn && !attrs.secure && !group) { 591 DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq); 592 return; 593 } 594 595 /* Secure EOI with GICC_CTLR.AckCtl == 0 when the IRQ is a Group 1 596 * interrupt is UNPREDICTABLE. We choose to handle it as if AckCtl == 1, 597 * i.e. go ahead and complete the irq anyway. 598 */ 599 600 gic_drop_prio(s, cpu, group); 601 602 /* In GICv2 the guest can choose to split priority-drop and deactivate */ 603 if (!gic_eoi_split(s, cpu, attrs)) { 604 GIC_CLEAR_ACTIVE(irq, cm); 605 } 606 gic_update(s); 607 } 608 609 static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) 610 { 611 GICState *s = (GICState *)opaque; 612 uint32_t res; 613 int irq; 614 int i; 615 int cpu; 616 int cm; 617 int mask; 618 619 cpu = gic_get_current_cpu(s); 620 cm = 1 << cpu; 621 if (offset < 0x100) { 622 if (offset == 0) { /* GICD_CTLR */ 623 if (s->security_extn && !attrs.secure) { 624 /* The NS bank of this register is just an alias of the 625 * EnableGrp1 bit in the S bank version. 626 */ 627 return extract32(s->ctlr, 1, 1); 628 } else { 629 return s->ctlr; 630 } 631 } 632 if (offset == 4) 633 /* Interrupt Controller Type Register */ 634 return ((s->num_irq / 32) - 1) 635 | ((s->num_cpu - 1) << 5) 636 | (s->security_extn << 10); 637 if (offset < 0x08) 638 return 0; 639 if (offset >= 0x80) { 640 /* Interrupt Group Registers: these RAZ/WI if this is an NS 641 * access to a GIC with the security extensions, or if the GIC 642 * doesn't have groups at all. 643 */ 644 res = 0; 645 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 646 /* Every byte offset holds 8 group status bits */ 647 irq = (offset - 0x080) * 8 + GIC_BASE_IRQ; 648 if (irq >= s->num_irq) { 649 goto bad_reg; 650 } 651 for (i = 0; i < 8; i++) { 652 if (GIC_TEST_GROUP(irq + i, cm)) { 653 res |= (1 << i); 654 } 655 } 656 } 657 return res; 658 } 659 goto bad_reg; 660 } else if (offset < 0x200) { 661 /* Interrupt Set/Clear Enable. */ 662 if (offset < 0x180) 663 irq = (offset - 0x100) * 8; 664 else 665 irq = (offset - 0x180) * 8; 666 irq += GIC_BASE_IRQ; 667 if (irq >= s->num_irq) 668 goto bad_reg; 669 res = 0; 670 for (i = 0; i < 8; i++) { 671 if (s->security_extn && !attrs.secure && 672 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 673 continue; /* Ignore Non-secure access of Group0 IRQ */ 674 } 675 676 if (GIC_TEST_ENABLED(irq + i, cm)) { 677 res |= (1 << i); 678 } 679 } 680 } else if (offset < 0x300) { 681 /* Interrupt Set/Clear Pending. */ 682 if (offset < 0x280) 683 irq = (offset - 0x200) * 8; 684 else 685 irq = (offset - 0x280) * 8; 686 irq += GIC_BASE_IRQ; 687 if (irq >= s->num_irq) 688 goto bad_reg; 689 res = 0; 690 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 691 for (i = 0; i < 8; i++) { 692 if (s->security_extn && !attrs.secure && 693 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 694 continue; /* Ignore Non-secure access of Group0 IRQ */ 695 } 696 697 if (gic_test_pending(s, irq + i, mask)) { 698 res |= (1 << i); 699 } 700 } 701 } else if (offset < 0x400) { 702 /* Interrupt Active. */ 703 irq = (offset - 0x300) * 8 + GIC_BASE_IRQ; 704 if (irq >= s->num_irq) 705 goto bad_reg; 706 res = 0; 707 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 708 for (i = 0; i < 8; i++) { 709 if (s->security_extn && !attrs.secure && 710 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 711 continue; /* Ignore Non-secure access of Group0 IRQ */ 712 } 713 714 if (GIC_TEST_ACTIVE(irq + i, mask)) { 715 res |= (1 << i); 716 } 717 } 718 } else if (offset < 0x800) { 719 /* Interrupt Priority. */ 720 irq = (offset - 0x400) + GIC_BASE_IRQ; 721 if (irq >= s->num_irq) 722 goto bad_reg; 723 res = gic_get_priority(s, cpu, irq, attrs); 724 } else if (offset < 0xc00) { 725 /* Interrupt CPU Target. */ 726 if (s->num_cpu == 1 && s->revision != REV_11MPCORE) { 727 /* For uniprocessor GICs these RAZ/WI */ 728 res = 0; 729 } else { 730 irq = (offset - 0x800) + GIC_BASE_IRQ; 731 if (irq >= s->num_irq) { 732 goto bad_reg; 733 } 734 if (irq >= 29 && irq <= 31) { 735 res = cm; 736 } else { 737 res = GIC_TARGET(irq); 738 } 739 } 740 } else if (offset < 0xf00) { 741 /* Interrupt Configuration. */ 742 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 743 if (irq >= s->num_irq) 744 goto bad_reg; 745 res = 0; 746 for (i = 0; i < 4; i++) { 747 if (s->security_extn && !attrs.secure && 748 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 749 continue; /* Ignore Non-secure access of Group0 IRQ */ 750 } 751 752 if (GIC_TEST_MODEL(irq + i)) 753 res |= (1 << (i * 2)); 754 if (GIC_TEST_EDGE_TRIGGER(irq + i)) 755 res |= (2 << (i * 2)); 756 } 757 } else if (offset < 0xf10) { 758 goto bad_reg; 759 } else if (offset < 0xf30) { 760 if (s->revision == REV_11MPCORE) { 761 goto bad_reg; 762 } 763 764 if (offset < 0xf20) { 765 /* GICD_CPENDSGIRn */ 766 irq = (offset - 0xf10); 767 } else { 768 irq = (offset - 0xf20); 769 /* GICD_SPENDSGIRn */ 770 } 771 772 if (s->security_extn && !attrs.secure && 773 !GIC_TEST_GROUP(irq, 1 << cpu)) { 774 res = 0; /* Ignore Non-secure access of Group0 IRQ */ 775 } else { 776 res = s->sgi_pending[irq][cpu]; 777 } 778 } else if (offset < 0xfd0) { 779 goto bad_reg; 780 } else if (offset < 0x1000) { 781 if (offset & 3) { 782 res = 0; 783 } else { 784 switch (s->revision) { 785 case REV_11MPCORE: 786 res = gic_id_11mpcore[(offset - 0xfd0) >> 2]; 787 break; 788 case 1: 789 res = gic_id_gicv1[(offset - 0xfd0) >> 2]; 790 break; 791 case 2: 792 res = gic_id_gicv2[(offset - 0xfd0) >> 2]; 793 break; 794 default: 795 res = 0; 796 } 797 } 798 } else { 799 g_assert_not_reached(); 800 } 801 return res; 802 bad_reg: 803 qemu_log_mask(LOG_GUEST_ERROR, 804 "gic_dist_readb: Bad offset %x\n", (int)offset); 805 return 0; 806 } 807 808 static MemTxResult gic_dist_read(void *opaque, hwaddr offset, uint64_t *data, 809 unsigned size, MemTxAttrs attrs) 810 { 811 switch (size) { 812 case 1: 813 *data = gic_dist_readb(opaque, offset, attrs); 814 return MEMTX_OK; 815 case 2: 816 *data = gic_dist_readb(opaque, offset, attrs); 817 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 818 return MEMTX_OK; 819 case 4: 820 *data = gic_dist_readb(opaque, offset, attrs); 821 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 822 *data |= gic_dist_readb(opaque, offset + 2, attrs) << 16; 823 *data |= gic_dist_readb(opaque, offset + 3, attrs) << 24; 824 return MEMTX_OK; 825 default: 826 return MEMTX_ERROR; 827 } 828 } 829 830 static void gic_dist_writeb(void *opaque, hwaddr offset, 831 uint32_t value, MemTxAttrs attrs) 832 { 833 GICState *s = (GICState *)opaque; 834 int irq; 835 int i; 836 int cpu; 837 838 cpu = gic_get_current_cpu(s); 839 if (offset < 0x100) { 840 if (offset == 0) { 841 if (s->security_extn && !attrs.secure) { 842 /* NS version is just an alias of the S version's bit 1 */ 843 s->ctlr = deposit32(s->ctlr, 1, 1, value); 844 } else if (gic_has_groups(s)) { 845 s->ctlr = value & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1); 846 } else { 847 s->ctlr = value & GICD_CTLR_EN_GRP0; 848 } 849 DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n", 850 s->ctlr & GICD_CTLR_EN_GRP0 ? "En" : "Dis", 851 s->ctlr & GICD_CTLR_EN_GRP1 ? "En" : "Dis"); 852 } else if (offset < 4) { 853 /* ignored. */ 854 } else if (offset >= 0x80) { 855 /* Interrupt Group Registers: RAZ/WI for NS access to secure 856 * GIC, or for GICs without groups. 857 */ 858 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 859 /* Every byte offset holds 8 group status bits */ 860 irq = (offset - 0x80) * 8 + GIC_BASE_IRQ; 861 if (irq >= s->num_irq) { 862 goto bad_reg; 863 } 864 for (i = 0; i < 8; i++) { 865 /* Group bits are banked for private interrupts */ 866 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 867 if (value & (1 << i)) { 868 /* Group1 (Non-secure) */ 869 GIC_SET_GROUP(irq + i, cm); 870 } else { 871 /* Group0 (Secure) */ 872 GIC_CLEAR_GROUP(irq + i, cm); 873 } 874 } 875 } 876 } else { 877 goto bad_reg; 878 } 879 } else if (offset < 0x180) { 880 /* Interrupt Set Enable. */ 881 irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; 882 if (irq >= s->num_irq) 883 goto bad_reg; 884 if (irq < GIC_NR_SGIS) { 885 value = 0xff; 886 } 887 888 for (i = 0; i < 8; i++) { 889 if (value & (1 << i)) { 890 int mask = 891 (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq + i); 892 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 893 894 if (s->security_extn && !attrs.secure && 895 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 896 continue; /* Ignore Non-secure access of Group0 IRQ */ 897 } 898 899 if (!GIC_TEST_ENABLED(irq + i, cm)) { 900 DPRINTF("Enabled IRQ %d\n", irq + i); 901 trace_gic_enable_irq(irq + i); 902 } 903 GIC_SET_ENABLED(irq + i, cm); 904 /* If a raised level triggered IRQ enabled then mark 905 is as pending. */ 906 if (GIC_TEST_LEVEL(irq + i, mask) 907 && !GIC_TEST_EDGE_TRIGGER(irq + i)) { 908 DPRINTF("Set %d pending mask %x\n", irq + i, mask); 909 GIC_SET_PENDING(irq + i, mask); 910 } 911 } 912 } 913 } else if (offset < 0x200) { 914 /* Interrupt Clear Enable. */ 915 irq = (offset - 0x180) * 8 + GIC_BASE_IRQ; 916 if (irq >= s->num_irq) 917 goto bad_reg; 918 if (irq < GIC_NR_SGIS) { 919 value = 0; 920 } 921 922 for (i = 0; i < 8; i++) { 923 if (value & (1 << i)) { 924 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 925 926 if (s->security_extn && !attrs.secure && 927 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 928 continue; /* Ignore Non-secure access of Group0 IRQ */ 929 } 930 931 if (GIC_TEST_ENABLED(irq + i, cm)) { 932 DPRINTF("Disabled IRQ %d\n", irq + i); 933 trace_gic_disable_irq(irq + i); 934 } 935 GIC_CLEAR_ENABLED(irq + i, cm); 936 } 937 } 938 } else if (offset < 0x280) { 939 /* Interrupt Set Pending. */ 940 irq = (offset - 0x200) * 8 + GIC_BASE_IRQ; 941 if (irq >= s->num_irq) 942 goto bad_reg; 943 if (irq < GIC_NR_SGIS) { 944 value = 0; 945 } 946 947 for (i = 0; i < 8; i++) { 948 if (value & (1 << i)) { 949 if (s->security_extn && !attrs.secure && 950 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 951 continue; /* Ignore Non-secure access of Group0 IRQ */ 952 } 953 954 GIC_SET_PENDING(irq + i, GIC_TARGET(irq + i)); 955 } 956 } 957 } else if (offset < 0x300) { 958 /* Interrupt Clear Pending. */ 959 irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; 960 if (irq >= s->num_irq) 961 goto bad_reg; 962 if (irq < GIC_NR_SGIS) { 963 value = 0; 964 } 965 966 for (i = 0; i < 8; i++) { 967 if (s->security_extn && !attrs.secure && 968 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 969 continue; /* Ignore Non-secure access of Group0 IRQ */ 970 } 971 972 /* ??? This currently clears the pending bit for all CPUs, even 973 for per-CPU interrupts. It's unclear whether this is the 974 corect behavior. */ 975 if (value & (1 << i)) { 976 GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK); 977 } 978 } 979 } else if (offset < 0x400) { 980 /* Interrupt Active. */ 981 goto bad_reg; 982 } else if (offset < 0x800) { 983 /* Interrupt Priority. */ 984 irq = (offset - 0x400) + GIC_BASE_IRQ; 985 if (irq >= s->num_irq) 986 goto bad_reg; 987 gic_set_priority(s, cpu, irq, value, attrs); 988 } else if (offset < 0xc00) { 989 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the 990 * annoying exception of the 11MPCore's GIC. 991 */ 992 if (s->num_cpu != 1 || s->revision == REV_11MPCORE) { 993 irq = (offset - 0x800) + GIC_BASE_IRQ; 994 if (irq >= s->num_irq) { 995 goto bad_reg; 996 } 997 if (irq < 29) { 998 value = 0; 999 } else if (irq < GIC_INTERNAL) { 1000 value = ALL_CPU_MASK; 1001 } 1002 s->irq_target[irq] = value & ALL_CPU_MASK; 1003 } 1004 } else if (offset < 0xf00) { 1005 /* Interrupt Configuration. */ 1006 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 1007 if (irq >= s->num_irq) 1008 goto bad_reg; 1009 if (irq < GIC_NR_SGIS) 1010 value |= 0xaa; 1011 for (i = 0; i < 4; i++) { 1012 if (s->security_extn && !attrs.secure && 1013 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 1014 continue; /* Ignore Non-secure access of Group0 IRQ */ 1015 } 1016 1017 if (s->revision == REV_11MPCORE) { 1018 if (value & (1 << (i * 2))) { 1019 GIC_SET_MODEL(irq + i); 1020 } else { 1021 GIC_CLEAR_MODEL(irq + i); 1022 } 1023 } 1024 if (value & (2 << (i * 2))) { 1025 GIC_SET_EDGE_TRIGGER(irq + i); 1026 } else { 1027 GIC_CLEAR_EDGE_TRIGGER(irq + i); 1028 } 1029 } 1030 } else if (offset < 0xf10) { 1031 /* 0xf00 is only handled for 32-bit writes. */ 1032 goto bad_reg; 1033 } else if (offset < 0xf20) { 1034 /* GICD_CPENDSGIRn */ 1035 if (s->revision == REV_11MPCORE) { 1036 goto bad_reg; 1037 } 1038 irq = (offset - 0xf10); 1039 1040 if (!s->security_extn || attrs.secure || 1041 GIC_TEST_GROUP(irq, 1 << cpu)) { 1042 s->sgi_pending[irq][cpu] &= ~value; 1043 if (s->sgi_pending[irq][cpu] == 0) { 1044 GIC_CLEAR_PENDING(irq, 1 << cpu); 1045 } 1046 } 1047 } else if (offset < 0xf30) { 1048 /* GICD_SPENDSGIRn */ 1049 if (s->revision == REV_11MPCORE) { 1050 goto bad_reg; 1051 } 1052 irq = (offset - 0xf20); 1053 1054 if (!s->security_extn || attrs.secure || 1055 GIC_TEST_GROUP(irq, 1 << cpu)) { 1056 GIC_SET_PENDING(irq, 1 << cpu); 1057 s->sgi_pending[irq][cpu] |= value; 1058 } 1059 } else { 1060 goto bad_reg; 1061 } 1062 gic_update(s); 1063 return; 1064 bad_reg: 1065 qemu_log_mask(LOG_GUEST_ERROR, 1066 "gic_dist_writeb: Bad offset %x\n", (int)offset); 1067 } 1068 1069 static void gic_dist_writew(void *opaque, hwaddr offset, 1070 uint32_t value, MemTxAttrs attrs) 1071 { 1072 gic_dist_writeb(opaque, offset, value & 0xff, attrs); 1073 gic_dist_writeb(opaque, offset + 1, value >> 8, attrs); 1074 } 1075 1076 static void gic_dist_writel(void *opaque, hwaddr offset, 1077 uint32_t value, MemTxAttrs attrs) 1078 { 1079 GICState *s = (GICState *)opaque; 1080 if (offset == 0xf00) { 1081 int cpu; 1082 int irq; 1083 int mask; 1084 int target_cpu; 1085 1086 cpu = gic_get_current_cpu(s); 1087 irq = value & 0x3ff; 1088 switch ((value >> 24) & 3) { 1089 case 0: 1090 mask = (value >> 16) & ALL_CPU_MASK; 1091 break; 1092 case 1: 1093 mask = ALL_CPU_MASK ^ (1 << cpu); 1094 break; 1095 case 2: 1096 mask = 1 << cpu; 1097 break; 1098 default: 1099 DPRINTF("Bad Soft Int target filter\n"); 1100 mask = ALL_CPU_MASK; 1101 break; 1102 } 1103 GIC_SET_PENDING(irq, mask); 1104 target_cpu = ctz32(mask); 1105 while (target_cpu < GIC_NCPU) { 1106 s->sgi_pending[irq][target_cpu] |= (1 << cpu); 1107 mask &= ~(1 << target_cpu); 1108 target_cpu = ctz32(mask); 1109 } 1110 gic_update(s); 1111 return; 1112 } 1113 gic_dist_writew(opaque, offset, value & 0xffff, attrs); 1114 gic_dist_writew(opaque, offset + 2, value >> 16, attrs); 1115 } 1116 1117 static MemTxResult gic_dist_write(void *opaque, hwaddr offset, uint64_t data, 1118 unsigned size, MemTxAttrs attrs) 1119 { 1120 switch (size) { 1121 case 1: 1122 gic_dist_writeb(opaque, offset, data, attrs); 1123 return MEMTX_OK; 1124 case 2: 1125 gic_dist_writew(opaque, offset, data, attrs); 1126 return MEMTX_OK; 1127 case 4: 1128 gic_dist_writel(opaque, offset, data, attrs); 1129 return MEMTX_OK; 1130 default: 1131 return MEMTX_ERROR; 1132 } 1133 } 1134 1135 static inline uint32_t gic_apr_ns_view(GICState *s, int cpu, int regno) 1136 { 1137 /* Return the Nonsecure view of GICC_APR<regno>. This is the 1138 * second half of GICC_NSAPR. 1139 */ 1140 switch (GIC_MIN_BPR) { 1141 case 0: 1142 if (regno < 2) { 1143 return s->nsapr[regno + 2][cpu]; 1144 } 1145 break; 1146 case 1: 1147 if (regno == 0) { 1148 return s->nsapr[regno + 1][cpu]; 1149 } 1150 break; 1151 case 2: 1152 if (regno == 0) { 1153 return extract32(s->nsapr[0][cpu], 16, 16); 1154 } 1155 break; 1156 case 3: 1157 if (regno == 0) { 1158 return extract32(s->nsapr[0][cpu], 8, 8); 1159 } 1160 break; 1161 default: 1162 g_assert_not_reached(); 1163 } 1164 return 0; 1165 } 1166 1167 static inline void gic_apr_write_ns_view(GICState *s, int cpu, int regno, 1168 uint32_t value) 1169 { 1170 /* Write the Nonsecure view of GICC_APR<regno>. */ 1171 switch (GIC_MIN_BPR) { 1172 case 0: 1173 if (regno < 2) { 1174 s->nsapr[regno + 2][cpu] = value; 1175 } 1176 break; 1177 case 1: 1178 if (regno == 0) { 1179 s->nsapr[regno + 1][cpu] = value; 1180 } 1181 break; 1182 case 2: 1183 if (regno == 0) { 1184 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 16, 16, value); 1185 } 1186 break; 1187 case 3: 1188 if (regno == 0) { 1189 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 8, 8, value); 1190 } 1191 break; 1192 default: 1193 g_assert_not_reached(); 1194 } 1195 } 1196 1197 static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset, 1198 uint64_t *data, MemTxAttrs attrs) 1199 { 1200 switch (offset) { 1201 case 0x00: /* Control */ 1202 *data = gic_get_cpu_control(s, cpu, attrs); 1203 break; 1204 case 0x04: /* Priority mask */ 1205 *data = gic_get_priority_mask(s, cpu, attrs); 1206 break; 1207 case 0x08: /* Binary Point */ 1208 if (s->security_extn && !attrs.secure) { 1209 /* BPR is banked. Non-secure copy stored in ABPR. */ 1210 *data = s->abpr[cpu]; 1211 } else { 1212 *data = s->bpr[cpu]; 1213 } 1214 break; 1215 case 0x0c: /* Acknowledge */ 1216 *data = gic_acknowledge_irq(s, cpu, attrs); 1217 break; 1218 case 0x14: /* Running Priority */ 1219 *data = gic_get_running_priority(s, cpu, attrs); 1220 break; 1221 case 0x18: /* Highest Pending Interrupt */ 1222 *data = gic_get_current_pending_irq(s, cpu, attrs); 1223 break; 1224 case 0x1c: /* Aliased Binary Point */ 1225 /* GIC v2, no security: ABPR 1226 * GIC v1, no security: not implemented (RAZ/WI) 1227 * With security extensions, secure access: ABPR (alias of NS BPR) 1228 * With security extensions, nonsecure access: RAZ/WI 1229 */ 1230 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 1231 *data = 0; 1232 } else { 1233 *data = s->abpr[cpu]; 1234 } 1235 break; 1236 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 1237 { 1238 int regno = (offset - 0xd0) / 4; 1239 1240 if (regno >= GIC_NR_APRS || s->revision != 2) { 1241 *data = 0; 1242 } else if (s->security_extn && !attrs.secure) { 1243 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ 1244 *data = gic_apr_ns_view(s, regno, cpu); 1245 } else { 1246 *data = s->apr[regno][cpu]; 1247 } 1248 break; 1249 } 1250 case 0xe0: case 0xe4: case 0xe8: case 0xec: 1251 { 1252 int regno = (offset - 0xe0) / 4; 1253 1254 if (regno >= GIC_NR_APRS || s->revision != 2 || !gic_has_groups(s) || 1255 (s->security_extn && !attrs.secure)) { 1256 *data = 0; 1257 } else { 1258 *data = s->nsapr[regno][cpu]; 1259 } 1260 break; 1261 } 1262 default: 1263 qemu_log_mask(LOG_GUEST_ERROR, 1264 "gic_cpu_read: Bad offset %x\n", (int)offset); 1265 *data = 0; 1266 break; 1267 } 1268 return MEMTX_OK; 1269 } 1270 1271 static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset, 1272 uint32_t value, MemTxAttrs attrs) 1273 { 1274 switch (offset) { 1275 case 0x00: /* Control */ 1276 gic_set_cpu_control(s, cpu, value, attrs); 1277 break; 1278 case 0x04: /* Priority mask */ 1279 gic_set_priority_mask(s, cpu, value, attrs); 1280 break; 1281 case 0x08: /* Binary Point */ 1282 if (s->security_extn && !attrs.secure) { 1283 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 1284 } else { 1285 s->bpr[cpu] = MAX(value & 0x7, GIC_MIN_BPR); 1286 } 1287 break; 1288 case 0x10: /* End Of Interrupt */ 1289 gic_complete_irq(s, cpu, value & 0x3ff, attrs); 1290 return MEMTX_OK; 1291 case 0x1c: /* Aliased Binary Point */ 1292 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 1293 /* unimplemented, or NS access: RAZ/WI */ 1294 return MEMTX_OK; 1295 } else { 1296 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 1297 } 1298 break; 1299 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 1300 { 1301 int regno = (offset - 0xd0) / 4; 1302 1303 if (regno >= GIC_NR_APRS || s->revision != 2) { 1304 return MEMTX_OK; 1305 } 1306 if (s->security_extn && !attrs.secure) { 1307 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ 1308 gic_apr_write_ns_view(s, regno, cpu, value); 1309 } else { 1310 s->apr[regno][cpu] = value; 1311 } 1312 break; 1313 } 1314 case 0xe0: case 0xe4: case 0xe8: case 0xec: 1315 { 1316 int regno = (offset - 0xe0) / 4; 1317 1318 if (regno >= GIC_NR_APRS || s->revision != 2) { 1319 return MEMTX_OK; 1320 } 1321 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 1322 return MEMTX_OK; 1323 } 1324 s->nsapr[regno][cpu] = value; 1325 break; 1326 } 1327 case 0x1000: 1328 /* GICC_DIR */ 1329 gic_deactivate_irq(s, cpu, value & 0x3ff, attrs); 1330 break; 1331 default: 1332 qemu_log_mask(LOG_GUEST_ERROR, 1333 "gic_cpu_write: Bad offset %x\n", (int)offset); 1334 return MEMTX_OK; 1335 } 1336 gic_update(s); 1337 return MEMTX_OK; 1338 } 1339 1340 /* Wrappers to read/write the GIC CPU interface for the current CPU */ 1341 static MemTxResult gic_thiscpu_read(void *opaque, hwaddr addr, uint64_t *data, 1342 unsigned size, MemTxAttrs attrs) 1343 { 1344 GICState *s = (GICState *)opaque; 1345 return gic_cpu_read(s, gic_get_current_cpu(s), addr, data, attrs); 1346 } 1347 1348 static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, 1349 uint64_t value, unsigned size, 1350 MemTxAttrs attrs) 1351 { 1352 GICState *s = (GICState *)opaque; 1353 return gic_cpu_write(s, gic_get_current_cpu(s), addr, value, attrs); 1354 } 1355 1356 /* Wrappers to read/write the GIC CPU interface for a specific CPU. 1357 * These just decode the opaque pointer into GICState* + cpu id. 1358 */ 1359 static MemTxResult gic_do_cpu_read(void *opaque, hwaddr addr, uint64_t *data, 1360 unsigned size, MemTxAttrs attrs) 1361 { 1362 GICState **backref = (GICState **)opaque; 1363 GICState *s = *backref; 1364 int id = (backref - s->backref); 1365 return gic_cpu_read(s, id, addr, data, attrs); 1366 } 1367 1368 static MemTxResult gic_do_cpu_write(void *opaque, hwaddr addr, 1369 uint64_t value, unsigned size, 1370 MemTxAttrs attrs) 1371 { 1372 GICState **backref = (GICState **)opaque; 1373 GICState *s = *backref; 1374 int id = (backref - s->backref); 1375 return gic_cpu_write(s, id, addr, value, attrs); 1376 } 1377 1378 static const MemoryRegionOps gic_ops[2] = { 1379 { 1380 .read_with_attrs = gic_dist_read, 1381 .write_with_attrs = gic_dist_write, 1382 .endianness = DEVICE_NATIVE_ENDIAN, 1383 }, 1384 { 1385 .read_with_attrs = gic_thiscpu_read, 1386 .write_with_attrs = gic_thiscpu_write, 1387 .endianness = DEVICE_NATIVE_ENDIAN, 1388 } 1389 }; 1390 1391 static const MemoryRegionOps gic_cpu_ops = { 1392 .read_with_attrs = gic_do_cpu_read, 1393 .write_with_attrs = gic_do_cpu_write, 1394 .endianness = DEVICE_NATIVE_ENDIAN, 1395 }; 1396 1397 /* This function is used by nvic model */ 1398 void gic_init_irqs_and_distributor(GICState *s) 1399 { 1400 gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops); 1401 } 1402 1403 static void arm_gic_realize(DeviceState *dev, Error **errp) 1404 { 1405 /* Device instance realize function for the GIC sysbus device */ 1406 int i; 1407 GICState *s = ARM_GIC(dev); 1408 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1409 ARMGICClass *agc = ARM_GIC_GET_CLASS(s); 1410 Error *local_err = NULL; 1411 1412 agc->parent_realize(dev, &local_err); 1413 if (local_err) { 1414 error_propagate(errp, local_err); 1415 return; 1416 } 1417 1418 if (kvm_enabled() && !kvm_arm_supports_user_irq()) { 1419 error_setg(errp, "KVM with user space irqchip only works when the " 1420 "host kernel supports KVM_CAP_ARM_USER_IRQ"); 1421 return; 1422 } 1423 1424 /* This creates distributor and main CPU interface (s->cpuiomem[0]) */ 1425 gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops); 1426 1427 /* Extra core-specific regions for the CPU interfaces. This is 1428 * necessary for "franken-GIC" implementations, for example on 1429 * Exynos 4. 1430 * NB that the memory region size of 0x100 applies for the 11MPCore 1431 * and also cores following the GIC v1 spec (ie A9). 1432 * GIC v2 defines a larger memory region (0x1000) so this will need 1433 * to be extended when we implement A15. 1434 */ 1435 for (i = 0; i < s->num_cpu; i++) { 1436 s->backref[i] = s; 1437 memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops, 1438 &s->backref[i], "gic_cpu", 0x100); 1439 sysbus_init_mmio(sbd, &s->cpuiomem[i+1]); 1440 } 1441 } 1442 1443 static void arm_gic_class_init(ObjectClass *klass, void *data) 1444 { 1445 DeviceClass *dc = DEVICE_CLASS(klass); 1446 ARMGICClass *agc = ARM_GIC_CLASS(klass); 1447 1448 agc->parent_realize = dc->realize; 1449 dc->realize = arm_gic_realize; 1450 } 1451 1452 static const TypeInfo arm_gic_info = { 1453 .name = TYPE_ARM_GIC, 1454 .parent = TYPE_ARM_GIC_COMMON, 1455 .instance_size = sizeof(GICState), 1456 .class_init = arm_gic_class_init, 1457 .class_size = sizeof(ARMGICClass), 1458 }; 1459 1460 static void arm_gic_register_types(void) 1461 { 1462 type_register_static(&arm_gic_info); 1463 } 1464 1465 type_init(arm_gic_register_types) 1466