1 /* 2 * ARM Generic/Distributed Interrupt Controller 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 /* This file contains implementation code for the RealView EB interrupt 11 * controller, MPCore distributed interrupt controller and ARMv7-M 12 * Nested Vectored Interrupt Controller. 13 * It is compiled in two ways: 14 * (1) as a standalone file to produce a sysbus device which is a GIC 15 * that can be used on the realview board and as one of the builtin 16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc) 17 * (2) by being directly #included into armv7m_nvic.c to produce the 18 * armv7m_nvic device. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/sysbus.h" 23 #include "gic_internal.h" 24 #include "qapi/error.h" 25 #include "qom/cpu.h" 26 #include "qemu/log.h" 27 #include "trace.h" 28 #include "sysemu/kvm.h" 29 30 /* #define DEBUG_GIC */ 31 32 #ifdef DEBUG_GIC 33 #define DEBUG_GIC_GATE 1 34 #else 35 #define DEBUG_GIC_GATE 0 36 #endif 37 38 #define DPRINTF(fmt, ...) do { \ 39 if (DEBUG_GIC_GATE) { \ 40 fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \ 41 } \ 42 } while (0) 43 44 static const uint8_t gic_id_11mpcore[] = { 45 0x00, 0x00, 0x00, 0x00, 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 46 }; 47 48 static const uint8_t gic_id_gicv1[] = { 49 0x04, 0x00, 0x00, 0x00, 0x90, 0xb3, 0x1b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 50 }; 51 52 static const uint8_t gic_id_gicv2[] = { 53 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 54 }; 55 56 static inline int gic_get_current_cpu(GICState *s) 57 { 58 if (s->num_cpu > 1) { 59 return current_cpu->cpu_index; 60 } 61 return 0; 62 } 63 64 static inline int gic_get_current_vcpu(GICState *s) 65 { 66 return gic_get_current_cpu(s) + GIC_NCPU; 67 } 68 69 /* Return true if this GIC config has interrupt groups, which is 70 * true if we're a GICv2, or a GICv1 with the security extensions. 71 */ 72 static inline bool gic_has_groups(GICState *s) 73 { 74 return s->revision == 2 || s->security_extn; 75 } 76 77 static inline bool gic_cpu_ns_access(GICState *s, int cpu, MemTxAttrs attrs) 78 { 79 return !gic_is_vcpu(cpu) && s->security_extn && !attrs.secure; 80 } 81 82 /* TODO: Many places that call this routine could be optimized. */ 83 /* Update interrupt status after enabled or pending bits have been changed. */ 84 static void gic_update(GICState *s) 85 { 86 int best_irq; 87 int best_prio; 88 int irq; 89 int irq_level, fiq_level; 90 int cpu; 91 int cm; 92 93 for (cpu = 0; cpu < s->num_cpu; cpu++) { 94 cm = 1 << cpu; 95 s->current_pending[cpu] = 1023; 96 if (!(s->ctlr & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1)) 97 || !(s->cpu_ctlr[cpu] & (GICC_CTLR_EN_GRP0 | GICC_CTLR_EN_GRP1))) { 98 qemu_irq_lower(s->parent_irq[cpu]); 99 qemu_irq_lower(s->parent_fiq[cpu]); 100 continue; 101 } 102 best_prio = 0x100; 103 best_irq = 1023; 104 for (irq = 0; irq < s->num_irq; irq++) { 105 if (GIC_DIST_TEST_ENABLED(irq, cm) && 106 gic_test_pending(s, irq, cm) && 107 (!GIC_DIST_TEST_ACTIVE(irq, cm)) && 108 (irq < GIC_INTERNAL || GIC_DIST_TARGET(irq) & cm)) { 109 if (GIC_DIST_GET_PRIORITY(irq, cpu) < best_prio) { 110 best_prio = GIC_DIST_GET_PRIORITY(irq, cpu); 111 best_irq = irq; 112 } 113 } 114 } 115 116 if (best_irq != 1023) { 117 trace_gic_update_bestirq(cpu, best_irq, best_prio, 118 s->priority_mask[cpu], s->running_priority[cpu]); 119 } 120 121 irq_level = fiq_level = 0; 122 123 if (best_prio < s->priority_mask[cpu]) { 124 s->current_pending[cpu] = best_irq; 125 if (best_prio < s->running_priority[cpu]) { 126 int group = GIC_DIST_TEST_GROUP(best_irq, cm); 127 128 if (extract32(s->ctlr, group, 1) && 129 extract32(s->cpu_ctlr[cpu], group, 1)) { 130 if (group == 0 && s->cpu_ctlr[cpu] & GICC_CTLR_FIQ_EN) { 131 DPRINTF("Raised pending FIQ %d (cpu %d)\n", 132 best_irq, cpu); 133 fiq_level = 1; 134 trace_gic_update_set_irq(cpu, "fiq", fiq_level); 135 } else { 136 DPRINTF("Raised pending IRQ %d (cpu %d)\n", 137 best_irq, cpu); 138 irq_level = 1; 139 trace_gic_update_set_irq(cpu, "irq", irq_level); 140 } 141 } 142 } 143 } 144 145 qemu_set_irq(s->parent_irq[cpu], irq_level); 146 qemu_set_irq(s->parent_fiq[cpu], fiq_level); 147 } 148 } 149 150 static void gic_set_irq_11mpcore(GICState *s, int irq, int level, 151 int cm, int target) 152 { 153 if (level) { 154 GIC_DIST_SET_LEVEL(irq, cm); 155 if (GIC_DIST_TEST_EDGE_TRIGGER(irq) || GIC_DIST_TEST_ENABLED(irq, cm)) { 156 DPRINTF("Set %d pending mask %x\n", irq, target); 157 GIC_DIST_SET_PENDING(irq, target); 158 } 159 } else { 160 GIC_DIST_CLEAR_LEVEL(irq, cm); 161 } 162 } 163 164 static void gic_set_irq_generic(GICState *s, int irq, int level, 165 int cm, int target) 166 { 167 if (level) { 168 GIC_DIST_SET_LEVEL(irq, cm); 169 DPRINTF("Set %d pending mask %x\n", irq, target); 170 if (GIC_DIST_TEST_EDGE_TRIGGER(irq)) { 171 GIC_DIST_SET_PENDING(irq, target); 172 } 173 } else { 174 GIC_DIST_CLEAR_LEVEL(irq, cm); 175 } 176 } 177 178 /* Process a change in an external IRQ input. */ 179 static void gic_set_irq(void *opaque, int irq, int level) 180 { 181 /* Meaning of the 'irq' parameter: 182 * [0..N-1] : external interrupts 183 * [N..N+31] : PPI (internal) interrupts for CPU 0 184 * [N+32..N+63] : PPI (internal interrupts for CPU 1 185 * ... 186 */ 187 GICState *s = (GICState *)opaque; 188 int cm, target; 189 if (irq < (s->num_irq - GIC_INTERNAL)) { 190 /* The first external input line is internal interrupt 32. */ 191 cm = ALL_CPU_MASK; 192 irq += GIC_INTERNAL; 193 target = GIC_DIST_TARGET(irq); 194 } else { 195 int cpu; 196 irq -= (s->num_irq - GIC_INTERNAL); 197 cpu = irq / GIC_INTERNAL; 198 irq %= GIC_INTERNAL; 199 cm = 1 << cpu; 200 target = cm; 201 } 202 203 assert(irq >= GIC_NR_SGIS); 204 205 if (level == GIC_DIST_TEST_LEVEL(irq, cm)) { 206 return; 207 } 208 209 if (s->revision == REV_11MPCORE) { 210 gic_set_irq_11mpcore(s, irq, level, cm, target); 211 } else { 212 gic_set_irq_generic(s, irq, level, cm, target); 213 } 214 trace_gic_set_irq(irq, level, cm, target); 215 216 gic_update(s); 217 } 218 219 static uint16_t gic_get_current_pending_irq(GICState *s, int cpu, 220 MemTxAttrs attrs) 221 { 222 uint16_t pending_irq = s->current_pending[cpu]; 223 224 if (pending_irq < GIC_MAXIRQ && gic_has_groups(s)) { 225 int group = gic_test_group(s, pending_irq, cpu); 226 227 /* On a GIC without the security extensions, reading this register 228 * behaves in the same way as a secure access to a GIC with them. 229 */ 230 bool secure = !gic_cpu_ns_access(s, cpu, attrs); 231 232 if (group == 0 && !secure) { 233 /* Group0 interrupts hidden from Non-secure access */ 234 return 1023; 235 } 236 if (group == 1 && secure && !(s->cpu_ctlr[cpu] & GICC_CTLR_ACK_CTL)) { 237 /* Group1 interrupts only seen by Secure access if 238 * AckCtl bit set. 239 */ 240 return 1022; 241 } 242 } 243 return pending_irq; 244 } 245 246 static int gic_get_group_priority(GICState *s, int cpu, int irq) 247 { 248 /* Return the group priority of the specified interrupt 249 * (which is the top bits of its priority, with the number 250 * of bits masked determined by the applicable binary point register). 251 */ 252 int bpr; 253 uint32_t mask; 254 255 if (gic_has_groups(s) && 256 !(s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) && 257 gic_test_group(s, irq, cpu)) { 258 bpr = s->abpr[cpu] - 1; 259 assert(bpr >= 0); 260 } else { 261 bpr = s->bpr[cpu]; 262 } 263 264 /* a BPR of 0 means the group priority bits are [7:1]; 265 * a BPR of 1 means they are [7:2], and so on down to 266 * a BPR of 7 meaning no group priority bits at all. 267 */ 268 mask = ~0U << ((bpr & 7) + 1); 269 270 return gic_get_priority(s, irq, cpu) & mask; 271 } 272 273 static void gic_activate_irq(GICState *s, int cpu, int irq) 274 { 275 /* Set the appropriate Active Priority Register bit for this IRQ, 276 * and update the running priority. 277 */ 278 int prio = gic_get_group_priority(s, cpu, irq); 279 int preemption_level = prio >> (GIC_MIN_BPR + 1); 280 int regno = preemption_level / 32; 281 int bitno = preemption_level % 32; 282 283 if (gic_has_groups(s) && gic_test_group(s, irq, cpu)) { 284 s->nsapr[regno][cpu] |= (1 << bitno); 285 } else { 286 s->apr[regno][cpu] |= (1 << bitno); 287 } 288 289 s->running_priority[cpu] = prio; 290 gic_set_active(s, irq, cpu); 291 } 292 293 static int gic_get_prio_from_apr_bits(GICState *s, int cpu) 294 { 295 /* Recalculate the current running priority for this CPU based 296 * on the set bits in the Active Priority Registers. 297 */ 298 int i; 299 for (i = 0; i < GIC_NR_APRS; i++) { 300 uint32_t apr = s->apr[i][cpu] | s->nsapr[i][cpu]; 301 if (!apr) { 302 continue; 303 } 304 return (i * 32 + ctz32(apr)) << (GIC_MIN_BPR + 1); 305 } 306 return 0x100; 307 } 308 309 static void gic_drop_prio(GICState *s, int cpu, int group) 310 { 311 /* Drop the priority of the currently active interrupt in the 312 * specified group. 313 * 314 * Note that we can guarantee (because of the requirement to nest 315 * GICC_IAR reads [which activate an interrupt and raise priority] 316 * with GICC_EOIR writes [which drop the priority for the interrupt]) 317 * that the interrupt we're being called for is the highest priority 318 * active interrupt, meaning that it has the lowest set bit in the 319 * APR registers. 320 * 321 * If the guest does not honour the ordering constraints then the 322 * behaviour of the GIC is UNPREDICTABLE, which for us means that 323 * the values of the APR registers might become incorrect and the 324 * running priority will be wrong, so interrupts that should preempt 325 * might not do so, and interrupts that should not preempt might do so. 326 */ 327 int i; 328 329 for (i = 0; i < GIC_NR_APRS; i++) { 330 uint32_t *papr = group ? &s->nsapr[i][cpu] : &s->apr[i][cpu]; 331 if (!*papr) { 332 continue; 333 } 334 /* Clear lowest set bit */ 335 *papr &= *papr - 1; 336 break; 337 } 338 339 s->running_priority[cpu] = gic_get_prio_from_apr_bits(s, cpu); 340 } 341 342 uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs) 343 { 344 int ret, irq, src; 345 int cm = 1 << cpu; 346 347 /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately 348 * for the case where this GIC supports grouping and the pending interrupt 349 * is in the wrong group. 350 */ 351 irq = gic_get_current_pending_irq(s, cpu, attrs); 352 trace_gic_acknowledge_irq(cpu, irq); 353 354 if (irq >= GIC_MAXIRQ) { 355 DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq); 356 return irq; 357 } 358 359 if (gic_get_priority(s, irq, cpu) >= s->running_priority[cpu]) { 360 DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq); 361 return 1023; 362 } 363 364 if (s->revision == REV_11MPCORE) { 365 /* Clear pending flags for both level and edge triggered interrupts. 366 * Level triggered IRQs will be reasserted once they become inactive. 367 */ 368 gic_clear_pending(s, irq, cpu); 369 ret = irq; 370 } else { 371 if (irq < GIC_NR_SGIS) { 372 /* Lookup the source CPU for the SGI and clear this in the 373 * sgi_pending map. Return the src and clear the overall pending 374 * state on this CPU if the SGI is not pending from any CPUs. 375 */ 376 assert(s->sgi_pending[irq][cpu] != 0); 377 src = ctz32(s->sgi_pending[irq][cpu]); 378 s->sgi_pending[irq][cpu] &= ~(1 << src); 379 if (s->sgi_pending[irq][cpu] == 0) { 380 gic_clear_pending(s, irq, cpu); 381 } 382 ret = irq | ((src & 0x7) << 10); 383 } else { 384 /* Clear pending state for both level and edge triggered 385 * interrupts. (level triggered interrupts with an active line 386 * remain pending, see gic_test_pending) 387 */ 388 gic_clear_pending(s, irq, cpu); 389 ret = irq; 390 } 391 } 392 393 gic_activate_irq(s, cpu, irq); 394 gic_update(s); 395 DPRINTF("ACK %d\n", irq); 396 return ret; 397 } 398 399 void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val, 400 MemTxAttrs attrs) 401 { 402 if (s->security_extn && !attrs.secure) { 403 if (!GIC_DIST_TEST_GROUP(irq, (1 << cpu))) { 404 return; /* Ignore Non-secure access of Group0 IRQ */ 405 } 406 val = 0x80 | (val >> 1); /* Non-secure view */ 407 } 408 409 if (irq < GIC_INTERNAL) { 410 s->priority1[irq][cpu] = val; 411 } else { 412 s->priority2[(irq) - GIC_INTERNAL] = val; 413 } 414 } 415 416 static uint32_t gic_dist_get_priority(GICState *s, int cpu, int irq, 417 MemTxAttrs attrs) 418 { 419 uint32_t prio = GIC_DIST_GET_PRIORITY(irq, cpu); 420 421 if (s->security_extn && !attrs.secure) { 422 if (!GIC_DIST_TEST_GROUP(irq, (1 << cpu))) { 423 return 0; /* Non-secure access cannot read priority of Group0 IRQ */ 424 } 425 prio = (prio << 1) & 0xff; /* Non-secure view */ 426 } 427 return prio; 428 } 429 430 static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, 431 MemTxAttrs attrs) 432 { 433 if (gic_cpu_ns_access(s, cpu, attrs)) { 434 if (s->priority_mask[cpu] & 0x80) { 435 /* Priority Mask in upper half */ 436 pmask = 0x80 | (pmask >> 1); 437 } else { 438 /* Non-secure write ignored if priority mask is in lower half */ 439 return; 440 } 441 } 442 s->priority_mask[cpu] = pmask; 443 } 444 445 static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs) 446 { 447 uint32_t pmask = s->priority_mask[cpu]; 448 449 if (gic_cpu_ns_access(s, cpu, attrs)) { 450 if (pmask & 0x80) { 451 /* Priority Mask in upper half, return Non-secure view */ 452 pmask = (pmask << 1) & 0xff; 453 } else { 454 /* Priority Mask in lower half, RAZ */ 455 pmask = 0; 456 } 457 } 458 return pmask; 459 } 460 461 static uint32_t gic_get_cpu_control(GICState *s, int cpu, MemTxAttrs attrs) 462 { 463 uint32_t ret = s->cpu_ctlr[cpu]; 464 465 if (gic_cpu_ns_access(s, cpu, attrs)) { 466 /* Construct the NS banked view of GICC_CTLR from the correct 467 * bits of the S banked view. We don't need to move the bypass 468 * control bits because we don't implement that (IMPDEF) part 469 * of the GIC architecture. 470 */ 471 ret = (ret & (GICC_CTLR_EN_GRP1 | GICC_CTLR_EOIMODE_NS)) >> 1; 472 } 473 return ret; 474 } 475 476 static void gic_set_cpu_control(GICState *s, int cpu, uint32_t value, 477 MemTxAttrs attrs) 478 { 479 uint32_t mask; 480 481 if (gic_cpu_ns_access(s, cpu, attrs)) { 482 /* The NS view can only write certain bits in the register; 483 * the rest are unchanged 484 */ 485 mask = GICC_CTLR_EN_GRP1; 486 if (s->revision == 2) { 487 mask |= GICC_CTLR_EOIMODE_NS; 488 } 489 s->cpu_ctlr[cpu] &= ~mask; 490 s->cpu_ctlr[cpu] |= (value << 1) & mask; 491 } else { 492 if (s->revision == 2) { 493 mask = s->security_extn ? GICC_CTLR_V2_S_MASK : GICC_CTLR_V2_MASK; 494 } else { 495 mask = s->security_extn ? GICC_CTLR_V1_S_MASK : GICC_CTLR_V1_MASK; 496 } 497 s->cpu_ctlr[cpu] = value & mask; 498 } 499 DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, " 500 "Group1 Interrupts %sabled\n", cpu, 501 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP0) ? "En" : "Dis", 502 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP1) ? "En" : "Dis"); 503 } 504 505 static uint8_t gic_get_running_priority(GICState *s, int cpu, MemTxAttrs attrs) 506 { 507 if ((s->revision != REV_11MPCORE) && (s->running_priority[cpu] > 0xff)) { 508 /* Idle priority */ 509 return 0xff; 510 } 511 512 if (gic_cpu_ns_access(s, cpu, attrs)) { 513 if (s->running_priority[cpu] & 0x80) { 514 /* Running priority in upper half of range: return the Non-secure 515 * view of the priority. 516 */ 517 return s->running_priority[cpu] << 1; 518 } else { 519 /* Running priority in lower half of range: RAZ */ 520 return 0; 521 } 522 } else { 523 return s->running_priority[cpu]; 524 } 525 } 526 527 /* Return true if we should split priority drop and interrupt deactivation, 528 * ie whether the relevant EOIMode bit is set. 529 */ 530 static bool gic_eoi_split(GICState *s, int cpu, MemTxAttrs attrs) 531 { 532 if (s->revision != 2) { 533 /* Before GICv2 prio-drop and deactivate are not separable */ 534 return false; 535 } 536 if (gic_cpu_ns_access(s, cpu, attrs)) { 537 return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE_NS; 538 } 539 return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE; 540 } 541 542 static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) 543 { 544 int group; 545 546 if (irq >= s->num_irq) { 547 /* 548 * This handles two cases: 549 * 1. If software writes the ID of a spurious interrupt [ie 1023] 550 * to the GICC_DIR, the GIC ignores that write. 551 * 2. If software writes the number of a non-existent interrupt 552 * this must be a subcase of "value written is not an active interrupt" 553 * and so this is UNPREDICTABLE. We choose to ignore it. 554 */ 555 return; 556 } 557 558 group = gic_has_groups(s) && gic_test_group(s, irq, cpu); 559 560 if (!gic_eoi_split(s, cpu, attrs)) { 561 /* This is UNPREDICTABLE; we choose to ignore it */ 562 qemu_log_mask(LOG_GUEST_ERROR, 563 "gic_deactivate_irq: GICC_DIR write when EOIMode clear"); 564 return; 565 } 566 567 if (gic_cpu_ns_access(s, cpu, attrs) && !group) { 568 DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq); 569 return; 570 } 571 572 gic_clear_active(s, irq, cpu); 573 } 574 575 static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) 576 { 577 int cm = 1 << cpu; 578 int group; 579 580 DPRINTF("EOI %d\n", irq); 581 if (irq >= s->num_irq) { 582 /* This handles two cases: 583 * 1. If software writes the ID of a spurious interrupt [ie 1023] 584 * to the GICC_EOIR, the GIC ignores that write. 585 * 2. If software writes the number of a non-existent interrupt 586 * this must be a subcase of "value written does not match the last 587 * valid interrupt value read from the Interrupt Acknowledge 588 * register" and so this is UNPREDICTABLE. We choose to ignore it. 589 */ 590 return; 591 } 592 if (s->running_priority[cpu] == 0x100) { 593 return; /* No active IRQ. */ 594 } 595 596 if (s->revision == REV_11MPCORE) { 597 /* Mark level triggered interrupts as pending if they are still 598 raised. */ 599 if (!GIC_DIST_TEST_EDGE_TRIGGER(irq) && GIC_DIST_TEST_ENABLED(irq, cm) 600 && GIC_DIST_TEST_LEVEL(irq, cm) 601 && (GIC_DIST_TARGET(irq) & cm) != 0) { 602 DPRINTF("Set %d pending mask %x\n", irq, cm); 603 GIC_DIST_SET_PENDING(irq, cm); 604 } 605 } 606 607 group = gic_has_groups(s) && gic_test_group(s, irq, cpu); 608 609 if (gic_cpu_ns_access(s, cpu, attrs) && !group) { 610 DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq); 611 return; 612 } 613 614 /* Secure EOI with GICC_CTLR.AckCtl == 0 when the IRQ is a Group 1 615 * interrupt is UNPREDICTABLE. We choose to handle it as if AckCtl == 1, 616 * i.e. go ahead and complete the irq anyway. 617 */ 618 619 gic_drop_prio(s, cpu, group); 620 621 /* In GICv2 the guest can choose to split priority-drop and deactivate */ 622 if (!gic_eoi_split(s, cpu, attrs)) { 623 gic_clear_active(s, irq, cpu); 624 } 625 gic_update(s); 626 } 627 628 static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) 629 { 630 GICState *s = (GICState *)opaque; 631 uint32_t res; 632 int irq; 633 int i; 634 int cpu; 635 int cm; 636 int mask; 637 638 cpu = gic_get_current_cpu(s); 639 cm = 1 << cpu; 640 if (offset < 0x100) { 641 if (offset == 0) { /* GICD_CTLR */ 642 if (s->security_extn && !attrs.secure) { 643 /* The NS bank of this register is just an alias of the 644 * EnableGrp1 bit in the S bank version. 645 */ 646 return extract32(s->ctlr, 1, 1); 647 } else { 648 return s->ctlr; 649 } 650 } 651 if (offset == 4) 652 /* Interrupt Controller Type Register */ 653 return ((s->num_irq / 32) - 1) 654 | ((s->num_cpu - 1) << 5) 655 | (s->security_extn << 10); 656 if (offset < 0x08) 657 return 0; 658 if (offset >= 0x80) { 659 /* Interrupt Group Registers: these RAZ/WI if this is an NS 660 * access to a GIC with the security extensions, or if the GIC 661 * doesn't have groups at all. 662 */ 663 res = 0; 664 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 665 /* Every byte offset holds 8 group status bits */ 666 irq = (offset - 0x080) * 8 + GIC_BASE_IRQ; 667 if (irq >= s->num_irq) { 668 goto bad_reg; 669 } 670 for (i = 0; i < 8; i++) { 671 if (GIC_DIST_TEST_GROUP(irq + i, cm)) { 672 res |= (1 << i); 673 } 674 } 675 } 676 return res; 677 } 678 goto bad_reg; 679 } else if (offset < 0x200) { 680 /* Interrupt Set/Clear Enable. */ 681 if (offset < 0x180) 682 irq = (offset - 0x100) * 8; 683 else 684 irq = (offset - 0x180) * 8; 685 irq += GIC_BASE_IRQ; 686 if (irq >= s->num_irq) 687 goto bad_reg; 688 res = 0; 689 for (i = 0; i < 8; i++) { 690 if (s->security_extn && !attrs.secure && 691 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 692 continue; /* Ignore Non-secure access of Group0 IRQ */ 693 } 694 695 if (GIC_DIST_TEST_ENABLED(irq + i, cm)) { 696 res |= (1 << i); 697 } 698 } 699 } else if (offset < 0x300) { 700 /* Interrupt Set/Clear Pending. */ 701 if (offset < 0x280) 702 irq = (offset - 0x200) * 8; 703 else 704 irq = (offset - 0x280) * 8; 705 irq += GIC_BASE_IRQ; 706 if (irq >= s->num_irq) 707 goto bad_reg; 708 res = 0; 709 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 710 for (i = 0; i < 8; i++) { 711 if (s->security_extn && !attrs.secure && 712 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 713 continue; /* Ignore Non-secure access of Group0 IRQ */ 714 } 715 716 if (gic_test_pending(s, irq + i, mask)) { 717 res |= (1 << i); 718 } 719 } 720 } else if (offset < 0x400) { 721 /* Interrupt Set/Clear Active. */ 722 if (offset < 0x380) { 723 irq = (offset - 0x300) * 8; 724 } else if (s->revision == 2) { 725 irq = (offset - 0x380) * 8; 726 } else { 727 goto bad_reg; 728 } 729 730 irq += GIC_BASE_IRQ; 731 if (irq >= s->num_irq) 732 goto bad_reg; 733 res = 0; 734 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 735 for (i = 0; i < 8; i++) { 736 if (s->security_extn && !attrs.secure && 737 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 738 continue; /* Ignore Non-secure access of Group0 IRQ */ 739 } 740 741 if (GIC_DIST_TEST_ACTIVE(irq + i, mask)) { 742 res |= (1 << i); 743 } 744 } 745 } else if (offset < 0x800) { 746 /* Interrupt Priority. */ 747 irq = (offset - 0x400) + GIC_BASE_IRQ; 748 if (irq >= s->num_irq) 749 goto bad_reg; 750 res = gic_dist_get_priority(s, cpu, irq, attrs); 751 } else if (offset < 0xc00) { 752 /* Interrupt CPU Target. */ 753 if (s->num_cpu == 1 && s->revision != REV_11MPCORE) { 754 /* For uniprocessor GICs these RAZ/WI */ 755 res = 0; 756 } else { 757 irq = (offset - 0x800) + GIC_BASE_IRQ; 758 if (irq >= s->num_irq) { 759 goto bad_reg; 760 } 761 if (irq < 29 && s->revision == REV_11MPCORE) { 762 res = 0; 763 } else if (irq < GIC_INTERNAL) { 764 res = cm; 765 } else { 766 res = GIC_DIST_TARGET(irq); 767 } 768 } 769 } else if (offset < 0xf00) { 770 /* Interrupt Configuration. */ 771 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 772 if (irq >= s->num_irq) 773 goto bad_reg; 774 res = 0; 775 for (i = 0; i < 4; i++) { 776 if (s->security_extn && !attrs.secure && 777 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 778 continue; /* Ignore Non-secure access of Group0 IRQ */ 779 } 780 781 if (GIC_DIST_TEST_MODEL(irq + i)) { 782 res |= (1 << (i * 2)); 783 } 784 if (GIC_DIST_TEST_EDGE_TRIGGER(irq + i)) { 785 res |= (2 << (i * 2)); 786 } 787 } 788 } else if (offset < 0xf10) { 789 goto bad_reg; 790 } else if (offset < 0xf30) { 791 if (s->revision == REV_11MPCORE) { 792 goto bad_reg; 793 } 794 795 if (offset < 0xf20) { 796 /* GICD_CPENDSGIRn */ 797 irq = (offset - 0xf10); 798 } else { 799 irq = (offset - 0xf20); 800 /* GICD_SPENDSGIRn */ 801 } 802 803 if (s->security_extn && !attrs.secure && 804 !GIC_DIST_TEST_GROUP(irq, 1 << cpu)) { 805 res = 0; /* Ignore Non-secure access of Group0 IRQ */ 806 } else { 807 res = s->sgi_pending[irq][cpu]; 808 } 809 } else if (offset < 0xfd0) { 810 goto bad_reg; 811 } else if (offset < 0x1000) { 812 if (offset & 3) { 813 res = 0; 814 } else { 815 switch (s->revision) { 816 case REV_11MPCORE: 817 res = gic_id_11mpcore[(offset - 0xfd0) >> 2]; 818 break; 819 case 1: 820 res = gic_id_gicv1[(offset - 0xfd0) >> 2]; 821 break; 822 case 2: 823 res = gic_id_gicv2[(offset - 0xfd0) >> 2]; 824 break; 825 default: 826 res = 0; 827 } 828 } 829 } else { 830 g_assert_not_reached(); 831 } 832 return res; 833 bad_reg: 834 qemu_log_mask(LOG_GUEST_ERROR, 835 "gic_dist_readb: Bad offset %x\n", (int)offset); 836 return 0; 837 } 838 839 static MemTxResult gic_dist_read(void *opaque, hwaddr offset, uint64_t *data, 840 unsigned size, MemTxAttrs attrs) 841 { 842 switch (size) { 843 case 1: 844 *data = gic_dist_readb(opaque, offset, attrs); 845 return MEMTX_OK; 846 case 2: 847 *data = gic_dist_readb(opaque, offset, attrs); 848 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 849 return MEMTX_OK; 850 case 4: 851 *data = gic_dist_readb(opaque, offset, attrs); 852 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 853 *data |= gic_dist_readb(opaque, offset + 2, attrs) << 16; 854 *data |= gic_dist_readb(opaque, offset + 3, attrs) << 24; 855 return MEMTX_OK; 856 default: 857 return MEMTX_ERROR; 858 } 859 } 860 861 static void gic_dist_writeb(void *opaque, hwaddr offset, 862 uint32_t value, MemTxAttrs attrs) 863 { 864 GICState *s = (GICState *)opaque; 865 int irq; 866 int i; 867 int cpu; 868 869 cpu = gic_get_current_cpu(s); 870 if (offset < 0x100) { 871 if (offset == 0) { 872 if (s->security_extn && !attrs.secure) { 873 /* NS version is just an alias of the S version's bit 1 */ 874 s->ctlr = deposit32(s->ctlr, 1, 1, value); 875 } else if (gic_has_groups(s)) { 876 s->ctlr = value & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1); 877 } else { 878 s->ctlr = value & GICD_CTLR_EN_GRP0; 879 } 880 DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n", 881 s->ctlr & GICD_CTLR_EN_GRP0 ? "En" : "Dis", 882 s->ctlr & GICD_CTLR_EN_GRP1 ? "En" : "Dis"); 883 } else if (offset < 4) { 884 /* ignored. */ 885 } else if (offset >= 0x80) { 886 /* Interrupt Group Registers: RAZ/WI for NS access to secure 887 * GIC, or for GICs without groups. 888 */ 889 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 890 /* Every byte offset holds 8 group status bits */ 891 irq = (offset - 0x80) * 8 + GIC_BASE_IRQ; 892 if (irq >= s->num_irq) { 893 goto bad_reg; 894 } 895 for (i = 0; i < 8; i++) { 896 /* Group bits are banked for private interrupts */ 897 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 898 if (value & (1 << i)) { 899 /* Group1 (Non-secure) */ 900 GIC_DIST_SET_GROUP(irq + i, cm); 901 } else { 902 /* Group0 (Secure) */ 903 GIC_DIST_CLEAR_GROUP(irq + i, cm); 904 } 905 } 906 } 907 } else { 908 goto bad_reg; 909 } 910 } else if (offset < 0x180) { 911 /* Interrupt Set Enable. */ 912 irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; 913 if (irq >= s->num_irq) 914 goto bad_reg; 915 if (irq < GIC_NR_SGIS) { 916 value = 0xff; 917 } 918 919 for (i = 0; i < 8; i++) { 920 if (value & (1 << i)) { 921 int mask = 922 (irq < GIC_INTERNAL) ? (1 << cpu) 923 : GIC_DIST_TARGET(irq + i); 924 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 925 926 if (s->security_extn && !attrs.secure && 927 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 928 continue; /* Ignore Non-secure access of Group0 IRQ */ 929 } 930 931 if (!GIC_DIST_TEST_ENABLED(irq + i, cm)) { 932 DPRINTF("Enabled IRQ %d\n", irq + i); 933 trace_gic_enable_irq(irq + i); 934 } 935 GIC_DIST_SET_ENABLED(irq + i, cm); 936 /* If a raised level triggered IRQ enabled then mark 937 is as pending. */ 938 if (GIC_DIST_TEST_LEVEL(irq + i, mask) 939 && !GIC_DIST_TEST_EDGE_TRIGGER(irq + i)) { 940 DPRINTF("Set %d pending mask %x\n", irq + i, mask); 941 GIC_DIST_SET_PENDING(irq + i, mask); 942 } 943 } 944 } 945 } else if (offset < 0x200) { 946 /* Interrupt Clear Enable. */ 947 irq = (offset - 0x180) * 8 + GIC_BASE_IRQ; 948 if (irq >= s->num_irq) 949 goto bad_reg; 950 if (irq < GIC_NR_SGIS) { 951 value = 0; 952 } 953 954 for (i = 0; i < 8; i++) { 955 if (value & (1 << i)) { 956 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 957 958 if (s->security_extn && !attrs.secure && 959 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 960 continue; /* Ignore Non-secure access of Group0 IRQ */ 961 } 962 963 if (GIC_DIST_TEST_ENABLED(irq + i, cm)) { 964 DPRINTF("Disabled IRQ %d\n", irq + i); 965 trace_gic_disable_irq(irq + i); 966 } 967 GIC_DIST_CLEAR_ENABLED(irq + i, cm); 968 } 969 } 970 } else if (offset < 0x280) { 971 /* Interrupt Set Pending. */ 972 irq = (offset - 0x200) * 8 + GIC_BASE_IRQ; 973 if (irq >= s->num_irq) 974 goto bad_reg; 975 if (irq < GIC_NR_SGIS) { 976 value = 0; 977 } 978 979 for (i = 0; i < 8; i++) { 980 if (value & (1 << i)) { 981 if (s->security_extn && !attrs.secure && 982 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 983 continue; /* Ignore Non-secure access of Group0 IRQ */ 984 } 985 986 GIC_DIST_SET_PENDING(irq + i, GIC_DIST_TARGET(irq + i)); 987 } 988 } 989 } else if (offset < 0x300) { 990 /* Interrupt Clear Pending. */ 991 irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; 992 if (irq >= s->num_irq) 993 goto bad_reg; 994 if (irq < GIC_NR_SGIS) { 995 value = 0; 996 } 997 998 for (i = 0; i < 8; i++) { 999 if (s->security_extn && !attrs.secure && 1000 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 1001 continue; /* Ignore Non-secure access of Group0 IRQ */ 1002 } 1003 1004 /* ??? This currently clears the pending bit for all CPUs, even 1005 for per-CPU interrupts. It's unclear whether this is the 1006 corect behavior. */ 1007 if (value & (1 << i)) { 1008 GIC_DIST_CLEAR_PENDING(irq + i, ALL_CPU_MASK); 1009 } 1010 } 1011 } else if (offset < 0x380) { 1012 /* Interrupt Set Active. */ 1013 if (s->revision != 2) { 1014 goto bad_reg; 1015 } 1016 1017 irq = (offset - 0x300) * 8 + GIC_BASE_IRQ; 1018 if (irq >= s->num_irq) { 1019 goto bad_reg; 1020 } 1021 1022 /* This register is banked per-cpu for PPIs */ 1023 int cm = irq < GIC_INTERNAL ? (1 << cpu) : ALL_CPU_MASK; 1024 1025 for (i = 0; i < 8; i++) { 1026 if (s->security_extn && !attrs.secure && 1027 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 1028 continue; /* Ignore Non-secure access of Group0 IRQ */ 1029 } 1030 1031 if (value & (1 << i)) { 1032 GIC_DIST_SET_ACTIVE(irq + i, cm); 1033 } 1034 } 1035 } else if (offset < 0x400) { 1036 /* Interrupt Clear Active. */ 1037 if (s->revision != 2) { 1038 goto bad_reg; 1039 } 1040 1041 irq = (offset - 0x380) * 8 + GIC_BASE_IRQ; 1042 if (irq >= s->num_irq) { 1043 goto bad_reg; 1044 } 1045 1046 /* This register is banked per-cpu for PPIs */ 1047 int cm = irq < GIC_INTERNAL ? (1 << cpu) : ALL_CPU_MASK; 1048 1049 for (i = 0; i < 8; i++) { 1050 if (s->security_extn && !attrs.secure && 1051 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 1052 continue; /* Ignore Non-secure access of Group0 IRQ */ 1053 } 1054 1055 if (value & (1 << i)) { 1056 GIC_DIST_CLEAR_ACTIVE(irq + i, cm); 1057 } 1058 } 1059 } else if (offset < 0x800) { 1060 /* Interrupt Priority. */ 1061 irq = (offset - 0x400) + GIC_BASE_IRQ; 1062 if (irq >= s->num_irq) 1063 goto bad_reg; 1064 gic_dist_set_priority(s, cpu, irq, value, attrs); 1065 } else if (offset < 0xc00) { 1066 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the 1067 * annoying exception of the 11MPCore's GIC. 1068 */ 1069 if (s->num_cpu != 1 || s->revision == REV_11MPCORE) { 1070 irq = (offset - 0x800) + GIC_BASE_IRQ; 1071 if (irq >= s->num_irq) { 1072 goto bad_reg; 1073 } 1074 if (irq < 29 && s->revision == REV_11MPCORE) { 1075 value = 0; 1076 } else if (irq < GIC_INTERNAL) { 1077 value = ALL_CPU_MASK; 1078 } 1079 s->irq_target[irq] = value & ALL_CPU_MASK; 1080 } 1081 } else if (offset < 0xf00) { 1082 /* Interrupt Configuration. */ 1083 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 1084 if (irq >= s->num_irq) 1085 goto bad_reg; 1086 if (irq < GIC_NR_SGIS) 1087 value |= 0xaa; 1088 for (i = 0; i < 4; i++) { 1089 if (s->security_extn && !attrs.secure && 1090 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 1091 continue; /* Ignore Non-secure access of Group0 IRQ */ 1092 } 1093 1094 if (s->revision == REV_11MPCORE) { 1095 if (value & (1 << (i * 2))) { 1096 GIC_DIST_SET_MODEL(irq + i); 1097 } else { 1098 GIC_DIST_CLEAR_MODEL(irq + i); 1099 } 1100 } 1101 if (value & (2 << (i * 2))) { 1102 GIC_DIST_SET_EDGE_TRIGGER(irq + i); 1103 } else { 1104 GIC_DIST_CLEAR_EDGE_TRIGGER(irq + i); 1105 } 1106 } 1107 } else if (offset < 0xf10) { 1108 /* 0xf00 is only handled for 32-bit writes. */ 1109 goto bad_reg; 1110 } else if (offset < 0xf20) { 1111 /* GICD_CPENDSGIRn */ 1112 if (s->revision == REV_11MPCORE) { 1113 goto bad_reg; 1114 } 1115 irq = (offset - 0xf10); 1116 1117 if (!s->security_extn || attrs.secure || 1118 GIC_DIST_TEST_GROUP(irq, 1 << cpu)) { 1119 s->sgi_pending[irq][cpu] &= ~value; 1120 if (s->sgi_pending[irq][cpu] == 0) { 1121 GIC_DIST_CLEAR_PENDING(irq, 1 << cpu); 1122 } 1123 } 1124 } else if (offset < 0xf30) { 1125 /* GICD_SPENDSGIRn */ 1126 if (s->revision == REV_11MPCORE) { 1127 goto bad_reg; 1128 } 1129 irq = (offset - 0xf20); 1130 1131 if (!s->security_extn || attrs.secure || 1132 GIC_DIST_TEST_GROUP(irq, 1 << cpu)) { 1133 GIC_DIST_SET_PENDING(irq, 1 << cpu); 1134 s->sgi_pending[irq][cpu] |= value; 1135 } 1136 } else { 1137 goto bad_reg; 1138 } 1139 gic_update(s); 1140 return; 1141 bad_reg: 1142 qemu_log_mask(LOG_GUEST_ERROR, 1143 "gic_dist_writeb: Bad offset %x\n", (int)offset); 1144 } 1145 1146 static void gic_dist_writew(void *opaque, hwaddr offset, 1147 uint32_t value, MemTxAttrs attrs) 1148 { 1149 gic_dist_writeb(opaque, offset, value & 0xff, attrs); 1150 gic_dist_writeb(opaque, offset + 1, value >> 8, attrs); 1151 } 1152 1153 static void gic_dist_writel(void *opaque, hwaddr offset, 1154 uint32_t value, MemTxAttrs attrs) 1155 { 1156 GICState *s = (GICState *)opaque; 1157 if (offset == 0xf00) { 1158 int cpu; 1159 int irq; 1160 int mask; 1161 int target_cpu; 1162 1163 cpu = gic_get_current_cpu(s); 1164 irq = value & 0x3ff; 1165 switch ((value >> 24) & 3) { 1166 case 0: 1167 mask = (value >> 16) & ALL_CPU_MASK; 1168 break; 1169 case 1: 1170 mask = ALL_CPU_MASK ^ (1 << cpu); 1171 break; 1172 case 2: 1173 mask = 1 << cpu; 1174 break; 1175 default: 1176 DPRINTF("Bad Soft Int target filter\n"); 1177 mask = ALL_CPU_MASK; 1178 break; 1179 } 1180 GIC_DIST_SET_PENDING(irq, mask); 1181 target_cpu = ctz32(mask); 1182 while (target_cpu < GIC_NCPU) { 1183 s->sgi_pending[irq][target_cpu] |= (1 << cpu); 1184 mask &= ~(1 << target_cpu); 1185 target_cpu = ctz32(mask); 1186 } 1187 gic_update(s); 1188 return; 1189 } 1190 gic_dist_writew(opaque, offset, value & 0xffff, attrs); 1191 gic_dist_writew(opaque, offset + 2, value >> 16, attrs); 1192 } 1193 1194 static MemTxResult gic_dist_write(void *opaque, hwaddr offset, uint64_t data, 1195 unsigned size, MemTxAttrs attrs) 1196 { 1197 switch (size) { 1198 case 1: 1199 gic_dist_writeb(opaque, offset, data, attrs); 1200 return MEMTX_OK; 1201 case 2: 1202 gic_dist_writew(opaque, offset, data, attrs); 1203 return MEMTX_OK; 1204 case 4: 1205 gic_dist_writel(opaque, offset, data, attrs); 1206 return MEMTX_OK; 1207 default: 1208 return MEMTX_ERROR; 1209 } 1210 } 1211 1212 static inline uint32_t gic_apr_ns_view(GICState *s, int cpu, int regno) 1213 { 1214 /* Return the Nonsecure view of GICC_APR<regno>. This is the 1215 * second half of GICC_NSAPR. 1216 */ 1217 switch (GIC_MIN_BPR) { 1218 case 0: 1219 if (regno < 2) { 1220 return s->nsapr[regno + 2][cpu]; 1221 } 1222 break; 1223 case 1: 1224 if (regno == 0) { 1225 return s->nsapr[regno + 1][cpu]; 1226 } 1227 break; 1228 case 2: 1229 if (regno == 0) { 1230 return extract32(s->nsapr[0][cpu], 16, 16); 1231 } 1232 break; 1233 case 3: 1234 if (regno == 0) { 1235 return extract32(s->nsapr[0][cpu], 8, 8); 1236 } 1237 break; 1238 default: 1239 g_assert_not_reached(); 1240 } 1241 return 0; 1242 } 1243 1244 static inline void gic_apr_write_ns_view(GICState *s, int cpu, int regno, 1245 uint32_t value) 1246 { 1247 /* Write the Nonsecure view of GICC_APR<regno>. */ 1248 switch (GIC_MIN_BPR) { 1249 case 0: 1250 if (regno < 2) { 1251 s->nsapr[regno + 2][cpu] = value; 1252 } 1253 break; 1254 case 1: 1255 if (regno == 0) { 1256 s->nsapr[regno + 1][cpu] = value; 1257 } 1258 break; 1259 case 2: 1260 if (regno == 0) { 1261 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 16, 16, value); 1262 } 1263 break; 1264 case 3: 1265 if (regno == 0) { 1266 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 8, 8, value); 1267 } 1268 break; 1269 default: 1270 g_assert_not_reached(); 1271 } 1272 } 1273 1274 static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset, 1275 uint64_t *data, MemTxAttrs attrs) 1276 { 1277 switch (offset) { 1278 case 0x00: /* Control */ 1279 *data = gic_get_cpu_control(s, cpu, attrs); 1280 break; 1281 case 0x04: /* Priority mask */ 1282 *data = gic_get_priority_mask(s, cpu, attrs); 1283 break; 1284 case 0x08: /* Binary Point */ 1285 if (gic_cpu_ns_access(s, cpu, attrs)) { 1286 if (s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) { 1287 /* NS view of BPR when CBPR is 1 */ 1288 *data = MIN(s->bpr[cpu] + 1, 7); 1289 } else { 1290 /* BPR is banked. Non-secure copy stored in ABPR. */ 1291 *data = s->abpr[cpu]; 1292 } 1293 } else { 1294 *data = s->bpr[cpu]; 1295 } 1296 break; 1297 case 0x0c: /* Acknowledge */ 1298 *data = gic_acknowledge_irq(s, cpu, attrs); 1299 break; 1300 case 0x14: /* Running Priority */ 1301 *data = gic_get_running_priority(s, cpu, attrs); 1302 break; 1303 case 0x18: /* Highest Pending Interrupt */ 1304 *data = gic_get_current_pending_irq(s, cpu, attrs); 1305 break; 1306 case 0x1c: /* Aliased Binary Point */ 1307 /* GIC v2, no security: ABPR 1308 * GIC v1, no security: not implemented (RAZ/WI) 1309 * With security extensions, secure access: ABPR (alias of NS BPR) 1310 * With security extensions, nonsecure access: RAZ/WI 1311 */ 1312 if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) { 1313 *data = 0; 1314 } else { 1315 *data = s->abpr[cpu]; 1316 } 1317 break; 1318 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 1319 { 1320 int regno = (offset - 0xd0) / 4; 1321 1322 if (regno >= GIC_NR_APRS || s->revision != 2) { 1323 *data = 0; 1324 } else if (gic_cpu_ns_access(s, cpu, attrs)) { 1325 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ 1326 *data = gic_apr_ns_view(s, regno, cpu); 1327 } else { 1328 *data = s->apr[regno][cpu]; 1329 } 1330 break; 1331 } 1332 case 0xe0: case 0xe4: case 0xe8: case 0xec: 1333 { 1334 int regno = (offset - 0xe0) / 4; 1335 1336 if (regno >= GIC_NR_APRS || s->revision != 2 || !gic_has_groups(s) || 1337 gic_cpu_ns_access(s, cpu, attrs)) { 1338 *data = 0; 1339 } else { 1340 *data = s->nsapr[regno][cpu]; 1341 } 1342 break; 1343 } 1344 default: 1345 qemu_log_mask(LOG_GUEST_ERROR, 1346 "gic_cpu_read: Bad offset %x\n", (int)offset); 1347 *data = 0; 1348 break; 1349 } 1350 return MEMTX_OK; 1351 } 1352 1353 static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset, 1354 uint32_t value, MemTxAttrs attrs) 1355 { 1356 switch (offset) { 1357 case 0x00: /* Control */ 1358 gic_set_cpu_control(s, cpu, value, attrs); 1359 break; 1360 case 0x04: /* Priority mask */ 1361 gic_set_priority_mask(s, cpu, value, attrs); 1362 break; 1363 case 0x08: /* Binary Point */ 1364 if (gic_cpu_ns_access(s, cpu, attrs)) { 1365 if (s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) { 1366 /* WI when CBPR is 1 */ 1367 return MEMTX_OK; 1368 } else { 1369 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 1370 } 1371 } else { 1372 s->bpr[cpu] = MAX(value & 0x7, GIC_MIN_BPR); 1373 } 1374 break; 1375 case 0x10: /* End Of Interrupt */ 1376 gic_complete_irq(s, cpu, value & 0x3ff, attrs); 1377 return MEMTX_OK; 1378 case 0x1c: /* Aliased Binary Point */ 1379 if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) { 1380 /* unimplemented, or NS access: RAZ/WI */ 1381 return MEMTX_OK; 1382 } else { 1383 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 1384 } 1385 break; 1386 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 1387 { 1388 int regno = (offset - 0xd0) / 4; 1389 1390 if (regno >= GIC_NR_APRS || s->revision != 2) { 1391 return MEMTX_OK; 1392 } 1393 if (gic_cpu_ns_access(s, cpu, attrs)) { 1394 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ 1395 gic_apr_write_ns_view(s, regno, cpu, value); 1396 } else { 1397 s->apr[regno][cpu] = value; 1398 } 1399 break; 1400 } 1401 case 0xe0: case 0xe4: case 0xe8: case 0xec: 1402 { 1403 int regno = (offset - 0xe0) / 4; 1404 1405 if (regno >= GIC_NR_APRS || s->revision != 2) { 1406 return MEMTX_OK; 1407 } 1408 if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) { 1409 return MEMTX_OK; 1410 } 1411 s->nsapr[regno][cpu] = value; 1412 break; 1413 } 1414 case 0x1000: 1415 /* GICC_DIR */ 1416 gic_deactivate_irq(s, cpu, value & 0x3ff, attrs); 1417 break; 1418 default: 1419 qemu_log_mask(LOG_GUEST_ERROR, 1420 "gic_cpu_write: Bad offset %x\n", (int)offset); 1421 return MEMTX_OK; 1422 } 1423 gic_update(s); 1424 return MEMTX_OK; 1425 } 1426 1427 /* Wrappers to read/write the GIC CPU interface for the current CPU */ 1428 static MemTxResult gic_thiscpu_read(void *opaque, hwaddr addr, uint64_t *data, 1429 unsigned size, MemTxAttrs attrs) 1430 { 1431 GICState *s = (GICState *)opaque; 1432 return gic_cpu_read(s, gic_get_current_cpu(s), addr, data, attrs); 1433 } 1434 1435 static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, 1436 uint64_t value, unsigned size, 1437 MemTxAttrs attrs) 1438 { 1439 GICState *s = (GICState *)opaque; 1440 return gic_cpu_write(s, gic_get_current_cpu(s), addr, value, attrs); 1441 } 1442 1443 /* Wrappers to read/write the GIC CPU interface for a specific CPU. 1444 * These just decode the opaque pointer into GICState* + cpu id. 1445 */ 1446 static MemTxResult gic_do_cpu_read(void *opaque, hwaddr addr, uint64_t *data, 1447 unsigned size, MemTxAttrs attrs) 1448 { 1449 GICState **backref = (GICState **)opaque; 1450 GICState *s = *backref; 1451 int id = (backref - s->backref); 1452 return gic_cpu_read(s, id, addr, data, attrs); 1453 } 1454 1455 static MemTxResult gic_do_cpu_write(void *opaque, hwaddr addr, 1456 uint64_t value, unsigned size, 1457 MemTxAttrs attrs) 1458 { 1459 GICState **backref = (GICState **)opaque; 1460 GICState *s = *backref; 1461 int id = (backref - s->backref); 1462 return gic_cpu_write(s, id, addr, value, attrs); 1463 } 1464 1465 static const MemoryRegionOps gic_ops[2] = { 1466 { 1467 .read_with_attrs = gic_dist_read, 1468 .write_with_attrs = gic_dist_write, 1469 .endianness = DEVICE_NATIVE_ENDIAN, 1470 }, 1471 { 1472 .read_with_attrs = gic_thiscpu_read, 1473 .write_with_attrs = gic_thiscpu_write, 1474 .endianness = DEVICE_NATIVE_ENDIAN, 1475 } 1476 }; 1477 1478 static const MemoryRegionOps gic_cpu_ops = { 1479 .read_with_attrs = gic_do_cpu_read, 1480 .write_with_attrs = gic_do_cpu_write, 1481 .endianness = DEVICE_NATIVE_ENDIAN, 1482 }; 1483 1484 static void arm_gic_realize(DeviceState *dev, Error **errp) 1485 { 1486 /* Device instance realize function for the GIC sysbus device */ 1487 int i; 1488 GICState *s = ARM_GIC(dev); 1489 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1490 ARMGICClass *agc = ARM_GIC_GET_CLASS(s); 1491 Error *local_err = NULL; 1492 1493 agc->parent_realize(dev, &local_err); 1494 if (local_err) { 1495 error_propagate(errp, local_err); 1496 return; 1497 } 1498 1499 if (kvm_enabled() && !kvm_arm_supports_user_irq()) { 1500 error_setg(errp, "KVM with user space irqchip only works when the " 1501 "host kernel supports KVM_CAP_ARM_USER_IRQ"); 1502 return; 1503 } 1504 1505 /* This creates distributor and main CPU interface (s->cpuiomem[0]) */ 1506 gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops, NULL); 1507 1508 /* Extra core-specific regions for the CPU interfaces. This is 1509 * necessary for "franken-GIC" implementations, for example on 1510 * Exynos 4. 1511 * NB that the memory region size of 0x100 applies for the 11MPCore 1512 * and also cores following the GIC v1 spec (ie A9). 1513 * GIC v2 defines a larger memory region (0x1000) so this will need 1514 * to be extended when we implement A15. 1515 */ 1516 for (i = 0; i < s->num_cpu; i++) { 1517 s->backref[i] = s; 1518 memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops, 1519 &s->backref[i], "gic_cpu", 0x100); 1520 sysbus_init_mmio(sbd, &s->cpuiomem[i+1]); 1521 } 1522 } 1523 1524 static void arm_gic_class_init(ObjectClass *klass, void *data) 1525 { 1526 DeviceClass *dc = DEVICE_CLASS(klass); 1527 ARMGICClass *agc = ARM_GIC_CLASS(klass); 1528 1529 device_class_set_parent_realize(dc, arm_gic_realize, &agc->parent_realize); 1530 } 1531 1532 static const TypeInfo arm_gic_info = { 1533 .name = TYPE_ARM_GIC, 1534 .parent = TYPE_ARM_GIC_COMMON, 1535 .instance_size = sizeof(GICState), 1536 .class_init = arm_gic_class_init, 1537 .class_size = sizeof(ARMGICClass), 1538 }; 1539 1540 static void arm_gic_register_types(void) 1541 { 1542 type_register_static(&arm_gic_info); 1543 } 1544 1545 type_init(arm_gic_register_types) 1546