1 /* 2 * ARM Generic/Distributed Interrupt Controller 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 /* This file contains implementation code for the RealView EB interrupt 11 * controller, MPCore distributed interrupt controller and ARMv7-M 12 * Nested Vectored Interrupt Controller. 13 * It is compiled in two ways: 14 * (1) as a standalone file to produce a sysbus device which is a GIC 15 * that can be used on the realview board and as one of the builtin 16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc) 17 * (2) by being directly #included into armv7m_nvic.c to produce the 18 * armv7m_nvic device. 19 */ 20 21 #include "hw/sysbus.h" 22 #include "gic_internal.h" 23 #include "qom/cpu.h" 24 25 //#define DEBUG_GIC 26 27 #ifdef DEBUG_GIC 28 #define DPRINTF(fmt, ...) \ 29 do { fprintf(stderr, "arm_gic: " fmt , ## __VA_ARGS__); } while (0) 30 #else 31 #define DPRINTF(fmt, ...) do {} while(0) 32 #endif 33 34 static const uint8_t gic_id[] = { 35 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 36 }; 37 38 #define NUM_CPU(s) ((s)->num_cpu) 39 40 static inline int gic_get_current_cpu(GICState *s) 41 { 42 if (s->num_cpu > 1) { 43 return current_cpu->cpu_index; 44 } 45 return 0; 46 } 47 48 /* Return true if this GIC config has interrupt groups, which is 49 * true if we're a GICv2, or a GICv1 with the security extensions. 50 */ 51 static inline bool gic_has_groups(GICState *s) 52 { 53 return s->revision == 2 || s->security_extn; 54 } 55 56 /* TODO: Many places that call this routine could be optimized. */ 57 /* Update interrupt status after enabled or pending bits have been changed. */ 58 void gic_update(GICState *s) 59 { 60 int best_irq; 61 int best_prio; 62 int irq; 63 int level; 64 int cpu; 65 int cm; 66 67 for (cpu = 0; cpu < NUM_CPU(s); cpu++) { 68 cm = 1 << cpu; 69 s->current_pending[cpu] = 1023; 70 if (!(s->ctlr & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1)) 71 || !(s->cpu_ctlr[cpu] & (GICC_CTLR_EN_GRP0 | GICC_CTLR_EN_GRP1))) { 72 qemu_irq_lower(s->parent_irq[cpu]); 73 return; 74 } 75 best_prio = 0x100; 76 best_irq = 1023; 77 for (irq = 0; irq < s->num_irq; irq++) { 78 if (GIC_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm) && 79 (irq < GIC_INTERNAL || GIC_TARGET(irq) & cm)) { 80 if (GIC_GET_PRIORITY(irq, cpu) < best_prio) { 81 best_prio = GIC_GET_PRIORITY(irq, cpu); 82 best_irq = irq; 83 } 84 } 85 } 86 level = 0; 87 if (best_prio < s->priority_mask[cpu]) { 88 s->current_pending[cpu] = best_irq; 89 if (best_prio < s->running_priority[cpu]) { 90 DPRINTF("Raised pending IRQ %d (cpu %d)\n", best_irq, cpu); 91 level = 1; 92 } 93 } 94 qemu_set_irq(s->parent_irq[cpu], level); 95 } 96 } 97 98 void gic_set_pending_private(GICState *s, int cpu, int irq) 99 { 100 int cm = 1 << cpu; 101 102 if (gic_test_pending(s, irq, cm)) { 103 return; 104 } 105 106 DPRINTF("Set %d pending cpu %d\n", irq, cpu); 107 GIC_SET_PENDING(irq, cm); 108 gic_update(s); 109 } 110 111 static void gic_set_irq_11mpcore(GICState *s, int irq, int level, 112 int cm, int target) 113 { 114 if (level) { 115 GIC_SET_LEVEL(irq, cm); 116 if (GIC_TEST_EDGE_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) { 117 DPRINTF("Set %d pending mask %x\n", irq, target); 118 GIC_SET_PENDING(irq, target); 119 } 120 } else { 121 GIC_CLEAR_LEVEL(irq, cm); 122 } 123 } 124 125 static void gic_set_irq_generic(GICState *s, int irq, int level, 126 int cm, int target) 127 { 128 if (level) { 129 GIC_SET_LEVEL(irq, cm); 130 DPRINTF("Set %d pending mask %x\n", irq, target); 131 if (GIC_TEST_EDGE_TRIGGER(irq)) { 132 GIC_SET_PENDING(irq, target); 133 } 134 } else { 135 GIC_CLEAR_LEVEL(irq, cm); 136 } 137 } 138 139 /* Process a change in an external IRQ input. */ 140 static void gic_set_irq(void *opaque, int irq, int level) 141 { 142 /* Meaning of the 'irq' parameter: 143 * [0..N-1] : external interrupts 144 * [N..N+31] : PPI (internal) interrupts for CPU 0 145 * [N+32..N+63] : PPI (internal interrupts for CPU 1 146 * ... 147 */ 148 GICState *s = (GICState *)opaque; 149 int cm, target; 150 if (irq < (s->num_irq - GIC_INTERNAL)) { 151 /* The first external input line is internal interrupt 32. */ 152 cm = ALL_CPU_MASK; 153 irq += GIC_INTERNAL; 154 target = GIC_TARGET(irq); 155 } else { 156 int cpu; 157 irq -= (s->num_irq - GIC_INTERNAL); 158 cpu = irq / GIC_INTERNAL; 159 irq %= GIC_INTERNAL; 160 cm = 1 << cpu; 161 target = cm; 162 } 163 164 assert(irq >= GIC_NR_SGIS); 165 166 if (level == GIC_TEST_LEVEL(irq, cm)) { 167 return; 168 } 169 170 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 171 gic_set_irq_11mpcore(s, irq, level, cm, target); 172 } else { 173 gic_set_irq_generic(s, irq, level, cm, target); 174 } 175 176 gic_update(s); 177 } 178 179 static void gic_set_running_irq(GICState *s, int cpu, int irq) 180 { 181 s->running_irq[cpu] = irq; 182 if (irq == 1023) { 183 s->running_priority[cpu] = 0x100; 184 } else { 185 s->running_priority[cpu] = GIC_GET_PRIORITY(irq, cpu); 186 } 187 gic_update(s); 188 } 189 190 uint32_t gic_acknowledge_irq(GICState *s, int cpu) 191 { 192 int ret, irq, src; 193 int cm = 1 << cpu; 194 irq = s->current_pending[cpu]; 195 if (irq == 1023 196 || GIC_GET_PRIORITY(irq, cpu) >= s->running_priority[cpu]) { 197 DPRINTF("ACK no pending IRQ\n"); 198 return 1023; 199 } 200 s->last_active[irq][cpu] = s->running_irq[cpu]; 201 202 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 203 /* Clear pending flags for both level and edge triggered interrupts. 204 * Level triggered IRQs will be reasserted once they become inactive. 205 */ 206 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 207 ret = irq; 208 } else { 209 if (irq < GIC_NR_SGIS) { 210 /* Lookup the source CPU for the SGI and clear this in the 211 * sgi_pending map. Return the src and clear the overall pending 212 * state on this CPU if the SGI is not pending from any CPUs. 213 */ 214 assert(s->sgi_pending[irq][cpu] != 0); 215 src = ctz32(s->sgi_pending[irq][cpu]); 216 s->sgi_pending[irq][cpu] &= ~(1 << src); 217 if (s->sgi_pending[irq][cpu] == 0) { 218 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 219 } 220 ret = irq | ((src & 0x7) << 10); 221 } else { 222 /* Clear pending state for both level and edge triggered 223 * interrupts. (level triggered interrupts with an active line 224 * remain pending, see gic_test_pending) 225 */ 226 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 227 ret = irq; 228 } 229 } 230 231 gic_set_running_irq(s, cpu, irq); 232 DPRINTF("ACK %d\n", irq); 233 return ret; 234 } 235 236 void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val, 237 MemTxAttrs attrs) 238 { 239 if (s->security_extn && !attrs.secure) { 240 if (!GIC_TEST_GROUP(irq, (1 << cpu))) { 241 return; /* Ignore Non-secure access of Group0 IRQ */ 242 } 243 val = 0x80 | (val >> 1); /* Non-secure view */ 244 } 245 246 if (irq < GIC_INTERNAL) { 247 s->priority1[irq][cpu] = val; 248 } else { 249 s->priority2[(irq) - GIC_INTERNAL] = val; 250 } 251 } 252 253 static uint32_t gic_get_priority(GICState *s, int cpu, int irq, 254 MemTxAttrs attrs) 255 { 256 uint32_t prio = GIC_GET_PRIORITY(irq, cpu); 257 258 if (s->security_extn && !attrs.secure) { 259 if (!GIC_TEST_GROUP(irq, (1 << cpu))) { 260 return 0; /* Non-secure access cannot read priority of Group0 IRQ */ 261 } 262 prio = (prio << 1) & 0xff; /* Non-secure view */ 263 } 264 return prio; 265 } 266 267 static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, 268 MemTxAttrs attrs) 269 { 270 if (s->security_extn && !attrs.secure) { 271 if (s->priority_mask[cpu] & 0x80) { 272 /* Priority Mask in upper half */ 273 pmask = 0x80 | (pmask >> 1); 274 } else { 275 /* Non-secure write ignored if priority mask is in lower half */ 276 return; 277 } 278 } 279 s->priority_mask[cpu] = pmask; 280 } 281 282 static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs) 283 { 284 uint32_t pmask = s->priority_mask[cpu]; 285 286 if (s->security_extn && !attrs.secure) { 287 if (pmask & 0x80) { 288 /* Priority Mask in upper half, return Non-secure view */ 289 pmask = (pmask << 1) & 0xff; 290 } else { 291 /* Priority Mask in lower half, RAZ */ 292 pmask = 0; 293 } 294 } 295 return pmask; 296 } 297 298 static uint32_t gic_get_cpu_control(GICState *s, int cpu, MemTxAttrs attrs) 299 { 300 uint32_t ret = s->cpu_ctlr[cpu]; 301 302 if (s->security_extn && !attrs.secure) { 303 /* Construct the NS banked view of GICC_CTLR from the correct 304 * bits of the S banked view. We don't need to move the bypass 305 * control bits because we don't implement that (IMPDEF) part 306 * of the GIC architecture. 307 */ 308 ret = (ret & (GICC_CTLR_EN_GRP1 | GICC_CTLR_EOIMODE_NS)) >> 1; 309 } 310 return ret; 311 } 312 313 static void gic_set_cpu_control(GICState *s, int cpu, uint32_t value, 314 MemTxAttrs attrs) 315 { 316 uint32_t mask; 317 318 if (s->security_extn && !attrs.secure) { 319 /* The NS view can only write certain bits in the register; 320 * the rest are unchanged 321 */ 322 mask = GICC_CTLR_EN_GRP1; 323 if (s->revision == 2) { 324 mask |= GICC_CTLR_EOIMODE_NS; 325 } 326 s->cpu_ctlr[cpu] &= ~mask; 327 s->cpu_ctlr[cpu] |= (value << 1) & mask; 328 } else { 329 if (s->revision == 2) { 330 mask = s->security_extn ? GICC_CTLR_V2_S_MASK : GICC_CTLR_V2_MASK; 331 } else { 332 mask = s->security_extn ? GICC_CTLR_V1_S_MASK : GICC_CTLR_V1_MASK; 333 } 334 s->cpu_ctlr[cpu] = value & mask; 335 } 336 DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, " 337 "Group1 Interrupts %sabled\n", cpu, 338 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP0) ? "En" : "Dis", 339 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP1) ? "En" : "Dis"); 340 } 341 342 static uint8_t gic_get_running_priority(GICState *s, int cpu, MemTxAttrs attrs) 343 { 344 if (s->security_extn && !attrs.secure) { 345 if (s->running_priority[cpu] & 0x80) { 346 /* Running priority in upper half of range: return the Non-secure 347 * view of the priority. 348 */ 349 return s->running_priority[cpu] << 1; 350 } else { 351 /* Running priority in lower half of range: RAZ */ 352 return 0; 353 } 354 } else { 355 return s->running_priority[cpu]; 356 } 357 } 358 359 void gic_complete_irq(GICState *s, int cpu, int irq) 360 { 361 int update = 0; 362 int cm = 1 << cpu; 363 DPRINTF("EOI %d\n", irq); 364 if (irq >= s->num_irq) { 365 /* This handles two cases: 366 * 1. If software writes the ID of a spurious interrupt [ie 1023] 367 * to the GICC_EOIR, the GIC ignores that write. 368 * 2. If software writes the number of a non-existent interrupt 369 * this must be a subcase of "value written does not match the last 370 * valid interrupt value read from the Interrupt Acknowledge 371 * register" and so this is UNPREDICTABLE. We choose to ignore it. 372 */ 373 return; 374 } 375 if (s->running_irq[cpu] == 1023) 376 return; /* No active IRQ. */ 377 378 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 379 /* Mark level triggered interrupts as pending if they are still 380 raised. */ 381 if (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm) 382 && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) { 383 DPRINTF("Set %d pending mask %x\n", irq, cm); 384 GIC_SET_PENDING(irq, cm); 385 update = 1; 386 } 387 } 388 389 if (irq != s->running_irq[cpu]) { 390 /* Complete an IRQ that is not currently running. */ 391 int tmp = s->running_irq[cpu]; 392 while (s->last_active[tmp][cpu] != 1023) { 393 if (s->last_active[tmp][cpu] == irq) { 394 s->last_active[tmp][cpu] = s->last_active[irq][cpu]; 395 break; 396 } 397 tmp = s->last_active[tmp][cpu]; 398 } 399 if (update) { 400 gic_update(s); 401 } 402 } else { 403 /* Complete the current running IRQ. */ 404 gic_set_running_irq(s, cpu, s->last_active[s->running_irq[cpu]][cpu]); 405 } 406 } 407 408 static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) 409 { 410 GICState *s = (GICState *)opaque; 411 uint32_t res; 412 int irq; 413 int i; 414 int cpu; 415 int cm; 416 int mask; 417 418 cpu = gic_get_current_cpu(s); 419 cm = 1 << cpu; 420 if (offset < 0x100) { 421 if (offset == 0) { /* GICD_CTLR */ 422 if (s->security_extn && !attrs.secure) { 423 /* The NS bank of this register is just an alias of the 424 * EnableGrp1 bit in the S bank version. 425 */ 426 return extract32(s->ctlr, 1, 1); 427 } else { 428 return s->ctlr; 429 } 430 } 431 if (offset == 4) 432 /* Interrupt Controller Type Register */ 433 return ((s->num_irq / 32) - 1) 434 | ((NUM_CPU(s) - 1) << 5) 435 | (s->security_extn << 10); 436 if (offset < 0x08) 437 return 0; 438 if (offset >= 0x80) { 439 /* Interrupt Group Registers: these RAZ/WI if this is an NS 440 * access to a GIC with the security extensions, or if the GIC 441 * doesn't have groups at all. 442 */ 443 res = 0; 444 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 445 /* Every byte offset holds 8 group status bits */ 446 irq = (offset - 0x080) * 8 + GIC_BASE_IRQ; 447 if (irq >= s->num_irq) { 448 goto bad_reg; 449 } 450 for (i = 0; i < 8; i++) { 451 if (GIC_TEST_GROUP(irq + i, cm)) { 452 res |= (1 << i); 453 } 454 } 455 } 456 return res; 457 } 458 goto bad_reg; 459 } else if (offset < 0x200) { 460 /* Interrupt Set/Clear Enable. */ 461 if (offset < 0x180) 462 irq = (offset - 0x100) * 8; 463 else 464 irq = (offset - 0x180) * 8; 465 irq += GIC_BASE_IRQ; 466 if (irq >= s->num_irq) 467 goto bad_reg; 468 res = 0; 469 for (i = 0; i < 8; i++) { 470 if (GIC_TEST_ENABLED(irq + i, cm)) { 471 res |= (1 << i); 472 } 473 } 474 } else if (offset < 0x300) { 475 /* Interrupt Set/Clear Pending. */ 476 if (offset < 0x280) 477 irq = (offset - 0x200) * 8; 478 else 479 irq = (offset - 0x280) * 8; 480 irq += GIC_BASE_IRQ; 481 if (irq >= s->num_irq) 482 goto bad_reg; 483 res = 0; 484 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 485 for (i = 0; i < 8; i++) { 486 if (gic_test_pending(s, irq + i, mask)) { 487 res |= (1 << i); 488 } 489 } 490 } else if (offset < 0x400) { 491 /* Interrupt Active. */ 492 irq = (offset - 0x300) * 8 + GIC_BASE_IRQ; 493 if (irq >= s->num_irq) 494 goto bad_reg; 495 res = 0; 496 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 497 for (i = 0; i < 8; i++) { 498 if (GIC_TEST_ACTIVE(irq + i, mask)) { 499 res |= (1 << i); 500 } 501 } 502 } else if (offset < 0x800) { 503 /* Interrupt Priority. */ 504 irq = (offset - 0x400) + GIC_BASE_IRQ; 505 if (irq >= s->num_irq) 506 goto bad_reg; 507 res = gic_get_priority(s, cpu, irq, attrs); 508 } else if (offset < 0xc00) { 509 /* Interrupt CPU Target. */ 510 if (s->num_cpu == 1 && s->revision != REV_11MPCORE) { 511 /* For uniprocessor GICs these RAZ/WI */ 512 res = 0; 513 } else { 514 irq = (offset - 0x800) + GIC_BASE_IRQ; 515 if (irq >= s->num_irq) { 516 goto bad_reg; 517 } 518 if (irq >= 29 && irq <= 31) { 519 res = cm; 520 } else { 521 res = GIC_TARGET(irq); 522 } 523 } 524 } else if (offset < 0xf00) { 525 /* Interrupt Configuration. */ 526 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 527 if (irq >= s->num_irq) 528 goto bad_reg; 529 res = 0; 530 for (i = 0; i < 4; i++) { 531 if (GIC_TEST_MODEL(irq + i)) 532 res |= (1 << (i * 2)); 533 if (GIC_TEST_EDGE_TRIGGER(irq + i)) 534 res |= (2 << (i * 2)); 535 } 536 } else if (offset < 0xf10) { 537 goto bad_reg; 538 } else if (offset < 0xf30) { 539 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 540 goto bad_reg; 541 } 542 543 if (offset < 0xf20) { 544 /* GICD_CPENDSGIRn */ 545 irq = (offset - 0xf10); 546 } else { 547 irq = (offset - 0xf20); 548 /* GICD_SPENDSGIRn */ 549 } 550 551 res = s->sgi_pending[irq][cpu]; 552 } else if (offset < 0xfe0) { 553 goto bad_reg; 554 } else /* offset >= 0xfe0 */ { 555 if (offset & 3) { 556 res = 0; 557 } else { 558 res = gic_id[(offset - 0xfe0) >> 2]; 559 } 560 } 561 return res; 562 bad_reg: 563 qemu_log_mask(LOG_GUEST_ERROR, 564 "gic_dist_readb: Bad offset %x\n", (int)offset); 565 return 0; 566 } 567 568 static MemTxResult gic_dist_read(void *opaque, hwaddr offset, uint64_t *data, 569 unsigned size, MemTxAttrs attrs) 570 { 571 switch (size) { 572 case 1: 573 *data = gic_dist_readb(opaque, offset, attrs); 574 return MEMTX_OK; 575 case 2: 576 *data = gic_dist_readb(opaque, offset, attrs); 577 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 578 return MEMTX_OK; 579 case 4: 580 *data = gic_dist_readb(opaque, offset, attrs); 581 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 582 *data |= gic_dist_readb(opaque, offset + 2, attrs) << 16; 583 *data |= gic_dist_readb(opaque, offset + 3, attrs) << 24; 584 return MEMTX_OK; 585 default: 586 return MEMTX_ERROR; 587 } 588 } 589 590 static void gic_dist_writeb(void *opaque, hwaddr offset, 591 uint32_t value, MemTxAttrs attrs) 592 { 593 GICState *s = (GICState *)opaque; 594 int irq; 595 int i; 596 int cpu; 597 598 cpu = gic_get_current_cpu(s); 599 if (offset < 0x100) { 600 if (offset == 0) { 601 if (s->security_extn && !attrs.secure) { 602 /* NS version is just an alias of the S version's bit 1 */ 603 s->ctlr = deposit32(s->ctlr, 1, 1, value); 604 } else if (gic_has_groups(s)) { 605 s->ctlr = value & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1); 606 } else { 607 s->ctlr = value & GICD_CTLR_EN_GRP0; 608 } 609 DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n", 610 s->ctlr & GICD_CTLR_EN_GRP0 ? "En" : "Dis", 611 s->ctlr & GICD_CTLR_EN_GRP1 ? "En" : "Dis"); 612 } else if (offset < 4) { 613 /* ignored. */ 614 } else if (offset >= 0x80) { 615 /* Interrupt Group Registers: RAZ/WI for NS access to secure 616 * GIC, or for GICs without groups. 617 */ 618 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 619 /* Every byte offset holds 8 group status bits */ 620 irq = (offset - 0x80) * 8 + GIC_BASE_IRQ; 621 if (irq >= s->num_irq) { 622 goto bad_reg; 623 } 624 for (i = 0; i < 8; i++) { 625 /* Group bits are banked for private interrupts */ 626 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 627 if (value & (1 << i)) { 628 /* Group1 (Non-secure) */ 629 GIC_SET_GROUP(irq + i, cm); 630 } else { 631 /* Group0 (Secure) */ 632 GIC_CLEAR_GROUP(irq + i, cm); 633 } 634 } 635 } 636 } else { 637 goto bad_reg; 638 } 639 } else if (offset < 0x180) { 640 /* Interrupt Set Enable. */ 641 irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; 642 if (irq >= s->num_irq) 643 goto bad_reg; 644 if (irq < GIC_NR_SGIS) { 645 value = 0xff; 646 } 647 648 for (i = 0; i < 8; i++) { 649 if (value & (1 << i)) { 650 int mask = 651 (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq + i); 652 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 653 654 if (!GIC_TEST_ENABLED(irq + i, cm)) { 655 DPRINTF("Enabled IRQ %d\n", irq + i); 656 } 657 GIC_SET_ENABLED(irq + i, cm); 658 /* If a raised level triggered IRQ enabled then mark 659 is as pending. */ 660 if (GIC_TEST_LEVEL(irq + i, mask) 661 && !GIC_TEST_EDGE_TRIGGER(irq + i)) { 662 DPRINTF("Set %d pending mask %x\n", irq + i, mask); 663 GIC_SET_PENDING(irq + i, mask); 664 } 665 } 666 } 667 } else if (offset < 0x200) { 668 /* Interrupt Clear Enable. */ 669 irq = (offset - 0x180) * 8 + GIC_BASE_IRQ; 670 if (irq >= s->num_irq) 671 goto bad_reg; 672 if (irq < GIC_NR_SGIS) { 673 value = 0; 674 } 675 676 for (i = 0; i < 8; i++) { 677 if (value & (1 << i)) { 678 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 679 680 if (GIC_TEST_ENABLED(irq + i, cm)) { 681 DPRINTF("Disabled IRQ %d\n", irq + i); 682 } 683 GIC_CLEAR_ENABLED(irq + i, cm); 684 } 685 } 686 } else if (offset < 0x280) { 687 /* Interrupt Set Pending. */ 688 irq = (offset - 0x200) * 8 + GIC_BASE_IRQ; 689 if (irq >= s->num_irq) 690 goto bad_reg; 691 if (irq < GIC_NR_SGIS) { 692 value = 0; 693 } 694 695 for (i = 0; i < 8; i++) { 696 if (value & (1 << i)) { 697 GIC_SET_PENDING(irq + i, GIC_TARGET(irq + i)); 698 } 699 } 700 } else if (offset < 0x300) { 701 /* Interrupt Clear Pending. */ 702 irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; 703 if (irq >= s->num_irq) 704 goto bad_reg; 705 if (irq < GIC_NR_SGIS) { 706 value = 0; 707 } 708 709 for (i = 0; i < 8; i++) { 710 /* ??? This currently clears the pending bit for all CPUs, even 711 for per-CPU interrupts. It's unclear whether this is the 712 corect behavior. */ 713 if (value & (1 << i)) { 714 GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK); 715 } 716 } 717 } else if (offset < 0x400) { 718 /* Interrupt Active. */ 719 goto bad_reg; 720 } else if (offset < 0x800) { 721 /* Interrupt Priority. */ 722 irq = (offset - 0x400) + GIC_BASE_IRQ; 723 if (irq >= s->num_irq) 724 goto bad_reg; 725 gic_set_priority(s, cpu, irq, value, attrs); 726 } else if (offset < 0xc00) { 727 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the 728 * annoying exception of the 11MPCore's GIC. 729 */ 730 if (s->num_cpu != 1 || s->revision == REV_11MPCORE) { 731 irq = (offset - 0x800) + GIC_BASE_IRQ; 732 if (irq >= s->num_irq) { 733 goto bad_reg; 734 } 735 if (irq < 29) { 736 value = 0; 737 } else if (irq < GIC_INTERNAL) { 738 value = ALL_CPU_MASK; 739 } 740 s->irq_target[irq] = value & ALL_CPU_MASK; 741 } 742 } else if (offset < 0xf00) { 743 /* Interrupt Configuration. */ 744 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 745 if (irq >= s->num_irq) 746 goto bad_reg; 747 if (irq < GIC_NR_SGIS) 748 value |= 0xaa; 749 for (i = 0; i < 4; i++) { 750 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 751 if (value & (1 << (i * 2))) { 752 GIC_SET_MODEL(irq + i); 753 } else { 754 GIC_CLEAR_MODEL(irq + i); 755 } 756 } 757 if (value & (2 << (i * 2))) { 758 GIC_SET_EDGE_TRIGGER(irq + i); 759 } else { 760 GIC_CLEAR_EDGE_TRIGGER(irq + i); 761 } 762 } 763 } else if (offset < 0xf10) { 764 /* 0xf00 is only handled for 32-bit writes. */ 765 goto bad_reg; 766 } else if (offset < 0xf20) { 767 /* GICD_CPENDSGIRn */ 768 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 769 goto bad_reg; 770 } 771 irq = (offset - 0xf10); 772 773 s->sgi_pending[irq][cpu] &= ~value; 774 if (s->sgi_pending[irq][cpu] == 0) { 775 GIC_CLEAR_PENDING(irq, 1 << cpu); 776 } 777 } else if (offset < 0xf30) { 778 /* GICD_SPENDSGIRn */ 779 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 780 goto bad_reg; 781 } 782 irq = (offset - 0xf20); 783 784 GIC_SET_PENDING(irq, 1 << cpu); 785 s->sgi_pending[irq][cpu] |= value; 786 } else { 787 goto bad_reg; 788 } 789 gic_update(s); 790 return; 791 bad_reg: 792 qemu_log_mask(LOG_GUEST_ERROR, 793 "gic_dist_writeb: Bad offset %x\n", (int)offset); 794 } 795 796 static void gic_dist_writew(void *opaque, hwaddr offset, 797 uint32_t value, MemTxAttrs attrs) 798 { 799 gic_dist_writeb(opaque, offset, value & 0xff, attrs); 800 gic_dist_writeb(opaque, offset + 1, value >> 8, attrs); 801 } 802 803 static void gic_dist_writel(void *opaque, hwaddr offset, 804 uint32_t value, MemTxAttrs attrs) 805 { 806 GICState *s = (GICState *)opaque; 807 if (offset == 0xf00) { 808 int cpu; 809 int irq; 810 int mask; 811 int target_cpu; 812 813 cpu = gic_get_current_cpu(s); 814 irq = value & 0x3ff; 815 switch ((value >> 24) & 3) { 816 case 0: 817 mask = (value >> 16) & ALL_CPU_MASK; 818 break; 819 case 1: 820 mask = ALL_CPU_MASK ^ (1 << cpu); 821 break; 822 case 2: 823 mask = 1 << cpu; 824 break; 825 default: 826 DPRINTF("Bad Soft Int target filter\n"); 827 mask = ALL_CPU_MASK; 828 break; 829 } 830 GIC_SET_PENDING(irq, mask); 831 target_cpu = ctz32(mask); 832 while (target_cpu < GIC_NCPU) { 833 s->sgi_pending[irq][target_cpu] |= (1 << cpu); 834 mask &= ~(1 << target_cpu); 835 target_cpu = ctz32(mask); 836 } 837 gic_update(s); 838 return; 839 } 840 gic_dist_writew(opaque, offset, value & 0xffff, attrs); 841 gic_dist_writew(opaque, offset + 2, value >> 16, attrs); 842 } 843 844 static MemTxResult gic_dist_write(void *opaque, hwaddr offset, uint64_t data, 845 unsigned size, MemTxAttrs attrs) 846 { 847 switch (size) { 848 case 1: 849 gic_dist_writeb(opaque, offset, data, attrs); 850 return MEMTX_OK; 851 case 2: 852 gic_dist_writew(opaque, offset, data, attrs); 853 return MEMTX_OK; 854 case 4: 855 gic_dist_writel(opaque, offset, data, attrs); 856 return MEMTX_OK; 857 default: 858 return MEMTX_ERROR; 859 } 860 } 861 862 static const MemoryRegionOps gic_dist_ops = { 863 .read_with_attrs = gic_dist_read, 864 .write_with_attrs = gic_dist_write, 865 .endianness = DEVICE_NATIVE_ENDIAN, 866 }; 867 868 static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset, 869 uint64_t *data, MemTxAttrs attrs) 870 { 871 switch (offset) { 872 case 0x00: /* Control */ 873 *data = gic_get_cpu_control(s, cpu, attrs); 874 break; 875 case 0x04: /* Priority mask */ 876 *data = gic_get_priority_mask(s, cpu, attrs); 877 break; 878 case 0x08: /* Binary Point */ 879 if (s->security_extn && !attrs.secure) { 880 /* BPR is banked. Non-secure copy stored in ABPR. */ 881 *data = s->abpr[cpu]; 882 } else { 883 *data = s->bpr[cpu]; 884 } 885 break; 886 case 0x0c: /* Acknowledge */ 887 *data = gic_acknowledge_irq(s, cpu); 888 break; 889 case 0x14: /* Running Priority */ 890 *data = gic_get_running_priority(s, cpu, attrs); 891 break; 892 case 0x18: /* Highest Pending Interrupt */ 893 *data = s->current_pending[cpu]; 894 break; 895 case 0x1c: /* Aliased Binary Point */ 896 /* GIC v2, no security: ABPR 897 * GIC v1, no security: not implemented (RAZ/WI) 898 * With security extensions, secure access: ABPR (alias of NS BPR) 899 * With security extensions, nonsecure access: RAZ/WI 900 */ 901 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 902 *data = 0; 903 } else { 904 *data = s->abpr[cpu]; 905 } 906 break; 907 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 908 *data = s->apr[(offset - 0xd0) / 4][cpu]; 909 break; 910 default: 911 qemu_log_mask(LOG_GUEST_ERROR, 912 "gic_cpu_read: Bad offset %x\n", (int)offset); 913 return MEMTX_ERROR; 914 } 915 return MEMTX_OK; 916 } 917 918 static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset, 919 uint32_t value, MemTxAttrs attrs) 920 { 921 switch (offset) { 922 case 0x00: /* Control */ 923 gic_set_cpu_control(s, cpu, value, attrs); 924 break; 925 case 0x04: /* Priority mask */ 926 gic_set_priority_mask(s, cpu, value, attrs); 927 break; 928 case 0x08: /* Binary Point */ 929 if (s->security_extn && !attrs.secure) { 930 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 931 } else { 932 s->bpr[cpu] = MAX(value & 0x7, GIC_MIN_BPR); 933 } 934 break; 935 case 0x10: /* End Of Interrupt */ 936 gic_complete_irq(s, cpu, value & 0x3ff); 937 return MEMTX_OK; 938 case 0x1c: /* Aliased Binary Point */ 939 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 940 /* unimplemented, or NS access: RAZ/WI */ 941 return MEMTX_OK; 942 } else { 943 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 944 } 945 break; 946 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 947 qemu_log_mask(LOG_UNIMP, "Writing APR not implemented\n"); 948 break; 949 default: 950 qemu_log_mask(LOG_GUEST_ERROR, 951 "gic_cpu_write: Bad offset %x\n", (int)offset); 952 return MEMTX_ERROR; 953 } 954 gic_update(s); 955 return MEMTX_OK; 956 } 957 958 /* Wrappers to read/write the GIC CPU interface for the current CPU */ 959 static MemTxResult gic_thiscpu_read(void *opaque, hwaddr addr, uint64_t *data, 960 unsigned size, MemTxAttrs attrs) 961 { 962 GICState *s = (GICState *)opaque; 963 return gic_cpu_read(s, gic_get_current_cpu(s), addr, data, attrs); 964 } 965 966 static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, 967 uint64_t value, unsigned size, 968 MemTxAttrs attrs) 969 { 970 GICState *s = (GICState *)opaque; 971 return gic_cpu_write(s, gic_get_current_cpu(s), addr, value, attrs); 972 } 973 974 /* Wrappers to read/write the GIC CPU interface for a specific CPU. 975 * These just decode the opaque pointer into GICState* + cpu id. 976 */ 977 static MemTxResult gic_do_cpu_read(void *opaque, hwaddr addr, uint64_t *data, 978 unsigned size, MemTxAttrs attrs) 979 { 980 GICState **backref = (GICState **)opaque; 981 GICState *s = *backref; 982 int id = (backref - s->backref); 983 return gic_cpu_read(s, id, addr, data, attrs); 984 } 985 986 static MemTxResult gic_do_cpu_write(void *opaque, hwaddr addr, 987 uint64_t value, unsigned size, 988 MemTxAttrs attrs) 989 { 990 GICState **backref = (GICState **)opaque; 991 GICState *s = *backref; 992 int id = (backref - s->backref); 993 return gic_cpu_write(s, id, addr, value, attrs); 994 } 995 996 static const MemoryRegionOps gic_thiscpu_ops = { 997 .read_with_attrs = gic_thiscpu_read, 998 .write_with_attrs = gic_thiscpu_write, 999 .endianness = DEVICE_NATIVE_ENDIAN, 1000 }; 1001 1002 static const MemoryRegionOps gic_cpu_ops = { 1003 .read_with_attrs = gic_do_cpu_read, 1004 .write_with_attrs = gic_do_cpu_write, 1005 .endianness = DEVICE_NATIVE_ENDIAN, 1006 }; 1007 1008 void gic_init_irqs_and_distributor(GICState *s) 1009 { 1010 SysBusDevice *sbd = SYS_BUS_DEVICE(s); 1011 int i; 1012 1013 i = s->num_irq - GIC_INTERNAL; 1014 /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU. 1015 * GPIO array layout is thus: 1016 * [0..N-1] SPIs 1017 * [N..N+31] PPIs for CPU 0 1018 * [N+32..N+63] PPIs for CPU 1 1019 * ... 1020 */ 1021 if (s->revision != REV_NVIC) { 1022 i += (GIC_INTERNAL * s->num_cpu); 1023 } 1024 qdev_init_gpio_in(DEVICE(s), gic_set_irq, i); 1025 for (i = 0; i < NUM_CPU(s); i++) { 1026 sysbus_init_irq(sbd, &s->parent_irq[i]); 1027 } 1028 for (i = 0; i < NUM_CPU(s); i++) { 1029 sysbus_init_irq(sbd, &s->parent_fiq[i]); 1030 } 1031 memory_region_init_io(&s->iomem, OBJECT(s), &gic_dist_ops, s, 1032 "gic_dist", 0x1000); 1033 } 1034 1035 static void arm_gic_realize(DeviceState *dev, Error **errp) 1036 { 1037 /* Device instance realize function for the GIC sysbus device */ 1038 int i; 1039 GICState *s = ARM_GIC(dev); 1040 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1041 ARMGICClass *agc = ARM_GIC_GET_CLASS(s); 1042 Error *local_err = NULL; 1043 1044 agc->parent_realize(dev, &local_err); 1045 if (local_err) { 1046 error_propagate(errp, local_err); 1047 return; 1048 } 1049 1050 gic_init_irqs_and_distributor(s); 1051 1052 /* Memory regions for the CPU interfaces (NVIC doesn't have these): 1053 * a region for "CPU interface for this core", then a region for 1054 * "CPU interface for core 0", "for core 1", ... 1055 * NB that the memory region size of 0x100 applies for the 11MPCore 1056 * and also cores following the GIC v1 spec (ie A9). 1057 * GIC v2 defines a larger memory region (0x1000) so this will need 1058 * to be extended when we implement A15. 1059 */ 1060 memory_region_init_io(&s->cpuiomem[0], OBJECT(s), &gic_thiscpu_ops, s, 1061 "gic_cpu", 0x100); 1062 for (i = 0; i < NUM_CPU(s); i++) { 1063 s->backref[i] = s; 1064 memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops, 1065 &s->backref[i], "gic_cpu", 0x100); 1066 } 1067 /* Distributor */ 1068 sysbus_init_mmio(sbd, &s->iomem); 1069 /* cpu interfaces (one for "current cpu" plus one per cpu) */ 1070 for (i = 0; i <= NUM_CPU(s); i++) { 1071 sysbus_init_mmio(sbd, &s->cpuiomem[i]); 1072 } 1073 } 1074 1075 static void arm_gic_class_init(ObjectClass *klass, void *data) 1076 { 1077 DeviceClass *dc = DEVICE_CLASS(klass); 1078 ARMGICClass *agc = ARM_GIC_CLASS(klass); 1079 1080 agc->parent_realize = dc->realize; 1081 dc->realize = arm_gic_realize; 1082 } 1083 1084 static const TypeInfo arm_gic_info = { 1085 .name = TYPE_ARM_GIC, 1086 .parent = TYPE_ARM_GIC_COMMON, 1087 .instance_size = sizeof(GICState), 1088 .class_init = arm_gic_class_init, 1089 .class_size = sizeof(ARMGICClass), 1090 }; 1091 1092 static void arm_gic_register_types(void) 1093 { 1094 type_register_static(&arm_gic_info); 1095 } 1096 1097 type_init(arm_gic_register_types) 1098