1 /* 2 * ARM Generic/Distributed Interrupt Controller 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 /* This file contains implementation code for the RealView EB interrupt 11 * controller, MPCore distributed interrupt controller and ARMv7-M 12 * Nested Vectored Interrupt Controller. 13 * It is compiled in two ways: 14 * (1) as a standalone file to produce a sysbus device which is a GIC 15 * that can be used on the realview board and as one of the builtin 16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc) 17 * (2) by being directly #included into armv7m_nvic.c to produce the 18 * armv7m_nvic device. 19 */ 20 21 #include "hw/sysbus.h" 22 #include "gic_internal.h" 23 #include "qom/cpu.h" 24 25 //#define DEBUG_GIC 26 27 #ifdef DEBUG_GIC 28 #define DPRINTF(fmt, ...) \ 29 do { fprintf(stderr, "arm_gic: " fmt , ## __VA_ARGS__); } while (0) 30 #else 31 #define DPRINTF(fmt, ...) do {} while(0) 32 #endif 33 34 static const uint8_t gic_id[] = { 35 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 36 }; 37 38 #define NUM_CPU(s) ((s)->num_cpu) 39 40 static inline int gic_get_current_cpu(GICState *s) 41 { 42 if (s->num_cpu > 1) { 43 return current_cpu->cpu_index; 44 } 45 return 0; 46 } 47 48 /* Return true if this GIC config has interrupt groups, which is 49 * true if we're a GICv2, or a GICv1 with the security extensions. 50 */ 51 static inline bool gic_has_groups(GICState *s) 52 { 53 return s->revision == 2 || s->security_extn; 54 } 55 56 /* TODO: Many places that call this routine could be optimized. */ 57 /* Update interrupt status after enabled or pending bits have been changed. */ 58 void gic_update(GICState *s) 59 { 60 int best_irq; 61 int best_prio; 62 int irq; 63 int level; 64 int cpu; 65 int cm; 66 67 for (cpu = 0; cpu < NUM_CPU(s); cpu++) { 68 cm = 1 << cpu; 69 s->current_pending[cpu] = 1023; 70 if (!(s->ctlr & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1)) 71 || !(s->cpu_ctlr[cpu] & (GICC_CTLR_EN_GRP0 | GICC_CTLR_EN_GRP1))) { 72 qemu_irq_lower(s->parent_irq[cpu]); 73 return; 74 } 75 best_prio = 0x100; 76 best_irq = 1023; 77 for (irq = 0; irq < s->num_irq; irq++) { 78 if (GIC_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm) && 79 (irq < GIC_INTERNAL || GIC_TARGET(irq) & cm)) { 80 if (GIC_GET_PRIORITY(irq, cpu) < best_prio) { 81 best_prio = GIC_GET_PRIORITY(irq, cpu); 82 best_irq = irq; 83 } 84 } 85 } 86 level = 0; 87 if (best_prio < s->priority_mask[cpu]) { 88 s->current_pending[cpu] = best_irq; 89 if (best_prio < s->running_priority[cpu]) { 90 DPRINTF("Raised pending IRQ %d (cpu %d)\n", best_irq, cpu); 91 level = 1; 92 } 93 } 94 qemu_set_irq(s->parent_irq[cpu], level); 95 } 96 } 97 98 void gic_set_pending_private(GICState *s, int cpu, int irq) 99 { 100 int cm = 1 << cpu; 101 102 if (gic_test_pending(s, irq, cm)) { 103 return; 104 } 105 106 DPRINTF("Set %d pending cpu %d\n", irq, cpu); 107 GIC_SET_PENDING(irq, cm); 108 gic_update(s); 109 } 110 111 static void gic_set_irq_11mpcore(GICState *s, int irq, int level, 112 int cm, int target) 113 { 114 if (level) { 115 GIC_SET_LEVEL(irq, cm); 116 if (GIC_TEST_EDGE_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) { 117 DPRINTF("Set %d pending mask %x\n", irq, target); 118 GIC_SET_PENDING(irq, target); 119 } 120 } else { 121 GIC_CLEAR_LEVEL(irq, cm); 122 } 123 } 124 125 static void gic_set_irq_generic(GICState *s, int irq, int level, 126 int cm, int target) 127 { 128 if (level) { 129 GIC_SET_LEVEL(irq, cm); 130 DPRINTF("Set %d pending mask %x\n", irq, target); 131 if (GIC_TEST_EDGE_TRIGGER(irq)) { 132 GIC_SET_PENDING(irq, target); 133 } 134 } else { 135 GIC_CLEAR_LEVEL(irq, cm); 136 } 137 } 138 139 /* Process a change in an external IRQ input. */ 140 static void gic_set_irq(void *opaque, int irq, int level) 141 { 142 /* Meaning of the 'irq' parameter: 143 * [0..N-1] : external interrupts 144 * [N..N+31] : PPI (internal) interrupts for CPU 0 145 * [N+32..N+63] : PPI (internal interrupts for CPU 1 146 * ... 147 */ 148 GICState *s = (GICState *)opaque; 149 int cm, target; 150 if (irq < (s->num_irq - GIC_INTERNAL)) { 151 /* The first external input line is internal interrupt 32. */ 152 cm = ALL_CPU_MASK; 153 irq += GIC_INTERNAL; 154 target = GIC_TARGET(irq); 155 } else { 156 int cpu; 157 irq -= (s->num_irq - GIC_INTERNAL); 158 cpu = irq / GIC_INTERNAL; 159 irq %= GIC_INTERNAL; 160 cm = 1 << cpu; 161 target = cm; 162 } 163 164 assert(irq >= GIC_NR_SGIS); 165 166 if (level == GIC_TEST_LEVEL(irq, cm)) { 167 return; 168 } 169 170 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 171 gic_set_irq_11mpcore(s, irq, level, cm, target); 172 } else { 173 gic_set_irq_generic(s, irq, level, cm, target); 174 } 175 176 gic_update(s); 177 } 178 179 static uint16_t gic_get_current_pending_irq(GICState *s, int cpu, 180 MemTxAttrs attrs) 181 { 182 uint16_t pending_irq = s->current_pending[cpu]; 183 184 if (pending_irq < GIC_MAXIRQ && gic_has_groups(s)) { 185 int group = GIC_TEST_GROUP(pending_irq, (1 << cpu)); 186 /* On a GIC without the security extensions, reading this register 187 * behaves in the same way as a secure access to a GIC with them. 188 */ 189 bool secure = !s->security_extn || attrs.secure; 190 191 if (group == 0 && !secure) { 192 /* Group0 interrupts hidden from Non-secure access */ 193 return 1023; 194 } 195 if (group == 1 && secure && !(s->cpu_ctlr[cpu] & GICC_CTLR_ACK_CTL)) { 196 /* Group1 interrupts only seen by Secure access if 197 * AckCtl bit set. 198 */ 199 return 1022; 200 } 201 } 202 return pending_irq; 203 } 204 205 static void gic_set_running_irq(GICState *s, int cpu, int irq) 206 { 207 s->running_irq[cpu] = irq; 208 if (irq == 1023) { 209 s->running_priority[cpu] = 0x100; 210 } else { 211 s->running_priority[cpu] = GIC_GET_PRIORITY(irq, cpu); 212 } 213 gic_update(s); 214 } 215 216 uint32_t gic_acknowledge_irq(GICState *s, int cpu) 217 { 218 int ret, irq, src; 219 int cm = 1 << cpu; 220 irq = s->current_pending[cpu]; 221 if (irq == 1023 222 || GIC_GET_PRIORITY(irq, cpu) >= s->running_priority[cpu]) { 223 DPRINTF("ACK no pending IRQ\n"); 224 return 1023; 225 } 226 s->last_active[irq][cpu] = s->running_irq[cpu]; 227 228 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 229 /* Clear pending flags for both level and edge triggered interrupts. 230 * Level triggered IRQs will be reasserted once they become inactive. 231 */ 232 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 233 ret = irq; 234 } else { 235 if (irq < GIC_NR_SGIS) { 236 /* Lookup the source CPU for the SGI and clear this in the 237 * sgi_pending map. Return the src and clear the overall pending 238 * state on this CPU if the SGI is not pending from any CPUs. 239 */ 240 assert(s->sgi_pending[irq][cpu] != 0); 241 src = ctz32(s->sgi_pending[irq][cpu]); 242 s->sgi_pending[irq][cpu] &= ~(1 << src); 243 if (s->sgi_pending[irq][cpu] == 0) { 244 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 245 } 246 ret = irq | ((src & 0x7) << 10); 247 } else { 248 /* Clear pending state for both level and edge triggered 249 * interrupts. (level triggered interrupts with an active line 250 * remain pending, see gic_test_pending) 251 */ 252 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 253 ret = irq; 254 } 255 } 256 257 gic_set_running_irq(s, cpu, irq); 258 DPRINTF("ACK %d\n", irq); 259 return ret; 260 } 261 262 void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val, 263 MemTxAttrs attrs) 264 { 265 if (s->security_extn && !attrs.secure) { 266 if (!GIC_TEST_GROUP(irq, (1 << cpu))) { 267 return; /* Ignore Non-secure access of Group0 IRQ */ 268 } 269 val = 0x80 | (val >> 1); /* Non-secure view */ 270 } 271 272 if (irq < GIC_INTERNAL) { 273 s->priority1[irq][cpu] = val; 274 } else { 275 s->priority2[(irq) - GIC_INTERNAL] = val; 276 } 277 } 278 279 static uint32_t gic_get_priority(GICState *s, int cpu, int irq, 280 MemTxAttrs attrs) 281 { 282 uint32_t prio = GIC_GET_PRIORITY(irq, cpu); 283 284 if (s->security_extn && !attrs.secure) { 285 if (!GIC_TEST_GROUP(irq, (1 << cpu))) { 286 return 0; /* Non-secure access cannot read priority of Group0 IRQ */ 287 } 288 prio = (prio << 1) & 0xff; /* Non-secure view */ 289 } 290 return prio; 291 } 292 293 static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, 294 MemTxAttrs attrs) 295 { 296 if (s->security_extn && !attrs.secure) { 297 if (s->priority_mask[cpu] & 0x80) { 298 /* Priority Mask in upper half */ 299 pmask = 0x80 | (pmask >> 1); 300 } else { 301 /* Non-secure write ignored if priority mask is in lower half */ 302 return; 303 } 304 } 305 s->priority_mask[cpu] = pmask; 306 } 307 308 static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs) 309 { 310 uint32_t pmask = s->priority_mask[cpu]; 311 312 if (s->security_extn && !attrs.secure) { 313 if (pmask & 0x80) { 314 /* Priority Mask in upper half, return Non-secure view */ 315 pmask = (pmask << 1) & 0xff; 316 } else { 317 /* Priority Mask in lower half, RAZ */ 318 pmask = 0; 319 } 320 } 321 return pmask; 322 } 323 324 static uint32_t gic_get_cpu_control(GICState *s, int cpu, MemTxAttrs attrs) 325 { 326 uint32_t ret = s->cpu_ctlr[cpu]; 327 328 if (s->security_extn && !attrs.secure) { 329 /* Construct the NS banked view of GICC_CTLR from the correct 330 * bits of the S banked view. We don't need to move the bypass 331 * control bits because we don't implement that (IMPDEF) part 332 * of the GIC architecture. 333 */ 334 ret = (ret & (GICC_CTLR_EN_GRP1 | GICC_CTLR_EOIMODE_NS)) >> 1; 335 } 336 return ret; 337 } 338 339 static void gic_set_cpu_control(GICState *s, int cpu, uint32_t value, 340 MemTxAttrs attrs) 341 { 342 uint32_t mask; 343 344 if (s->security_extn && !attrs.secure) { 345 /* The NS view can only write certain bits in the register; 346 * the rest are unchanged 347 */ 348 mask = GICC_CTLR_EN_GRP1; 349 if (s->revision == 2) { 350 mask |= GICC_CTLR_EOIMODE_NS; 351 } 352 s->cpu_ctlr[cpu] &= ~mask; 353 s->cpu_ctlr[cpu] |= (value << 1) & mask; 354 } else { 355 if (s->revision == 2) { 356 mask = s->security_extn ? GICC_CTLR_V2_S_MASK : GICC_CTLR_V2_MASK; 357 } else { 358 mask = s->security_extn ? GICC_CTLR_V1_S_MASK : GICC_CTLR_V1_MASK; 359 } 360 s->cpu_ctlr[cpu] = value & mask; 361 } 362 DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, " 363 "Group1 Interrupts %sabled\n", cpu, 364 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP0) ? "En" : "Dis", 365 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP1) ? "En" : "Dis"); 366 } 367 368 static uint8_t gic_get_running_priority(GICState *s, int cpu, MemTxAttrs attrs) 369 { 370 if (s->security_extn && !attrs.secure) { 371 if (s->running_priority[cpu] & 0x80) { 372 /* Running priority in upper half of range: return the Non-secure 373 * view of the priority. 374 */ 375 return s->running_priority[cpu] << 1; 376 } else { 377 /* Running priority in lower half of range: RAZ */ 378 return 0; 379 } 380 } else { 381 return s->running_priority[cpu]; 382 } 383 } 384 385 void gic_complete_irq(GICState *s, int cpu, int irq) 386 { 387 int update = 0; 388 int cm = 1 << cpu; 389 DPRINTF("EOI %d\n", irq); 390 if (irq >= s->num_irq) { 391 /* This handles two cases: 392 * 1. If software writes the ID of a spurious interrupt [ie 1023] 393 * to the GICC_EOIR, the GIC ignores that write. 394 * 2. If software writes the number of a non-existent interrupt 395 * this must be a subcase of "value written does not match the last 396 * valid interrupt value read from the Interrupt Acknowledge 397 * register" and so this is UNPREDICTABLE. We choose to ignore it. 398 */ 399 return; 400 } 401 if (s->running_irq[cpu] == 1023) 402 return; /* No active IRQ. */ 403 404 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 405 /* Mark level triggered interrupts as pending if they are still 406 raised. */ 407 if (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm) 408 && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) { 409 DPRINTF("Set %d pending mask %x\n", irq, cm); 410 GIC_SET_PENDING(irq, cm); 411 update = 1; 412 } 413 } 414 415 if (irq != s->running_irq[cpu]) { 416 /* Complete an IRQ that is not currently running. */ 417 int tmp = s->running_irq[cpu]; 418 while (s->last_active[tmp][cpu] != 1023) { 419 if (s->last_active[tmp][cpu] == irq) { 420 s->last_active[tmp][cpu] = s->last_active[irq][cpu]; 421 break; 422 } 423 tmp = s->last_active[tmp][cpu]; 424 } 425 if (update) { 426 gic_update(s); 427 } 428 } else { 429 /* Complete the current running IRQ. */ 430 gic_set_running_irq(s, cpu, s->last_active[s->running_irq[cpu]][cpu]); 431 } 432 } 433 434 static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) 435 { 436 GICState *s = (GICState *)opaque; 437 uint32_t res; 438 int irq; 439 int i; 440 int cpu; 441 int cm; 442 int mask; 443 444 cpu = gic_get_current_cpu(s); 445 cm = 1 << cpu; 446 if (offset < 0x100) { 447 if (offset == 0) { /* GICD_CTLR */ 448 if (s->security_extn && !attrs.secure) { 449 /* The NS bank of this register is just an alias of the 450 * EnableGrp1 bit in the S bank version. 451 */ 452 return extract32(s->ctlr, 1, 1); 453 } else { 454 return s->ctlr; 455 } 456 } 457 if (offset == 4) 458 /* Interrupt Controller Type Register */ 459 return ((s->num_irq / 32) - 1) 460 | ((NUM_CPU(s) - 1) << 5) 461 | (s->security_extn << 10); 462 if (offset < 0x08) 463 return 0; 464 if (offset >= 0x80) { 465 /* Interrupt Group Registers: these RAZ/WI if this is an NS 466 * access to a GIC with the security extensions, or if the GIC 467 * doesn't have groups at all. 468 */ 469 res = 0; 470 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 471 /* Every byte offset holds 8 group status bits */ 472 irq = (offset - 0x080) * 8 + GIC_BASE_IRQ; 473 if (irq >= s->num_irq) { 474 goto bad_reg; 475 } 476 for (i = 0; i < 8; i++) { 477 if (GIC_TEST_GROUP(irq + i, cm)) { 478 res |= (1 << i); 479 } 480 } 481 } 482 return res; 483 } 484 goto bad_reg; 485 } else if (offset < 0x200) { 486 /* Interrupt Set/Clear Enable. */ 487 if (offset < 0x180) 488 irq = (offset - 0x100) * 8; 489 else 490 irq = (offset - 0x180) * 8; 491 irq += GIC_BASE_IRQ; 492 if (irq >= s->num_irq) 493 goto bad_reg; 494 res = 0; 495 for (i = 0; i < 8; i++) { 496 if (GIC_TEST_ENABLED(irq + i, cm)) { 497 res |= (1 << i); 498 } 499 } 500 } else if (offset < 0x300) { 501 /* Interrupt Set/Clear Pending. */ 502 if (offset < 0x280) 503 irq = (offset - 0x200) * 8; 504 else 505 irq = (offset - 0x280) * 8; 506 irq += GIC_BASE_IRQ; 507 if (irq >= s->num_irq) 508 goto bad_reg; 509 res = 0; 510 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 511 for (i = 0; i < 8; i++) { 512 if (gic_test_pending(s, irq + i, mask)) { 513 res |= (1 << i); 514 } 515 } 516 } else if (offset < 0x400) { 517 /* Interrupt Active. */ 518 irq = (offset - 0x300) * 8 + GIC_BASE_IRQ; 519 if (irq >= s->num_irq) 520 goto bad_reg; 521 res = 0; 522 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 523 for (i = 0; i < 8; i++) { 524 if (GIC_TEST_ACTIVE(irq + i, mask)) { 525 res |= (1 << i); 526 } 527 } 528 } else if (offset < 0x800) { 529 /* Interrupt Priority. */ 530 irq = (offset - 0x400) + GIC_BASE_IRQ; 531 if (irq >= s->num_irq) 532 goto bad_reg; 533 res = gic_get_priority(s, cpu, irq, attrs); 534 } else if (offset < 0xc00) { 535 /* Interrupt CPU Target. */ 536 if (s->num_cpu == 1 && s->revision != REV_11MPCORE) { 537 /* For uniprocessor GICs these RAZ/WI */ 538 res = 0; 539 } else { 540 irq = (offset - 0x800) + GIC_BASE_IRQ; 541 if (irq >= s->num_irq) { 542 goto bad_reg; 543 } 544 if (irq >= 29 && irq <= 31) { 545 res = cm; 546 } else { 547 res = GIC_TARGET(irq); 548 } 549 } 550 } else if (offset < 0xf00) { 551 /* Interrupt Configuration. */ 552 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 553 if (irq >= s->num_irq) 554 goto bad_reg; 555 res = 0; 556 for (i = 0; i < 4; i++) { 557 if (GIC_TEST_MODEL(irq + i)) 558 res |= (1 << (i * 2)); 559 if (GIC_TEST_EDGE_TRIGGER(irq + i)) 560 res |= (2 << (i * 2)); 561 } 562 } else if (offset < 0xf10) { 563 goto bad_reg; 564 } else if (offset < 0xf30) { 565 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 566 goto bad_reg; 567 } 568 569 if (offset < 0xf20) { 570 /* GICD_CPENDSGIRn */ 571 irq = (offset - 0xf10); 572 } else { 573 irq = (offset - 0xf20); 574 /* GICD_SPENDSGIRn */ 575 } 576 577 res = s->sgi_pending[irq][cpu]; 578 } else if (offset < 0xfe0) { 579 goto bad_reg; 580 } else /* offset >= 0xfe0 */ { 581 if (offset & 3) { 582 res = 0; 583 } else { 584 res = gic_id[(offset - 0xfe0) >> 2]; 585 } 586 } 587 return res; 588 bad_reg: 589 qemu_log_mask(LOG_GUEST_ERROR, 590 "gic_dist_readb: Bad offset %x\n", (int)offset); 591 return 0; 592 } 593 594 static MemTxResult gic_dist_read(void *opaque, hwaddr offset, uint64_t *data, 595 unsigned size, MemTxAttrs attrs) 596 { 597 switch (size) { 598 case 1: 599 *data = gic_dist_readb(opaque, offset, attrs); 600 return MEMTX_OK; 601 case 2: 602 *data = gic_dist_readb(opaque, offset, attrs); 603 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 604 return MEMTX_OK; 605 case 4: 606 *data = gic_dist_readb(opaque, offset, attrs); 607 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 608 *data |= gic_dist_readb(opaque, offset + 2, attrs) << 16; 609 *data |= gic_dist_readb(opaque, offset + 3, attrs) << 24; 610 return MEMTX_OK; 611 default: 612 return MEMTX_ERROR; 613 } 614 } 615 616 static void gic_dist_writeb(void *opaque, hwaddr offset, 617 uint32_t value, MemTxAttrs attrs) 618 { 619 GICState *s = (GICState *)opaque; 620 int irq; 621 int i; 622 int cpu; 623 624 cpu = gic_get_current_cpu(s); 625 if (offset < 0x100) { 626 if (offset == 0) { 627 if (s->security_extn && !attrs.secure) { 628 /* NS version is just an alias of the S version's bit 1 */ 629 s->ctlr = deposit32(s->ctlr, 1, 1, value); 630 } else if (gic_has_groups(s)) { 631 s->ctlr = value & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1); 632 } else { 633 s->ctlr = value & GICD_CTLR_EN_GRP0; 634 } 635 DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n", 636 s->ctlr & GICD_CTLR_EN_GRP0 ? "En" : "Dis", 637 s->ctlr & GICD_CTLR_EN_GRP1 ? "En" : "Dis"); 638 } else if (offset < 4) { 639 /* ignored. */ 640 } else if (offset >= 0x80) { 641 /* Interrupt Group Registers: RAZ/WI for NS access to secure 642 * GIC, or for GICs without groups. 643 */ 644 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 645 /* Every byte offset holds 8 group status bits */ 646 irq = (offset - 0x80) * 8 + GIC_BASE_IRQ; 647 if (irq >= s->num_irq) { 648 goto bad_reg; 649 } 650 for (i = 0; i < 8; i++) { 651 /* Group bits are banked for private interrupts */ 652 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 653 if (value & (1 << i)) { 654 /* Group1 (Non-secure) */ 655 GIC_SET_GROUP(irq + i, cm); 656 } else { 657 /* Group0 (Secure) */ 658 GIC_CLEAR_GROUP(irq + i, cm); 659 } 660 } 661 } 662 } else { 663 goto bad_reg; 664 } 665 } else if (offset < 0x180) { 666 /* Interrupt Set Enable. */ 667 irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; 668 if (irq >= s->num_irq) 669 goto bad_reg; 670 if (irq < GIC_NR_SGIS) { 671 value = 0xff; 672 } 673 674 for (i = 0; i < 8; i++) { 675 if (value & (1 << i)) { 676 int mask = 677 (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq + i); 678 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 679 680 if (!GIC_TEST_ENABLED(irq + i, cm)) { 681 DPRINTF("Enabled IRQ %d\n", irq + i); 682 } 683 GIC_SET_ENABLED(irq + i, cm); 684 /* If a raised level triggered IRQ enabled then mark 685 is as pending. */ 686 if (GIC_TEST_LEVEL(irq + i, mask) 687 && !GIC_TEST_EDGE_TRIGGER(irq + i)) { 688 DPRINTF("Set %d pending mask %x\n", irq + i, mask); 689 GIC_SET_PENDING(irq + i, mask); 690 } 691 } 692 } 693 } else if (offset < 0x200) { 694 /* Interrupt Clear Enable. */ 695 irq = (offset - 0x180) * 8 + GIC_BASE_IRQ; 696 if (irq >= s->num_irq) 697 goto bad_reg; 698 if (irq < GIC_NR_SGIS) { 699 value = 0; 700 } 701 702 for (i = 0; i < 8; i++) { 703 if (value & (1 << i)) { 704 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 705 706 if (GIC_TEST_ENABLED(irq + i, cm)) { 707 DPRINTF("Disabled IRQ %d\n", irq + i); 708 } 709 GIC_CLEAR_ENABLED(irq + i, cm); 710 } 711 } 712 } else if (offset < 0x280) { 713 /* Interrupt Set Pending. */ 714 irq = (offset - 0x200) * 8 + GIC_BASE_IRQ; 715 if (irq >= s->num_irq) 716 goto bad_reg; 717 if (irq < GIC_NR_SGIS) { 718 value = 0; 719 } 720 721 for (i = 0; i < 8; i++) { 722 if (value & (1 << i)) { 723 GIC_SET_PENDING(irq + i, GIC_TARGET(irq + i)); 724 } 725 } 726 } else if (offset < 0x300) { 727 /* Interrupt Clear Pending. */ 728 irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; 729 if (irq >= s->num_irq) 730 goto bad_reg; 731 if (irq < GIC_NR_SGIS) { 732 value = 0; 733 } 734 735 for (i = 0; i < 8; i++) { 736 /* ??? This currently clears the pending bit for all CPUs, even 737 for per-CPU interrupts. It's unclear whether this is the 738 corect behavior. */ 739 if (value & (1 << i)) { 740 GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK); 741 } 742 } 743 } else if (offset < 0x400) { 744 /* Interrupt Active. */ 745 goto bad_reg; 746 } else if (offset < 0x800) { 747 /* Interrupt Priority. */ 748 irq = (offset - 0x400) + GIC_BASE_IRQ; 749 if (irq >= s->num_irq) 750 goto bad_reg; 751 gic_set_priority(s, cpu, irq, value, attrs); 752 } else if (offset < 0xc00) { 753 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the 754 * annoying exception of the 11MPCore's GIC. 755 */ 756 if (s->num_cpu != 1 || s->revision == REV_11MPCORE) { 757 irq = (offset - 0x800) + GIC_BASE_IRQ; 758 if (irq >= s->num_irq) { 759 goto bad_reg; 760 } 761 if (irq < 29) { 762 value = 0; 763 } else if (irq < GIC_INTERNAL) { 764 value = ALL_CPU_MASK; 765 } 766 s->irq_target[irq] = value & ALL_CPU_MASK; 767 } 768 } else if (offset < 0xf00) { 769 /* Interrupt Configuration. */ 770 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 771 if (irq >= s->num_irq) 772 goto bad_reg; 773 if (irq < GIC_NR_SGIS) 774 value |= 0xaa; 775 for (i = 0; i < 4; i++) { 776 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 777 if (value & (1 << (i * 2))) { 778 GIC_SET_MODEL(irq + i); 779 } else { 780 GIC_CLEAR_MODEL(irq + i); 781 } 782 } 783 if (value & (2 << (i * 2))) { 784 GIC_SET_EDGE_TRIGGER(irq + i); 785 } else { 786 GIC_CLEAR_EDGE_TRIGGER(irq + i); 787 } 788 } 789 } else if (offset < 0xf10) { 790 /* 0xf00 is only handled for 32-bit writes. */ 791 goto bad_reg; 792 } else if (offset < 0xf20) { 793 /* GICD_CPENDSGIRn */ 794 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 795 goto bad_reg; 796 } 797 irq = (offset - 0xf10); 798 799 s->sgi_pending[irq][cpu] &= ~value; 800 if (s->sgi_pending[irq][cpu] == 0) { 801 GIC_CLEAR_PENDING(irq, 1 << cpu); 802 } 803 } else if (offset < 0xf30) { 804 /* GICD_SPENDSGIRn */ 805 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 806 goto bad_reg; 807 } 808 irq = (offset - 0xf20); 809 810 GIC_SET_PENDING(irq, 1 << cpu); 811 s->sgi_pending[irq][cpu] |= value; 812 } else { 813 goto bad_reg; 814 } 815 gic_update(s); 816 return; 817 bad_reg: 818 qemu_log_mask(LOG_GUEST_ERROR, 819 "gic_dist_writeb: Bad offset %x\n", (int)offset); 820 } 821 822 static void gic_dist_writew(void *opaque, hwaddr offset, 823 uint32_t value, MemTxAttrs attrs) 824 { 825 gic_dist_writeb(opaque, offset, value & 0xff, attrs); 826 gic_dist_writeb(opaque, offset + 1, value >> 8, attrs); 827 } 828 829 static void gic_dist_writel(void *opaque, hwaddr offset, 830 uint32_t value, MemTxAttrs attrs) 831 { 832 GICState *s = (GICState *)opaque; 833 if (offset == 0xf00) { 834 int cpu; 835 int irq; 836 int mask; 837 int target_cpu; 838 839 cpu = gic_get_current_cpu(s); 840 irq = value & 0x3ff; 841 switch ((value >> 24) & 3) { 842 case 0: 843 mask = (value >> 16) & ALL_CPU_MASK; 844 break; 845 case 1: 846 mask = ALL_CPU_MASK ^ (1 << cpu); 847 break; 848 case 2: 849 mask = 1 << cpu; 850 break; 851 default: 852 DPRINTF("Bad Soft Int target filter\n"); 853 mask = ALL_CPU_MASK; 854 break; 855 } 856 GIC_SET_PENDING(irq, mask); 857 target_cpu = ctz32(mask); 858 while (target_cpu < GIC_NCPU) { 859 s->sgi_pending[irq][target_cpu] |= (1 << cpu); 860 mask &= ~(1 << target_cpu); 861 target_cpu = ctz32(mask); 862 } 863 gic_update(s); 864 return; 865 } 866 gic_dist_writew(opaque, offset, value & 0xffff, attrs); 867 gic_dist_writew(opaque, offset + 2, value >> 16, attrs); 868 } 869 870 static MemTxResult gic_dist_write(void *opaque, hwaddr offset, uint64_t data, 871 unsigned size, MemTxAttrs attrs) 872 { 873 switch (size) { 874 case 1: 875 gic_dist_writeb(opaque, offset, data, attrs); 876 return MEMTX_OK; 877 case 2: 878 gic_dist_writew(opaque, offset, data, attrs); 879 return MEMTX_OK; 880 case 4: 881 gic_dist_writel(opaque, offset, data, attrs); 882 return MEMTX_OK; 883 default: 884 return MEMTX_ERROR; 885 } 886 } 887 888 static const MemoryRegionOps gic_dist_ops = { 889 .read_with_attrs = gic_dist_read, 890 .write_with_attrs = gic_dist_write, 891 .endianness = DEVICE_NATIVE_ENDIAN, 892 }; 893 894 static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset, 895 uint64_t *data, MemTxAttrs attrs) 896 { 897 switch (offset) { 898 case 0x00: /* Control */ 899 *data = gic_get_cpu_control(s, cpu, attrs); 900 break; 901 case 0x04: /* Priority mask */ 902 *data = gic_get_priority_mask(s, cpu, attrs); 903 break; 904 case 0x08: /* Binary Point */ 905 if (s->security_extn && !attrs.secure) { 906 /* BPR is banked. Non-secure copy stored in ABPR. */ 907 *data = s->abpr[cpu]; 908 } else { 909 *data = s->bpr[cpu]; 910 } 911 break; 912 case 0x0c: /* Acknowledge */ 913 *data = gic_acknowledge_irq(s, cpu); 914 break; 915 case 0x14: /* Running Priority */ 916 *data = gic_get_running_priority(s, cpu, attrs); 917 break; 918 case 0x18: /* Highest Pending Interrupt */ 919 *data = gic_get_current_pending_irq(s, cpu, attrs); 920 break; 921 case 0x1c: /* Aliased Binary Point */ 922 /* GIC v2, no security: ABPR 923 * GIC v1, no security: not implemented (RAZ/WI) 924 * With security extensions, secure access: ABPR (alias of NS BPR) 925 * With security extensions, nonsecure access: RAZ/WI 926 */ 927 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 928 *data = 0; 929 } else { 930 *data = s->abpr[cpu]; 931 } 932 break; 933 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 934 *data = s->apr[(offset - 0xd0) / 4][cpu]; 935 break; 936 default: 937 qemu_log_mask(LOG_GUEST_ERROR, 938 "gic_cpu_read: Bad offset %x\n", (int)offset); 939 return MEMTX_ERROR; 940 } 941 return MEMTX_OK; 942 } 943 944 static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset, 945 uint32_t value, MemTxAttrs attrs) 946 { 947 switch (offset) { 948 case 0x00: /* Control */ 949 gic_set_cpu_control(s, cpu, value, attrs); 950 break; 951 case 0x04: /* Priority mask */ 952 gic_set_priority_mask(s, cpu, value, attrs); 953 break; 954 case 0x08: /* Binary Point */ 955 if (s->security_extn && !attrs.secure) { 956 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 957 } else { 958 s->bpr[cpu] = MAX(value & 0x7, GIC_MIN_BPR); 959 } 960 break; 961 case 0x10: /* End Of Interrupt */ 962 gic_complete_irq(s, cpu, value & 0x3ff); 963 return MEMTX_OK; 964 case 0x1c: /* Aliased Binary Point */ 965 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 966 /* unimplemented, or NS access: RAZ/WI */ 967 return MEMTX_OK; 968 } else { 969 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 970 } 971 break; 972 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 973 qemu_log_mask(LOG_UNIMP, "Writing APR not implemented\n"); 974 break; 975 default: 976 qemu_log_mask(LOG_GUEST_ERROR, 977 "gic_cpu_write: Bad offset %x\n", (int)offset); 978 return MEMTX_ERROR; 979 } 980 gic_update(s); 981 return MEMTX_OK; 982 } 983 984 /* Wrappers to read/write the GIC CPU interface for the current CPU */ 985 static MemTxResult gic_thiscpu_read(void *opaque, hwaddr addr, uint64_t *data, 986 unsigned size, MemTxAttrs attrs) 987 { 988 GICState *s = (GICState *)opaque; 989 return gic_cpu_read(s, gic_get_current_cpu(s), addr, data, attrs); 990 } 991 992 static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, 993 uint64_t value, unsigned size, 994 MemTxAttrs attrs) 995 { 996 GICState *s = (GICState *)opaque; 997 return gic_cpu_write(s, gic_get_current_cpu(s), addr, value, attrs); 998 } 999 1000 /* Wrappers to read/write the GIC CPU interface for a specific CPU. 1001 * These just decode the opaque pointer into GICState* + cpu id. 1002 */ 1003 static MemTxResult gic_do_cpu_read(void *opaque, hwaddr addr, uint64_t *data, 1004 unsigned size, MemTxAttrs attrs) 1005 { 1006 GICState **backref = (GICState **)opaque; 1007 GICState *s = *backref; 1008 int id = (backref - s->backref); 1009 return gic_cpu_read(s, id, addr, data, attrs); 1010 } 1011 1012 static MemTxResult gic_do_cpu_write(void *opaque, hwaddr addr, 1013 uint64_t value, unsigned size, 1014 MemTxAttrs attrs) 1015 { 1016 GICState **backref = (GICState **)opaque; 1017 GICState *s = *backref; 1018 int id = (backref - s->backref); 1019 return gic_cpu_write(s, id, addr, value, attrs); 1020 } 1021 1022 static const MemoryRegionOps gic_thiscpu_ops = { 1023 .read_with_attrs = gic_thiscpu_read, 1024 .write_with_attrs = gic_thiscpu_write, 1025 .endianness = DEVICE_NATIVE_ENDIAN, 1026 }; 1027 1028 static const MemoryRegionOps gic_cpu_ops = { 1029 .read_with_attrs = gic_do_cpu_read, 1030 .write_with_attrs = gic_do_cpu_write, 1031 .endianness = DEVICE_NATIVE_ENDIAN, 1032 }; 1033 1034 void gic_init_irqs_and_distributor(GICState *s) 1035 { 1036 SysBusDevice *sbd = SYS_BUS_DEVICE(s); 1037 int i; 1038 1039 i = s->num_irq - GIC_INTERNAL; 1040 /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU. 1041 * GPIO array layout is thus: 1042 * [0..N-1] SPIs 1043 * [N..N+31] PPIs for CPU 0 1044 * [N+32..N+63] PPIs for CPU 1 1045 * ... 1046 */ 1047 if (s->revision != REV_NVIC) { 1048 i += (GIC_INTERNAL * s->num_cpu); 1049 } 1050 qdev_init_gpio_in(DEVICE(s), gic_set_irq, i); 1051 for (i = 0; i < NUM_CPU(s); i++) { 1052 sysbus_init_irq(sbd, &s->parent_irq[i]); 1053 } 1054 for (i = 0; i < NUM_CPU(s); i++) { 1055 sysbus_init_irq(sbd, &s->parent_fiq[i]); 1056 } 1057 memory_region_init_io(&s->iomem, OBJECT(s), &gic_dist_ops, s, 1058 "gic_dist", 0x1000); 1059 } 1060 1061 static void arm_gic_realize(DeviceState *dev, Error **errp) 1062 { 1063 /* Device instance realize function for the GIC sysbus device */ 1064 int i; 1065 GICState *s = ARM_GIC(dev); 1066 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1067 ARMGICClass *agc = ARM_GIC_GET_CLASS(s); 1068 Error *local_err = NULL; 1069 1070 agc->parent_realize(dev, &local_err); 1071 if (local_err) { 1072 error_propagate(errp, local_err); 1073 return; 1074 } 1075 1076 gic_init_irqs_and_distributor(s); 1077 1078 /* Memory regions for the CPU interfaces (NVIC doesn't have these): 1079 * a region for "CPU interface for this core", then a region for 1080 * "CPU interface for core 0", "for core 1", ... 1081 * NB that the memory region size of 0x100 applies for the 11MPCore 1082 * and also cores following the GIC v1 spec (ie A9). 1083 * GIC v2 defines a larger memory region (0x1000) so this will need 1084 * to be extended when we implement A15. 1085 */ 1086 memory_region_init_io(&s->cpuiomem[0], OBJECT(s), &gic_thiscpu_ops, s, 1087 "gic_cpu", 0x100); 1088 for (i = 0; i < NUM_CPU(s); i++) { 1089 s->backref[i] = s; 1090 memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops, 1091 &s->backref[i], "gic_cpu", 0x100); 1092 } 1093 /* Distributor */ 1094 sysbus_init_mmio(sbd, &s->iomem); 1095 /* cpu interfaces (one for "current cpu" plus one per cpu) */ 1096 for (i = 0; i <= NUM_CPU(s); i++) { 1097 sysbus_init_mmio(sbd, &s->cpuiomem[i]); 1098 } 1099 } 1100 1101 static void arm_gic_class_init(ObjectClass *klass, void *data) 1102 { 1103 DeviceClass *dc = DEVICE_CLASS(klass); 1104 ARMGICClass *agc = ARM_GIC_CLASS(klass); 1105 1106 agc->parent_realize = dc->realize; 1107 dc->realize = arm_gic_realize; 1108 } 1109 1110 static const TypeInfo arm_gic_info = { 1111 .name = TYPE_ARM_GIC, 1112 .parent = TYPE_ARM_GIC_COMMON, 1113 .instance_size = sizeof(GICState), 1114 .class_init = arm_gic_class_init, 1115 .class_size = sizeof(ARMGICClass), 1116 }; 1117 1118 static void arm_gic_register_types(void) 1119 { 1120 type_register_static(&arm_gic_info); 1121 } 1122 1123 type_init(arm_gic_register_types) 1124