1 /* 2 * ARM Generic/Distributed Interrupt Controller 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 /* This file contains implementation code for the RealView EB interrupt 11 * controller, MPCore distributed interrupt controller and ARMv7-M 12 * Nested Vectored Interrupt Controller. 13 * It is compiled in two ways: 14 * (1) as a standalone file to produce a sysbus device which is a GIC 15 * that can be used on the realview board and as one of the builtin 16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc) 17 * (2) by being directly #included into armv7m_nvic.c to produce the 18 * armv7m_nvic device. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/sysbus.h" 23 #include "gic_internal.h" 24 #include "qapi/error.h" 25 #include "qom/cpu.h" 26 #include "qemu/log.h" 27 #include "trace.h" 28 #include "sysemu/kvm.h" 29 30 /* #define DEBUG_GIC */ 31 32 #ifdef DEBUG_GIC 33 #define DEBUG_GIC_GATE 1 34 #else 35 #define DEBUG_GIC_GATE 0 36 #endif 37 38 #define DPRINTF(fmt, ...) do { \ 39 if (DEBUG_GIC_GATE) { \ 40 fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \ 41 } \ 42 } while (0) 43 44 static const uint8_t gic_id_11mpcore[] = { 45 0x00, 0x00, 0x00, 0x00, 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 46 }; 47 48 static const uint8_t gic_id_gicv1[] = { 49 0x04, 0x00, 0x00, 0x00, 0x90, 0xb3, 0x1b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 50 }; 51 52 static const uint8_t gic_id_gicv2[] = { 53 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 54 }; 55 56 static inline int gic_get_current_cpu(GICState *s) 57 { 58 if (s->num_cpu > 1) { 59 return current_cpu->cpu_index; 60 } 61 return 0; 62 } 63 64 /* Return true if this GIC config has interrupt groups, which is 65 * true if we're a GICv2, or a GICv1 with the security extensions. 66 */ 67 static inline bool gic_has_groups(GICState *s) 68 { 69 return s->revision == 2 || s->security_extn; 70 } 71 72 /* TODO: Many places that call this routine could be optimized. */ 73 /* Update interrupt status after enabled or pending bits have been changed. */ 74 void gic_update(GICState *s) 75 { 76 int best_irq; 77 int best_prio; 78 int irq; 79 int irq_level, fiq_level; 80 int cpu; 81 int cm; 82 83 for (cpu = 0; cpu < s->num_cpu; cpu++) { 84 cm = 1 << cpu; 85 s->current_pending[cpu] = 1023; 86 if (!(s->ctlr & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1)) 87 || !(s->cpu_ctlr[cpu] & (GICC_CTLR_EN_GRP0 | GICC_CTLR_EN_GRP1))) { 88 qemu_irq_lower(s->parent_irq[cpu]); 89 qemu_irq_lower(s->parent_fiq[cpu]); 90 continue; 91 } 92 best_prio = 0x100; 93 best_irq = 1023; 94 for (irq = 0; irq < s->num_irq; irq++) { 95 if (GIC_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm) && 96 (!GIC_TEST_ACTIVE(irq, cm)) && 97 (irq < GIC_INTERNAL || GIC_TARGET(irq) & cm)) { 98 if (GIC_GET_PRIORITY(irq, cpu) < best_prio) { 99 best_prio = GIC_GET_PRIORITY(irq, cpu); 100 best_irq = irq; 101 } 102 } 103 } 104 105 if (best_irq != 1023) { 106 trace_gic_update_bestirq(cpu, best_irq, best_prio, 107 s->priority_mask[cpu], s->running_priority[cpu]); 108 } 109 110 irq_level = fiq_level = 0; 111 112 if (best_prio < s->priority_mask[cpu]) { 113 s->current_pending[cpu] = best_irq; 114 if (best_prio < s->running_priority[cpu]) { 115 int group = GIC_TEST_GROUP(best_irq, cm); 116 117 if (extract32(s->ctlr, group, 1) && 118 extract32(s->cpu_ctlr[cpu], group, 1)) { 119 if (group == 0 && s->cpu_ctlr[cpu] & GICC_CTLR_FIQ_EN) { 120 DPRINTF("Raised pending FIQ %d (cpu %d)\n", 121 best_irq, cpu); 122 fiq_level = 1; 123 trace_gic_update_set_irq(cpu, "fiq", fiq_level); 124 } else { 125 DPRINTF("Raised pending IRQ %d (cpu %d)\n", 126 best_irq, cpu); 127 irq_level = 1; 128 trace_gic_update_set_irq(cpu, "irq", irq_level); 129 } 130 } 131 } 132 } 133 134 qemu_set_irq(s->parent_irq[cpu], irq_level); 135 qemu_set_irq(s->parent_fiq[cpu], fiq_level); 136 } 137 } 138 139 void gic_set_pending_private(GICState *s, int cpu, int irq) 140 { 141 int cm = 1 << cpu; 142 143 if (gic_test_pending(s, irq, cm)) { 144 return; 145 } 146 147 DPRINTF("Set %d pending cpu %d\n", irq, cpu); 148 GIC_SET_PENDING(irq, cm); 149 gic_update(s); 150 } 151 152 static void gic_set_irq_11mpcore(GICState *s, int irq, int level, 153 int cm, int target) 154 { 155 if (level) { 156 GIC_SET_LEVEL(irq, cm); 157 if (GIC_TEST_EDGE_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) { 158 DPRINTF("Set %d pending mask %x\n", irq, target); 159 GIC_SET_PENDING(irq, target); 160 } 161 } else { 162 GIC_CLEAR_LEVEL(irq, cm); 163 } 164 } 165 166 static void gic_set_irq_generic(GICState *s, int irq, int level, 167 int cm, int target) 168 { 169 if (level) { 170 GIC_SET_LEVEL(irq, cm); 171 DPRINTF("Set %d pending mask %x\n", irq, target); 172 if (GIC_TEST_EDGE_TRIGGER(irq)) { 173 GIC_SET_PENDING(irq, target); 174 } 175 } else { 176 GIC_CLEAR_LEVEL(irq, cm); 177 } 178 } 179 180 /* Process a change in an external IRQ input. */ 181 static void gic_set_irq(void *opaque, int irq, int level) 182 { 183 /* Meaning of the 'irq' parameter: 184 * [0..N-1] : external interrupts 185 * [N..N+31] : PPI (internal) interrupts for CPU 0 186 * [N+32..N+63] : PPI (internal interrupts for CPU 1 187 * ... 188 */ 189 GICState *s = (GICState *)opaque; 190 int cm, target; 191 if (irq < (s->num_irq - GIC_INTERNAL)) { 192 /* The first external input line is internal interrupt 32. */ 193 cm = ALL_CPU_MASK; 194 irq += GIC_INTERNAL; 195 target = GIC_TARGET(irq); 196 } else { 197 int cpu; 198 irq -= (s->num_irq - GIC_INTERNAL); 199 cpu = irq / GIC_INTERNAL; 200 irq %= GIC_INTERNAL; 201 cm = 1 << cpu; 202 target = cm; 203 } 204 205 assert(irq >= GIC_NR_SGIS); 206 207 if (level == GIC_TEST_LEVEL(irq, cm)) { 208 return; 209 } 210 211 if (s->revision == REV_11MPCORE) { 212 gic_set_irq_11mpcore(s, irq, level, cm, target); 213 } else { 214 gic_set_irq_generic(s, irq, level, cm, target); 215 } 216 trace_gic_set_irq(irq, level, cm, target); 217 218 gic_update(s); 219 } 220 221 static uint16_t gic_get_current_pending_irq(GICState *s, int cpu, 222 MemTxAttrs attrs) 223 { 224 uint16_t pending_irq = s->current_pending[cpu]; 225 226 if (pending_irq < GIC_MAXIRQ && gic_has_groups(s)) { 227 int group = GIC_TEST_GROUP(pending_irq, (1 << cpu)); 228 /* On a GIC without the security extensions, reading this register 229 * behaves in the same way as a secure access to a GIC with them. 230 */ 231 bool secure = !s->security_extn || attrs.secure; 232 233 if (group == 0 && !secure) { 234 /* Group0 interrupts hidden from Non-secure access */ 235 return 1023; 236 } 237 if (group == 1 && secure && !(s->cpu_ctlr[cpu] & GICC_CTLR_ACK_CTL)) { 238 /* Group1 interrupts only seen by Secure access if 239 * AckCtl bit set. 240 */ 241 return 1022; 242 } 243 } 244 return pending_irq; 245 } 246 247 static int gic_get_group_priority(GICState *s, int cpu, int irq) 248 { 249 /* Return the group priority of the specified interrupt 250 * (which is the top bits of its priority, with the number 251 * of bits masked determined by the applicable binary point register). 252 */ 253 int bpr; 254 uint32_t mask; 255 256 if (gic_has_groups(s) && 257 !(s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) && 258 GIC_TEST_GROUP(irq, (1 << cpu))) { 259 bpr = s->abpr[cpu]; 260 } else { 261 bpr = s->bpr[cpu]; 262 } 263 264 /* a BPR of 0 means the group priority bits are [7:1]; 265 * a BPR of 1 means they are [7:2], and so on down to 266 * a BPR of 7 meaning no group priority bits at all. 267 */ 268 mask = ~0U << ((bpr & 7) + 1); 269 270 return GIC_GET_PRIORITY(irq, cpu) & mask; 271 } 272 273 static void gic_activate_irq(GICState *s, int cpu, int irq) 274 { 275 /* Set the appropriate Active Priority Register bit for this IRQ, 276 * and update the running priority. 277 */ 278 int prio = gic_get_group_priority(s, cpu, irq); 279 int preemption_level = prio >> (GIC_MIN_BPR + 1); 280 int regno = preemption_level / 32; 281 int bitno = preemption_level % 32; 282 283 if (gic_has_groups(s) && GIC_TEST_GROUP(irq, (1 << cpu))) { 284 s->nsapr[regno][cpu] |= (1 << bitno); 285 } else { 286 s->apr[regno][cpu] |= (1 << bitno); 287 } 288 289 s->running_priority[cpu] = prio; 290 GIC_SET_ACTIVE(irq, 1 << cpu); 291 } 292 293 static int gic_get_prio_from_apr_bits(GICState *s, int cpu) 294 { 295 /* Recalculate the current running priority for this CPU based 296 * on the set bits in the Active Priority Registers. 297 */ 298 int i; 299 for (i = 0; i < GIC_NR_APRS; i++) { 300 uint32_t apr = s->apr[i][cpu] | s->nsapr[i][cpu]; 301 if (!apr) { 302 continue; 303 } 304 return (i * 32 + ctz32(apr)) << (GIC_MIN_BPR + 1); 305 } 306 return 0x100; 307 } 308 309 static void gic_drop_prio(GICState *s, int cpu, int group) 310 { 311 /* Drop the priority of the currently active interrupt in the 312 * specified group. 313 * 314 * Note that we can guarantee (because of the requirement to nest 315 * GICC_IAR reads [which activate an interrupt and raise priority] 316 * with GICC_EOIR writes [which drop the priority for the interrupt]) 317 * that the interrupt we're being called for is the highest priority 318 * active interrupt, meaning that it has the lowest set bit in the 319 * APR registers. 320 * 321 * If the guest does not honour the ordering constraints then the 322 * behaviour of the GIC is UNPREDICTABLE, which for us means that 323 * the values of the APR registers might become incorrect and the 324 * running priority will be wrong, so interrupts that should preempt 325 * might not do so, and interrupts that should not preempt might do so. 326 */ 327 int i; 328 329 for (i = 0; i < GIC_NR_APRS; i++) { 330 uint32_t *papr = group ? &s->nsapr[i][cpu] : &s->apr[i][cpu]; 331 if (!*papr) { 332 continue; 333 } 334 /* Clear lowest set bit */ 335 *papr &= *papr - 1; 336 break; 337 } 338 339 s->running_priority[cpu] = gic_get_prio_from_apr_bits(s, cpu); 340 } 341 342 uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs) 343 { 344 int ret, irq, src; 345 int cm = 1 << cpu; 346 347 /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately 348 * for the case where this GIC supports grouping and the pending interrupt 349 * is in the wrong group. 350 */ 351 irq = gic_get_current_pending_irq(s, cpu, attrs); 352 trace_gic_acknowledge_irq(cpu, irq); 353 354 if (irq >= GIC_MAXIRQ) { 355 DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq); 356 return irq; 357 } 358 359 if (GIC_GET_PRIORITY(irq, cpu) >= s->running_priority[cpu]) { 360 DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq); 361 return 1023; 362 } 363 364 if (s->revision == REV_11MPCORE) { 365 /* Clear pending flags for both level and edge triggered interrupts. 366 * Level triggered IRQs will be reasserted once they become inactive. 367 */ 368 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 369 ret = irq; 370 } else { 371 if (irq < GIC_NR_SGIS) { 372 /* Lookup the source CPU for the SGI and clear this in the 373 * sgi_pending map. Return the src and clear the overall pending 374 * state on this CPU if the SGI is not pending from any CPUs. 375 */ 376 assert(s->sgi_pending[irq][cpu] != 0); 377 src = ctz32(s->sgi_pending[irq][cpu]); 378 s->sgi_pending[irq][cpu] &= ~(1 << src); 379 if (s->sgi_pending[irq][cpu] == 0) { 380 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 381 } 382 ret = irq | ((src & 0x7) << 10); 383 } else { 384 /* Clear pending state for both level and edge triggered 385 * interrupts. (level triggered interrupts with an active line 386 * remain pending, see gic_test_pending) 387 */ 388 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 389 ret = irq; 390 } 391 } 392 393 gic_activate_irq(s, cpu, irq); 394 gic_update(s); 395 DPRINTF("ACK %d\n", irq); 396 return ret; 397 } 398 399 void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val, 400 MemTxAttrs attrs) 401 { 402 if (s->security_extn && !attrs.secure) { 403 if (!GIC_TEST_GROUP(irq, (1 << cpu))) { 404 return; /* Ignore Non-secure access of Group0 IRQ */ 405 } 406 val = 0x80 | (val >> 1); /* Non-secure view */ 407 } 408 409 if (irq < GIC_INTERNAL) { 410 s->priority1[irq][cpu] = val; 411 } else { 412 s->priority2[(irq) - GIC_INTERNAL] = val; 413 } 414 } 415 416 static uint32_t gic_get_priority(GICState *s, int cpu, int irq, 417 MemTxAttrs attrs) 418 { 419 uint32_t prio = GIC_GET_PRIORITY(irq, cpu); 420 421 if (s->security_extn && !attrs.secure) { 422 if (!GIC_TEST_GROUP(irq, (1 << cpu))) { 423 return 0; /* Non-secure access cannot read priority of Group0 IRQ */ 424 } 425 prio = (prio << 1) & 0xff; /* Non-secure view */ 426 } 427 return prio; 428 } 429 430 static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, 431 MemTxAttrs attrs) 432 { 433 if (s->security_extn && !attrs.secure) { 434 if (s->priority_mask[cpu] & 0x80) { 435 /* Priority Mask in upper half */ 436 pmask = 0x80 | (pmask >> 1); 437 } else { 438 /* Non-secure write ignored if priority mask is in lower half */ 439 return; 440 } 441 } 442 s->priority_mask[cpu] = pmask; 443 } 444 445 static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs) 446 { 447 uint32_t pmask = s->priority_mask[cpu]; 448 449 if (s->security_extn && !attrs.secure) { 450 if (pmask & 0x80) { 451 /* Priority Mask in upper half, return Non-secure view */ 452 pmask = (pmask << 1) & 0xff; 453 } else { 454 /* Priority Mask in lower half, RAZ */ 455 pmask = 0; 456 } 457 } 458 return pmask; 459 } 460 461 static uint32_t gic_get_cpu_control(GICState *s, int cpu, MemTxAttrs attrs) 462 { 463 uint32_t ret = s->cpu_ctlr[cpu]; 464 465 if (s->security_extn && !attrs.secure) { 466 /* Construct the NS banked view of GICC_CTLR from the correct 467 * bits of the S banked view. We don't need to move the bypass 468 * control bits because we don't implement that (IMPDEF) part 469 * of the GIC architecture. 470 */ 471 ret = (ret & (GICC_CTLR_EN_GRP1 | GICC_CTLR_EOIMODE_NS)) >> 1; 472 } 473 return ret; 474 } 475 476 static void gic_set_cpu_control(GICState *s, int cpu, uint32_t value, 477 MemTxAttrs attrs) 478 { 479 uint32_t mask; 480 481 if (s->security_extn && !attrs.secure) { 482 /* The NS view can only write certain bits in the register; 483 * the rest are unchanged 484 */ 485 mask = GICC_CTLR_EN_GRP1; 486 if (s->revision == 2) { 487 mask |= GICC_CTLR_EOIMODE_NS; 488 } 489 s->cpu_ctlr[cpu] &= ~mask; 490 s->cpu_ctlr[cpu] |= (value << 1) & mask; 491 } else { 492 if (s->revision == 2) { 493 mask = s->security_extn ? GICC_CTLR_V2_S_MASK : GICC_CTLR_V2_MASK; 494 } else { 495 mask = s->security_extn ? GICC_CTLR_V1_S_MASK : GICC_CTLR_V1_MASK; 496 } 497 s->cpu_ctlr[cpu] = value & mask; 498 } 499 DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, " 500 "Group1 Interrupts %sabled\n", cpu, 501 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP0) ? "En" : "Dis", 502 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP1) ? "En" : "Dis"); 503 } 504 505 static uint8_t gic_get_running_priority(GICState *s, int cpu, MemTxAttrs attrs) 506 { 507 if ((s->revision != REV_11MPCORE) && (s->running_priority[cpu] > 0xff)) { 508 /* Idle priority */ 509 return 0xff; 510 } 511 512 if (s->security_extn && !attrs.secure) { 513 if (s->running_priority[cpu] & 0x80) { 514 /* Running priority in upper half of range: return the Non-secure 515 * view of the priority. 516 */ 517 return s->running_priority[cpu] << 1; 518 } else { 519 /* Running priority in lower half of range: RAZ */ 520 return 0; 521 } 522 } else { 523 return s->running_priority[cpu]; 524 } 525 } 526 527 /* Return true if we should split priority drop and interrupt deactivation, 528 * ie whether the relevant EOIMode bit is set. 529 */ 530 static bool gic_eoi_split(GICState *s, int cpu, MemTxAttrs attrs) 531 { 532 if (s->revision != 2) { 533 /* Before GICv2 prio-drop and deactivate are not separable */ 534 return false; 535 } 536 if (s->security_extn && !attrs.secure) { 537 return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE_NS; 538 } 539 return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE; 540 } 541 542 static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) 543 { 544 int cm = 1 << cpu; 545 int group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm); 546 547 if (!gic_eoi_split(s, cpu, attrs)) { 548 /* This is UNPREDICTABLE; we choose to ignore it */ 549 qemu_log_mask(LOG_GUEST_ERROR, 550 "gic_deactivate_irq: GICC_DIR write when EOIMode clear"); 551 return; 552 } 553 554 if (s->security_extn && !attrs.secure && !group) { 555 DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq); 556 return; 557 } 558 559 GIC_CLEAR_ACTIVE(irq, cm); 560 } 561 562 void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) 563 { 564 int cm = 1 << cpu; 565 int group; 566 567 DPRINTF("EOI %d\n", irq); 568 if (irq >= s->num_irq) { 569 /* This handles two cases: 570 * 1. If software writes the ID of a spurious interrupt [ie 1023] 571 * to the GICC_EOIR, the GIC ignores that write. 572 * 2. If software writes the number of a non-existent interrupt 573 * this must be a subcase of "value written does not match the last 574 * valid interrupt value read from the Interrupt Acknowledge 575 * register" and so this is UNPREDICTABLE. We choose to ignore it. 576 */ 577 return; 578 } 579 if (s->running_priority[cpu] == 0x100) { 580 return; /* No active IRQ. */ 581 } 582 583 if (s->revision == REV_11MPCORE) { 584 /* Mark level triggered interrupts as pending if they are still 585 raised. */ 586 if (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm) 587 && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) { 588 DPRINTF("Set %d pending mask %x\n", irq, cm); 589 GIC_SET_PENDING(irq, cm); 590 } 591 } 592 593 group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm); 594 595 if (s->security_extn && !attrs.secure && !group) { 596 DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq); 597 return; 598 } 599 600 /* Secure EOI with GICC_CTLR.AckCtl == 0 when the IRQ is a Group 1 601 * interrupt is UNPREDICTABLE. We choose to handle it as if AckCtl == 1, 602 * i.e. go ahead and complete the irq anyway. 603 */ 604 605 gic_drop_prio(s, cpu, group); 606 607 /* In GICv2 the guest can choose to split priority-drop and deactivate */ 608 if (!gic_eoi_split(s, cpu, attrs)) { 609 GIC_CLEAR_ACTIVE(irq, cm); 610 } 611 gic_update(s); 612 } 613 614 static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) 615 { 616 GICState *s = (GICState *)opaque; 617 uint32_t res; 618 int irq; 619 int i; 620 int cpu; 621 int cm; 622 int mask; 623 624 cpu = gic_get_current_cpu(s); 625 cm = 1 << cpu; 626 if (offset < 0x100) { 627 if (offset == 0) { /* GICD_CTLR */ 628 if (s->security_extn && !attrs.secure) { 629 /* The NS bank of this register is just an alias of the 630 * EnableGrp1 bit in the S bank version. 631 */ 632 return extract32(s->ctlr, 1, 1); 633 } else { 634 return s->ctlr; 635 } 636 } 637 if (offset == 4) 638 /* Interrupt Controller Type Register */ 639 return ((s->num_irq / 32) - 1) 640 | ((s->num_cpu - 1) << 5) 641 | (s->security_extn << 10); 642 if (offset < 0x08) 643 return 0; 644 if (offset >= 0x80) { 645 /* Interrupt Group Registers: these RAZ/WI if this is an NS 646 * access to a GIC with the security extensions, or if the GIC 647 * doesn't have groups at all. 648 */ 649 res = 0; 650 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 651 /* Every byte offset holds 8 group status bits */ 652 irq = (offset - 0x080) * 8 + GIC_BASE_IRQ; 653 if (irq >= s->num_irq) { 654 goto bad_reg; 655 } 656 for (i = 0; i < 8; i++) { 657 if (GIC_TEST_GROUP(irq + i, cm)) { 658 res |= (1 << i); 659 } 660 } 661 } 662 return res; 663 } 664 goto bad_reg; 665 } else if (offset < 0x200) { 666 /* Interrupt Set/Clear Enable. */ 667 if (offset < 0x180) 668 irq = (offset - 0x100) * 8; 669 else 670 irq = (offset - 0x180) * 8; 671 irq += GIC_BASE_IRQ; 672 if (irq >= s->num_irq) 673 goto bad_reg; 674 res = 0; 675 for (i = 0; i < 8; i++) { 676 if (s->security_extn && !attrs.secure && 677 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 678 continue; /* Ignore Non-secure access of Group0 IRQ */ 679 } 680 681 if (GIC_TEST_ENABLED(irq + i, cm)) { 682 res |= (1 << i); 683 } 684 } 685 } else if (offset < 0x300) { 686 /* Interrupt Set/Clear Pending. */ 687 if (offset < 0x280) 688 irq = (offset - 0x200) * 8; 689 else 690 irq = (offset - 0x280) * 8; 691 irq += GIC_BASE_IRQ; 692 if (irq >= s->num_irq) 693 goto bad_reg; 694 res = 0; 695 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 696 for (i = 0; i < 8; i++) { 697 if (s->security_extn && !attrs.secure && 698 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 699 continue; /* Ignore Non-secure access of Group0 IRQ */ 700 } 701 702 if (gic_test_pending(s, irq + i, mask)) { 703 res |= (1 << i); 704 } 705 } 706 } else if (offset < 0x400) { 707 /* Interrupt Active. */ 708 irq = (offset - 0x300) * 8 + GIC_BASE_IRQ; 709 if (irq >= s->num_irq) 710 goto bad_reg; 711 res = 0; 712 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 713 for (i = 0; i < 8; i++) { 714 if (s->security_extn && !attrs.secure && 715 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 716 continue; /* Ignore Non-secure access of Group0 IRQ */ 717 } 718 719 if (GIC_TEST_ACTIVE(irq + i, mask)) { 720 res |= (1 << i); 721 } 722 } 723 } else if (offset < 0x800) { 724 /* Interrupt Priority. */ 725 irq = (offset - 0x400) + GIC_BASE_IRQ; 726 if (irq >= s->num_irq) 727 goto bad_reg; 728 res = gic_get_priority(s, cpu, irq, attrs); 729 } else if (offset < 0xc00) { 730 /* Interrupt CPU Target. */ 731 if (s->num_cpu == 1 && s->revision != REV_11MPCORE) { 732 /* For uniprocessor GICs these RAZ/WI */ 733 res = 0; 734 } else { 735 irq = (offset - 0x800) + GIC_BASE_IRQ; 736 if (irq >= s->num_irq) { 737 goto bad_reg; 738 } 739 if (irq >= 29 && irq <= 31) { 740 res = cm; 741 } else { 742 res = GIC_TARGET(irq); 743 } 744 } 745 } else if (offset < 0xf00) { 746 /* Interrupt Configuration. */ 747 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 748 if (irq >= s->num_irq) 749 goto bad_reg; 750 res = 0; 751 for (i = 0; i < 4; i++) { 752 if (s->security_extn && !attrs.secure && 753 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 754 continue; /* Ignore Non-secure access of Group0 IRQ */ 755 } 756 757 if (GIC_TEST_MODEL(irq + i)) 758 res |= (1 << (i * 2)); 759 if (GIC_TEST_EDGE_TRIGGER(irq + i)) 760 res |= (2 << (i * 2)); 761 } 762 } else if (offset < 0xf10) { 763 goto bad_reg; 764 } else if (offset < 0xf30) { 765 if (s->revision == REV_11MPCORE) { 766 goto bad_reg; 767 } 768 769 if (offset < 0xf20) { 770 /* GICD_CPENDSGIRn */ 771 irq = (offset - 0xf10); 772 } else { 773 irq = (offset - 0xf20); 774 /* GICD_SPENDSGIRn */ 775 } 776 777 if (s->security_extn && !attrs.secure && 778 !GIC_TEST_GROUP(irq, 1 << cpu)) { 779 res = 0; /* Ignore Non-secure access of Group0 IRQ */ 780 } else { 781 res = s->sgi_pending[irq][cpu]; 782 } 783 } else if (offset < 0xfd0) { 784 goto bad_reg; 785 } else if (offset < 0x1000) { 786 if (offset & 3) { 787 res = 0; 788 } else { 789 switch (s->revision) { 790 case REV_11MPCORE: 791 res = gic_id_11mpcore[(offset - 0xfd0) >> 2]; 792 break; 793 case 1: 794 res = gic_id_gicv1[(offset - 0xfd0) >> 2]; 795 break; 796 case 2: 797 res = gic_id_gicv2[(offset - 0xfd0) >> 2]; 798 break; 799 default: 800 res = 0; 801 } 802 } 803 } else { 804 g_assert_not_reached(); 805 } 806 return res; 807 bad_reg: 808 qemu_log_mask(LOG_GUEST_ERROR, 809 "gic_dist_readb: Bad offset %x\n", (int)offset); 810 return 0; 811 } 812 813 static MemTxResult gic_dist_read(void *opaque, hwaddr offset, uint64_t *data, 814 unsigned size, MemTxAttrs attrs) 815 { 816 switch (size) { 817 case 1: 818 *data = gic_dist_readb(opaque, offset, attrs); 819 return MEMTX_OK; 820 case 2: 821 *data = gic_dist_readb(opaque, offset, attrs); 822 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 823 return MEMTX_OK; 824 case 4: 825 *data = gic_dist_readb(opaque, offset, attrs); 826 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 827 *data |= gic_dist_readb(opaque, offset + 2, attrs) << 16; 828 *data |= gic_dist_readb(opaque, offset + 3, attrs) << 24; 829 return MEMTX_OK; 830 default: 831 return MEMTX_ERROR; 832 } 833 } 834 835 static void gic_dist_writeb(void *opaque, hwaddr offset, 836 uint32_t value, MemTxAttrs attrs) 837 { 838 GICState *s = (GICState *)opaque; 839 int irq; 840 int i; 841 int cpu; 842 843 cpu = gic_get_current_cpu(s); 844 if (offset < 0x100) { 845 if (offset == 0) { 846 if (s->security_extn && !attrs.secure) { 847 /* NS version is just an alias of the S version's bit 1 */ 848 s->ctlr = deposit32(s->ctlr, 1, 1, value); 849 } else if (gic_has_groups(s)) { 850 s->ctlr = value & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1); 851 } else { 852 s->ctlr = value & GICD_CTLR_EN_GRP0; 853 } 854 DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n", 855 s->ctlr & GICD_CTLR_EN_GRP0 ? "En" : "Dis", 856 s->ctlr & GICD_CTLR_EN_GRP1 ? "En" : "Dis"); 857 } else if (offset < 4) { 858 /* ignored. */ 859 } else if (offset >= 0x80) { 860 /* Interrupt Group Registers: RAZ/WI for NS access to secure 861 * GIC, or for GICs without groups. 862 */ 863 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 864 /* Every byte offset holds 8 group status bits */ 865 irq = (offset - 0x80) * 8 + GIC_BASE_IRQ; 866 if (irq >= s->num_irq) { 867 goto bad_reg; 868 } 869 for (i = 0; i < 8; i++) { 870 /* Group bits are banked for private interrupts */ 871 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 872 if (value & (1 << i)) { 873 /* Group1 (Non-secure) */ 874 GIC_SET_GROUP(irq + i, cm); 875 } else { 876 /* Group0 (Secure) */ 877 GIC_CLEAR_GROUP(irq + i, cm); 878 } 879 } 880 } 881 } else { 882 goto bad_reg; 883 } 884 } else if (offset < 0x180) { 885 /* Interrupt Set Enable. */ 886 irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; 887 if (irq >= s->num_irq) 888 goto bad_reg; 889 if (irq < GIC_NR_SGIS) { 890 value = 0xff; 891 } 892 893 for (i = 0; i < 8; i++) { 894 if (value & (1 << i)) { 895 int mask = 896 (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq + i); 897 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 898 899 if (s->security_extn && !attrs.secure && 900 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 901 continue; /* Ignore Non-secure access of Group0 IRQ */ 902 } 903 904 if (!GIC_TEST_ENABLED(irq + i, cm)) { 905 DPRINTF("Enabled IRQ %d\n", irq + i); 906 trace_gic_enable_irq(irq + i); 907 } 908 GIC_SET_ENABLED(irq + i, cm); 909 /* If a raised level triggered IRQ enabled then mark 910 is as pending. */ 911 if (GIC_TEST_LEVEL(irq + i, mask) 912 && !GIC_TEST_EDGE_TRIGGER(irq + i)) { 913 DPRINTF("Set %d pending mask %x\n", irq + i, mask); 914 GIC_SET_PENDING(irq + i, mask); 915 } 916 } 917 } 918 } else if (offset < 0x200) { 919 /* Interrupt Clear Enable. */ 920 irq = (offset - 0x180) * 8 + GIC_BASE_IRQ; 921 if (irq >= s->num_irq) 922 goto bad_reg; 923 if (irq < GIC_NR_SGIS) { 924 value = 0; 925 } 926 927 for (i = 0; i < 8; i++) { 928 if (value & (1 << i)) { 929 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 930 931 if (s->security_extn && !attrs.secure && 932 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 933 continue; /* Ignore Non-secure access of Group0 IRQ */ 934 } 935 936 if (GIC_TEST_ENABLED(irq + i, cm)) { 937 DPRINTF("Disabled IRQ %d\n", irq + i); 938 trace_gic_disable_irq(irq + i); 939 } 940 GIC_CLEAR_ENABLED(irq + i, cm); 941 } 942 } 943 } else if (offset < 0x280) { 944 /* Interrupt Set Pending. */ 945 irq = (offset - 0x200) * 8 + GIC_BASE_IRQ; 946 if (irq >= s->num_irq) 947 goto bad_reg; 948 if (irq < GIC_NR_SGIS) { 949 value = 0; 950 } 951 952 for (i = 0; i < 8; i++) { 953 if (value & (1 << i)) { 954 if (s->security_extn && !attrs.secure && 955 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 956 continue; /* Ignore Non-secure access of Group0 IRQ */ 957 } 958 959 GIC_SET_PENDING(irq + i, GIC_TARGET(irq + i)); 960 } 961 } 962 } else if (offset < 0x300) { 963 /* Interrupt Clear Pending. */ 964 irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; 965 if (irq >= s->num_irq) 966 goto bad_reg; 967 if (irq < GIC_NR_SGIS) { 968 value = 0; 969 } 970 971 for (i = 0; i < 8; i++) { 972 if (s->security_extn && !attrs.secure && 973 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 974 continue; /* Ignore Non-secure access of Group0 IRQ */ 975 } 976 977 /* ??? This currently clears the pending bit for all CPUs, even 978 for per-CPU interrupts. It's unclear whether this is the 979 corect behavior. */ 980 if (value & (1 << i)) { 981 GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK); 982 } 983 } 984 } else if (offset < 0x400) { 985 /* Interrupt Active. */ 986 goto bad_reg; 987 } else if (offset < 0x800) { 988 /* Interrupt Priority. */ 989 irq = (offset - 0x400) + GIC_BASE_IRQ; 990 if (irq >= s->num_irq) 991 goto bad_reg; 992 gic_set_priority(s, cpu, irq, value, attrs); 993 } else if (offset < 0xc00) { 994 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the 995 * annoying exception of the 11MPCore's GIC. 996 */ 997 if (s->num_cpu != 1 || s->revision == REV_11MPCORE) { 998 irq = (offset - 0x800) + GIC_BASE_IRQ; 999 if (irq >= s->num_irq) { 1000 goto bad_reg; 1001 } 1002 if (irq < 29) { 1003 value = 0; 1004 } else if (irq < GIC_INTERNAL) { 1005 value = ALL_CPU_MASK; 1006 } 1007 s->irq_target[irq] = value & ALL_CPU_MASK; 1008 } 1009 } else if (offset < 0xf00) { 1010 /* Interrupt Configuration. */ 1011 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 1012 if (irq >= s->num_irq) 1013 goto bad_reg; 1014 if (irq < GIC_NR_SGIS) 1015 value |= 0xaa; 1016 for (i = 0; i < 4; i++) { 1017 if (s->security_extn && !attrs.secure && 1018 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 1019 continue; /* Ignore Non-secure access of Group0 IRQ */ 1020 } 1021 1022 if (s->revision == REV_11MPCORE) { 1023 if (value & (1 << (i * 2))) { 1024 GIC_SET_MODEL(irq + i); 1025 } else { 1026 GIC_CLEAR_MODEL(irq + i); 1027 } 1028 } 1029 if (value & (2 << (i * 2))) { 1030 GIC_SET_EDGE_TRIGGER(irq + i); 1031 } else { 1032 GIC_CLEAR_EDGE_TRIGGER(irq + i); 1033 } 1034 } 1035 } else if (offset < 0xf10) { 1036 /* 0xf00 is only handled for 32-bit writes. */ 1037 goto bad_reg; 1038 } else if (offset < 0xf20) { 1039 /* GICD_CPENDSGIRn */ 1040 if (s->revision == REV_11MPCORE) { 1041 goto bad_reg; 1042 } 1043 irq = (offset - 0xf10); 1044 1045 if (!s->security_extn || attrs.secure || 1046 GIC_TEST_GROUP(irq, 1 << cpu)) { 1047 s->sgi_pending[irq][cpu] &= ~value; 1048 if (s->sgi_pending[irq][cpu] == 0) { 1049 GIC_CLEAR_PENDING(irq, 1 << cpu); 1050 } 1051 } 1052 } else if (offset < 0xf30) { 1053 /* GICD_SPENDSGIRn */ 1054 if (s->revision == REV_11MPCORE) { 1055 goto bad_reg; 1056 } 1057 irq = (offset - 0xf20); 1058 1059 if (!s->security_extn || attrs.secure || 1060 GIC_TEST_GROUP(irq, 1 << cpu)) { 1061 GIC_SET_PENDING(irq, 1 << cpu); 1062 s->sgi_pending[irq][cpu] |= value; 1063 } 1064 } else { 1065 goto bad_reg; 1066 } 1067 gic_update(s); 1068 return; 1069 bad_reg: 1070 qemu_log_mask(LOG_GUEST_ERROR, 1071 "gic_dist_writeb: Bad offset %x\n", (int)offset); 1072 } 1073 1074 static void gic_dist_writew(void *opaque, hwaddr offset, 1075 uint32_t value, MemTxAttrs attrs) 1076 { 1077 gic_dist_writeb(opaque, offset, value & 0xff, attrs); 1078 gic_dist_writeb(opaque, offset + 1, value >> 8, attrs); 1079 } 1080 1081 static void gic_dist_writel(void *opaque, hwaddr offset, 1082 uint32_t value, MemTxAttrs attrs) 1083 { 1084 GICState *s = (GICState *)opaque; 1085 if (offset == 0xf00) { 1086 int cpu; 1087 int irq; 1088 int mask; 1089 int target_cpu; 1090 1091 cpu = gic_get_current_cpu(s); 1092 irq = value & 0x3ff; 1093 switch ((value >> 24) & 3) { 1094 case 0: 1095 mask = (value >> 16) & ALL_CPU_MASK; 1096 break; 1097 case 1: 1098 mask = ALL_CPU_MASK ^ (1 << cpu); 1099 break; 1100 case 2: 1101 mask = 1 << cpu; 1102 break; 1103 default: 1104 DPRINTF("Bad Soft Int target filter\n"); 1105 mask = ALL_CPU_MASK; 1106 break; 1107 } 1108 GIC_SET_PENDING(irq, mask); 1109 target_cpu = ctz32(mask); 1110 while (target_cpu < GIC_NCPU) { 1111 s->sgi_pending[irq][target_cpu] |= (1 << cpu); 1112 mask &= ~(1 << target_cpu); 1113 target_cpu = ctz32(mask); 1114 } 1115 gic_update(s); 1116 return; 1117 } 1118 gic_dist_writew(opaque, offset, value & 0xffff, attrs); 1119 gic_dist_writew(opaque, offset + 2, value >> 16, attrs); 1120 } 1121 1122 static MemTxResult gic_dist_write(void *opaque, hwaddr offset, uint64_t data, 1123 unsigned size, MemTxAttrs attrs) 1124 { 1125 switch (size) { 1126 case 1: 1127 gic_dist_writeb(opaque, offset, data, attrs); 1128 return MEMTX_OK; 1129 case 2: 1130 gic_dist_writew(opaque, offset, data, attrs); 1131 return MEMTX_OK; 1132 case 4: 1133 gic_dist_writel(opaque, offset, data, attrs); 1134 return MEMTX_OK; 1135 default: 1136 return MEMTX_ERROR; 1137 } 1138 } 1139 1140 static inline uint32_t gic_apr_ns_view(GICState *s, int cpu, int regno) 1141 { 1142 /* Return the Nonsecure view of GICC_APR<regno>. This is the 1143 * second half of GICC_NSAPR. 1144 */ 1145 switch (GIC_MIN_BPR) { 1146 case 0: 1147 if (regno < 2) { 1148 return s->nsapr[regno + 2][cpu]; 1149 } 1150 break; 1151 case 1: 1152 if (regno == 0) { 1153 return s->nsapr[regno + 1][cpu]; 1154 } 1155 break; 1156 case 2: 1157 if (regno == 0) { 1158 return extract32(s->nsapr[0][cpu], 16, 16); 1159 } 1160 break; 1161 case 3: 1162 if (regno == 0) { 1163 return extract32(s->nsapr[0][cpu], 8, 8); 1164 } 1165 break; 1166 default: 1167 g_assert_not_reached(); 1168 } 1169 return 0; 1170 } 1171 1172 static inline void gic_apr_write_ns_view(GICState *s, int cpu, int regno, 1173 uint32_t value) 1174 { 1175 /* Write the Nonsecure view of GICC_APR<regno>. */ 1176 switch (GIC_MIN_BPR) { 1177 case 0: 1178 if (regno < 2) { 1179 s->nsapr[regno + 2][cpu] = value; 1180 } 1181 break; 1182 case 1: 1183 if (regno == 0) { 1184 s->nsapr[regno + 1][cpu] = value; 1185 } 1186 break; 1187 case 2: 1188 if (regno == 0) { 1189 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 16, 16, value); 1190 } 1191 break; 1192 case 3: 1193 if (regno == 0) { 1194 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 8, 8, value); 1195 } 1196 break; 1197 default: 1198 g_assert_not_reached(); 1199 } 1200 } 1201 1202 static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset, 1203 uint64_t *data, MemTxAttrs attrs) 1204 { 1205 switch (offset) { 1206 case 0x00: /* Control */ 1207 *data = gic_get_cpu_control(s, cpu, attrs); 1208 break; 1209 case 0x04: /* Priority mask */ 1210 *data = gic_get_priority_mask(s, cpu, attrs); 1211 break; 1212 case 0x08: /* Binary Point */ 1213 if (s->security_extn && !attrs.secure) { 1214 /* BPR is banked. Non-secure copy stored in ABPR. */ 1215 *data = s->abpr[cpu]; 1216 } else { 1217 *data = s->bpr[cpu]; 1218 } 1219 break; 1220 case 0x0c: /* Acknowledge */ 1221 *data = gic_acknowledge_irq(s, cpu, attrs); 1222 break; 1223 case 0x14: /* Running Priority */ 1224 *data = gic_get_running_priority(s, cpu, attrs); 1225 break; 1226 case 0x18: /* Highest Pending Interrupt */ 1227 *data = gic_get_current_pending_irq(s, cpu, attrs); 1228 break; 1229 case 0x1c: /* Aliased Binary Point */ 1230 /* GIC v2, no security: ABPR 1231 * GIC v1, no security: not implemented (RAZ/WI) 1232 * With security extensions, secure access: ABPR (alias of NS BPR) 1233 * With security extensions, nonsecure access: RAZ/WI 1234 */ 1235 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 1236 *data = 0; 1237 } else { 1238 *data = s->abpr[cpu]; 1239 } 1240 break; 1241 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 1242 { 1243 int regno = (offset - 0xd0) / 4; 1244 1245 if (regno >= GIC_NR_APRS || s->revision != 2) { 1246 *data = 0; 1247 } else if (s->security_extn && !attrs.secure) { 1248 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ 1249 *data = gic_apr_ns_view(s, regno, cpu); 1250 } else { 1251 *data = s->apr[regno][cpu]; 1252 } 1253 break; 1254 } 1255 case 0xe0: case 0xe4: case 0xe8: case 0xec: 1256 { 1257 int regno = (offset - 0xe0) / 4; 1258 1259 if (regno >= GIC_NR_APRS || s->revision != 2 || !gic_has_groups(s) || 1260 (s->security_extn && !attrs.secure)) { 1261 *data = 0; 1262 } else { 1263 *data = s->nsapr[regno][cpu]; 1264 } 1265 break; 1266 } 1267 default: 1268 qemu_log_mask(LOG_GUEST_ERROR, 1269 "gic_cpu_read: Bad offset %x\n", (int)offset); 1270 *data = 0; 1271 break; 1272 } 1273 return MEMTX_OK; 1274 } 1275 1276 static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset, 1277 uint32_t value, MemTxAttrs attrs) 1278 { 1279 switch (offset) { 1280 case 0x00: /* Control */ 1281 gic_set_cpu_control(s, cpu, value, attrs); 1282 break; 1283 case 0x04: /* Priority mask */ 1284 gic_set_priority_mask(s, cpu, value, attrs); 1285 break; 1286 case 0x08: /* Binary Point */ 1287 if (s->security_extn && !attrs.secure) { 1288 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 1289 } else { 1290 s->bpr[cpu] = MAX(value & 0x7, GIC_MIN_BPR); 1291 } 1292 break; 1293 case 0x10: /* End Of Interrupt */ 1294 gic_complete_irq(s, cpu, value & 0x3ff, attrs); 1295 return MEMTX_OK; 1296 case 0x1c: /* Aliased Binary Point */ 1297 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 1298 /* unimplemented, or NS access: RAZ/WI */ 1299 return MEMTX_OK; 1300 } else { 1301 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 1302 } 1303 break; 1304 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 1305 { 1306 int regno = (offset - 0xd0) / 4; 1307 1308 if (regno >= GIC_NR_APRS || s->revision != 2) { 1309 return MEMTX_OK; 1310 } 1311 if (s->security_extn && !attrs.secure) { 1312 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ 1313 gic_apr_write_ns_view(s, regno, cpu, value); 1314 } else { 1315 s->apr[regno][cpu] = value; 1316 } 1317 break; 1318 } 1319 case 0xe0: case 0xe4: case 0xe8: case 0xec: 1320 { 1321 int regno = (offset - 0xe0) / 4; 1322 1323 if (regno >= GIC_NR_APRS || s->revision != 2) { 1324 return MEMTX_OK; 1325 } 1326 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 1327 return MEMTX_OK; 1328 } 1329 s->nsapr[regno][cpu] = value; 1330 break; 1331 } 1332 case 0x1000: 1333 /* GICC_DIR */ 1334 gic_deactivate_irq(s, cpu, value & 0x3ff, attrs); 1335 break; 1336 default: 1337 qemu_log_mask(LOG_GUEST_ERROR, 1338 "gic_cpu_write: Bad offset %x\n", (int)offset); 1339 return MEMTX_OK; 1340 } 1341 gic_update(s); 1342 return MEMTX_OK; 1343 } 1344 1345 /* Wrappers to read/write the GIC CPU interface for the current CPU */ 1346 static MemTxResult gic_thiscpu_read(void *opaque, hwaddr addr, uint64_t *data, 1347 unsigned size, MemTxAttrs attrs) 1348 { 1349 GICState *s = (GICState *)opaque; 1350 return gic_cpu_read(s, gic_get_current_cpu(s), addr, data, attrs); 1351 } 1352 1353 static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, 1354 uint64_t value, unsigned size, 1355 MemTxAttrs attrs) 1356 { 1357 GICState *s = (GICState *)opaque; 1358 return gic_cpu_write(s, gic_get_current_cpu(s), addr, value, attrs); 1359 } 1360 1361 /* Wrappers to read/write the GIC CPU interface for a specific CPU. 1362 * These just decode the opaque pointer into GICState* + cpu id. 1363 */ 1364 static MemTxResult gic_do_cpu_read(void *opaque, hwaddr addr, uint64_t *data, 1365 unsigned size, MemTxAttrs attrs) 1366 { 1367 GICState **backref = (GICState **)opaque; 1368 GICState *s = *backref; 1369 int id = (backref - s->backref); 1370 return gic_cpu_read(s, id, addr, data, attrs); 1371 } 1372 1373 static MemTxResult gic_do_cpu_write(void *opaque, hwaddr addr, 1374 uint64_t value, unsigned size, 1375 MemTxAttrs attrs) 1376 { 1377 GICState **backref = (GICState **)opaque; 1378 GICState *s = *backref; 1379 int id = (backref - s->backref); 1380 return gic_cpu_write(s, id, addr, value, attrs); 1381 } 1382 1383 static const MemoryRegionOps gic_ops[2] = { 1384 { 1385 .read_with_attrs = gic_dist_read, 1386 .write_with_attrs = gic_dist_write, 1387 .endianness = DEVICE_NATIVE_ENDIAN, 1388 }, 1389 { 1390 .read_with_attrs = gic_thiscpu_read, 1391 .write_with_attrs = gic_thiscpu_write, 1392 .endianness = DEVICE_NATIVE_ENDIAN, 1393 } 1394 }; 1395 1396 static const MemoryRegionOps gic_cpu_ops = { 1397 .read_with_attrs = gic_do_cpu_read, 1398 .write_with_attrs = gic_do_cpu_write, 1399 .endianness = DEVICE_NATIVE_ENDIAN, 1400 }; 1401 1402 /* This function is used by nvic model */ 1403 void gic_init_irqs_and_distributor(GICState *s) 1404 { 1405 gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops); 1406 } 1407 1408 static void arm_gic_realize(DeviceState *dev, Error **errp) 1409 { 1410 /* Device instance realize function for the GIC sysbus device */ 1411 int i; 1412 GICState *s = ARM_GIC(dev); 1413 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1414 ARMGICClass *agc = ARM_GIC_GET_CLASS(s); 1415 Error *local_err = NULL; 1416 1417 agc->parent_realize(dev, &local_err); 1418 if (local_err) { 1419 error_propagate(errp, local_err); 1420 return; 1421 } 1422 1423 if (kvm_enabled() && !kvm_arm_supports_user_irq()) { 1424 error_setg(errp, "KVM with user space irqchip only works when the " 1425 "host kernel supports KVM_CAP_ARM_USER_IRQ"); 1426 return; 1427 } 1428 1429 /* This creates distributor and main CPU interface (s->cpuiomem[0]) */ 1430 gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops); 1431 1432 /* Extra core-specific regions for the CPU interfaces. This is 1433 * necessary for "franken-GIC" implementations, for example on 1434 * Exynos 4. 1435 * NB that the memory region size of 0x100 applies for the 11MPCore 1436 * and also cores following the GIC v1 spec (ie A9). 1437 * GIC v2 defines a larger memory region (0x1000) so this will need 1438 * to be extended when we implement A15. 1439 */ 1440 for (i = 0; i < s->num_cpu; i++) { 1441 s->backref[i] = s; 1442 memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops, 1443 &s->backref[i], "gic_cpu", 0x100); 1444 sysbus_init_mmio(sbd, &s->cpuiomem[i+1]); 1445 } 1446 } 1447 1448 static void arm_gic_class_init(ObjectClass *klass, void *data) 1449 { 1450 DeviceClass *dc = DEVICE_CLASS(klass); 1451 ARMGICClass *agc = ARM_GIC_CLASS(klass); 1452 1453 agc->parent_realize = dc->realize; 1454 dc->realize = arm_gic_realize; 1455 } 1456 1457 static const TypeInfo arm_gic_info = { 1458 .name = TYPE_ARM_GIC, 1459 .parent = TYPE_ARM_GIC_COMMON, 1460 .instance_size = sizeof(GICState), 1461 .class_init = arm_gic_class_init, 1462 .class_size = sizeof(ARMGICClass), 1463 }; 1464 1465 static void arm_gic_register_types(void) 1466 { 1467 type_register_static(&arm_gic_info); 1468 } 1469 1470 type_init(arm_gic_register_types) 1471