1 /* 2 * ARM Generic/Distributed Interrupt Controller 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 /* This file contains implementation code for the RealView EB interrupt 11 * controller, MPCore distributed interrupt controller and ARMv7-M 12 * Nested Vectored Interrupt Controller. 13 * It is compiled in two ways: 14 * (1) as a standalone file to produce a sysbus device which is a GIC 15 * that can be used on the realview board and as one of the builtin 16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc) 17 * (2) by being directly #included into armv7m_nvic.c to produce the 18 * armv7m_nvic device. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/sysbus.h" 23 #include "gic_internal.h" 24 #include "qapi/error.h" 25 #include "qom/cpu.h" 26 #include "qemu/log.h" 27 #include "trace.h" 28 #include "sysemu/kvm.h" 29 30 /* #define DEBUG_GIC */ 31 32 #ifdef DEBUG_GIC 33 #define DEBUG_GIC_GATE 1 34 #else 35 #define DEBUG_GIC_GATE 0 36 #endif 37 38 #define DPRINTF(fmt, ...) do { \ 39 if (DEBUG_GIC_GATE) { \ 40 fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \ 41 } \ 42 } while (0) 43 44 static const uint8_t gic_id_11mpcore[] = { 45 0x00, 0x00, 0x00, 0x00, 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 46 }; 47 48 static const uint8_t gic_id_gicv1[] = { 49 0x04, 0x00, 0x00, 0x00, 0x90, 0xb3, 0x1b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 50 }; 51 52 static const uint8_t gic_id_gicv2[] = { 53 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 54 }; 55 56 static inline int gic_get_current_cpu(GICState *s) 57 { 58 if (s->num_cpu > 1) { 59 return current_cpu->cpu_index; 60 } 61 return 0; 62 } 63 64 /* Return true if this GIC config has interrupt groups, which is 65 * true if we're a GICv2, or a GICv1 with the security extensions. 66 */ 67 static inline bool gic_has_groups(GICState *s) 68 { 69 return s->revision == 2 || s->security_extn; 70 } 71 72 /* TODO: Many places that call this routine could be optimized. */ 73 /* Update interrupt status after enabled or pending bits have been changed. */ 74 void gic_update(GICState *s) 75 { 76 int best_irq; 77 int best_prio; 78 int irq; 79 int irq_level, fiq_level; 80 int cpu; 81 int cm; 82 83 for (cpu = 0; cpu < s->num_cpu; cpu++) { 84 cm = 1 << cpu; 85 s->current_pending[cpu] = 1023; 86 if (!(s->ctlr & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1)) 87 || !(s->cpu_ctlr[cpu] & (GICC_CTLR_EN_GRP0 | GICC_CTLR_EN_GRP1))) { 88 qemu_irq_lower(s->parent_irq[cpu]); 89 qemu_irq_lower(s->parent_fiq[cpu]); 90 continue; 91 } 92 best_prio = 0x100; 93 best_irq = 1023; 94 for (irq = 0; irq < s->num_irq; irq++) { 95 if (GIC_DIST_TEST_ENABLED(irq, cm) && 96 gic_test_pending(s, irq, cm) && 97 (!GIC_DIST_TEST_ACTIVE(irq, cm)) && 98 (irq < GIC_INTERNAL || GIC_DIST_TARGET(irq) & cm)) { 99 if (GIC_DIST_GET_PRIORITY(irq, cpu) < best_prio) { 100 best_prio = GIC_DIST_GET_PRIORITY(irq, cpu); 101 best_irq = irq; 102 } 103 } 104 } 105 106 if (best_irq != 1023) { 107 trace_gic_update_bestirq(cpu, best_irq, best_prio, 108 s->priority_mask[cpu], s->running_priority[cpu]); 109 } 110 111 irq_level = fiq_level = 0; 112 113 if (best_prio < s->priority_mask[cpu]) { 114 s->current_pending[cpu] = best_irq; 115 if (best_prio < s->running_priority[cpu]) { 116 int group = GIC_DIST_TEST_GROUP(best_irq, cm); 117 118 if (extract32(s->ctlr, group, 1) && 119 extract32(s->cpu_ctlr[cpu], group, 1)) { 120 if (group == 0 && s->cpu_ctlr[cpu] & GICC_CTLR_FIQ_EN) { 121 DPRINTF("Raised pending FIQ %d (cpu %d)\n", 122 best_irq, cpu); 123 fiq_level = 1; 124 trace_gic_update_set_irq(cpu, "fiq", fiq_level); 125 } else { 126 DPRINTF("Raised pending IRQ %d (cpu %d)\n", 127 best_irq, cpu); 128 irq_level = 1; 129 trace_gic_update_set_irq(cpu, "irq", irq_level); 130 } 131 } 132 } 133 } 134 135 qemu_set_irq(s->parent_irq[cpu], irq_level); 136 qemu_set_irq(s->parent_fiq[cpu], fiq_level); 137 } 138 } 139 140 void gic_set_pending_private(GICState *s, int cpu, int irq) 141 { 142 int cm = 1 << cpu; 143 144 if (gic_test_pending(s, irq, cm)) { 145 return; 146 } 147 148 DPRINTF("Set %d pending cpu %d\n", irq, cpu); 149 GIC_DIST_SET_PENDING(irq, cm); 150 gic_update(s); 151 } 152 153 static void gic_set_irq_11mpcore(GICState *s, int irq, int level, 154 int cm, int target) 155 { 156 if (level) { 157 GIC_DIST_SET_LEVEL(irq, cm); 158 if (GIC_DIST_TEST_EDGE_TRIGGER(irq) || GIC_DIST_TEST_ENABLED(irq, cm)) { 159 DPRINTF("Set %d pending mask %x\n", irq, target); 160 GIC_DIST_SET_PENDING(irq, target); 161 } 162 } else { 163 GIC_DIST_CLEAR_LEVEL(irq, cm); 164 } 165 } 166 167 static void gic_set_irq_generic(GICState *s, int irq, int level, 168 int cm, int target) 169 { 170 if (level) { 171 GIC_DIST_SET_LEVEL(irq, cm); 172 DPRINTF("Set %d pending mask %x\n", irq, target); 173 if (GIC_DIST_TEST_EDGE_TRIGGER(irq)) { 174 GIC_DIST_SET_PENDING(irq, target); 175 } 176 } else { 177 GIC_DIST_CLEAR_LEVEL(irq, cm); 178 } 179 } 180 181 /* Process a change in an external IRQ input. */ 182 static void gic_set_irq(void *opaque, int irq, int level) 183 { 184 /* Meaning of the 'irq' parameter: 185 * [0..N-1] : external interrupts 186 * [N..N+31] : PPI (internal) interrupts for CPU 0 187 * [N+32..N+63] : PPI (internal interrupts for CPU 1 188 * ... 189 */ 190 GICState *s = (GICState *)opaque; 191 int cm, target; 192 if (irq < (s->num_irq - GIC_INTERNAL)) { 193 /* The first external input line is internal interrupt 32. */ 194 cm = ALL_CPU_MASK; 195 irq += GIC_INTERNAL; 196 target = GIC_DIST_TARGET(irq); 197 } else { 198 int cpu; 199 irq -= (s->num_irq - GIC_INTERNAL); 200 cpu = irq / GIC_INTERNAL; 201 irq %= GIC_INTERNAL; 202 cm = 1 << cpu; 203 target = cm; 204 } 205 206 assert(irq >= GIC_NR_SGIS); 207 208 if (level == GIC_DIST_TEST_LEVEL(irq, cm)) { 209 return; 210 } 211 212 if (s->revision == REV_11MPCORE) { 213 gic_set_irq_11mpcore(s, irq, level, cm, target); 214 } else { 215 gic_set_irq_generic(s, irq, level, cm, target); 216 } 217 trace_gic_set_irq(irq, level, cm, target); 218 219 gic_update(s); 220 } 221 222 static uint16_t gic_get_current_pending_irq(GICState *s, int cpu, 223 MemTxAttrs attrs) 224 { 225 uint16_t pending_irq = s->current_pending[cpu]; 226 227 if (pending_irq < GIC_MAXIRQ && gic_has_groups(s)) { 228 int group = GIC_DIST_TEST_GROUP(pending_irq, (1 << cpu)); 229 /* On a GIC without the security extensions, reading this register 230 * behaves in the same way as a secure access to a GIC with them. 231 */ 232 bool secure = !s->security_extn || attrs.secure; 233 234 if (group == 0 && !secure) { 235 /* Group0 interrupts hidden from Non-secure access */ 236 return 1023; 237 } 238 if (group == 1 && secure && !(s->cpu_ctlr[cpu] & GICC_CTLR_ACK_CTL)) { 239 /* Group1 interrupts only seen by Secure access if 240 * AckCtl bit set. 241 */ 242 return 1022; 243 } 244 } 245 return pending_irq; 246 } 247 248 static int gic_get_group_priority(GICState *s, int cpu, int irq) 249 { 250 /* Return the group priority of the specified interrupt 251 * (which is the top bits of its priority, with the number 252 * of bits masked determined by the applicable binary point register). 253 */ 254 int bpr; 255 uint32_t mask; 256 257 if (gic_has_groups(s) && 258 !(s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) && 259 GIC_DIST_TEST_GROUP(irq, (1 << cpu))) { 260 bpr = s->abpr[cpu] - 1; 261 assert(bpr >= 0); 262 } else { 263 bpr = s->bpr[cpu]; 264 } 265 266 /* a BPR of 0 means the group priority bits are [7:1]; 267 * a BPR of 1 means they are [7:2], and so on down to 268 * a BPR of 7 meaning no group priority bits at all. 269 */ 270 mask = ~0U << ((bpr & 7) + 1); 271 272 return GIC_DIST_GET_PRIORITY(irq, cpu) & mask; 273 } 274 275 static void gic_activate_irq(GICState *s, int cpu, int irq) 276 { 277 /* Set the appropriate Active Priority Register bit for this IRQ, 278 * and update the running priority. 279 */ 280 int prio = gic_get_group_priority(s, cpu, irq); 281 int preemption_level = prio >> (GIC_MIN_BPR + 1); 282 int regno = preemption_level / 32; 283 int bitno = preemption_level % 32; 284 285 if (gic_has_groups(s) && GIC_DIST_TEST_GROUP(irq, (1 << cpu))) { 286 s->nsapr[regno][cpu] |= (1 << bitno); 287 } else { 288 s->apr[regno][cpu] |= (1 << bitno); 289 } 290 291 s->running_priority[cpu] = prio; 292 GIC_DIST_SET_ACTIVE(irq, 1 << cpu); 293 } 294 295 static int gic_get_prio_from_apr_bits(GICState *s, int cpu) 296 { 297 /* Recalculate the current running priority for this CPU based 298 * on the set bits in the Active Priority Registers. 299 */ 300 int i; 301 for (i = 0; i < GIC_NR_APRS; i++) { 302 uint32_t apr = s->apr[i][cpu] | s->nsapr[i][cpu]; 303 if (!apr) { 304 continue; 305 } 306 return (i * 32 + ctz32(apr)) << (GIC_MIN_BPR + 1); 307 } 308 return 0x100; 309 } 310 311 static void gic_drop_prio(GICState *s, int cpu, int group) 312 { 313 /* Drop the priority of the currently active interrupt in the 314 * specified group. 315 * 316 * Note that we can guarantee (because of the requirement to nest 317 * GICC_IAR reads [which activate an interrupt and raise priority] 318 * with GICC_EOIR writes [which drop the priority for the interrupt]) 319 * that the interrupt we're being called for is the highest priority 320 * active interrupt, meaning that it has the lowest set bit in the 321 * APR registers. 322 * 323 * If the guest does not honour the ordering constraints then the 324 * behaviour of the GIC is UNPREDICTABLE, which for us means that 325 * the values of the APR registers might become incorrect and the 326 * running priority will be wrong, so interrupts that should preempt 327 * might not do so, and interrupts that should not preempt might do so. 328 */ 329 int i; 330 331 for (i = 0; i < GIC_NR_APRS; i++) { 332 uint32_t *papr = group ? &s->nsapr[i][cpu] : &s->apr[i][cpu]; 333 if (!*papr) { 334 continue; 335 } 336 /* Clear lowest set bit */ 337 *papr &= *papr - 1; 338 break; 339 } 340 341 s->running_priority[cpu] = gic_get_prio_from_apr_bits(s, cpu); 342 } 343 344 uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs) 345 { 346 int ret, irq, src; 347 int cm = 1 << cpu; 348 349 /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately 350 * for the case where this GIC supports grouping and the pending interrupt 351 * is in the wrong group. 352 */ 353 irq = gic_get_current_pending_irq(s, cpu, attrs); 354 trace_gic_acknowledge_irq(cpu, irq); 355 356 if (irq >= GIC_MAXIRQ) { 357 DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq); 358 return irq; 359 } 360 361 if (GIC_DIST_GET_PRIORITY(irq, cpu) >= s->running_priority[cpu]) { 362 DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq); 363 return 1023; 364 } 365 366 if (s->revision == REV_11MPCORE) { 367 /* Clear pending flags for both level and edge triggered interrupts. 368 * Level triggered IRQs will be reasserted once they become inactive. 369 */ 370 GIC_DIST_CLEAR_PENDING(irq, GIC_DIST_TEST_MODEL(irq) ? ALL_CPU_MASK 371 : cm); 372 ret = irq; 373 } else { 374 if (irq < GIC_NR_SGIS) { 375 /* Lookup the source CPU for the SGI and clear this in the 376 * sgi_pending map. Return the src and clear the overall pending 377 * state on this CPU if the SGI is not pending from any CPUs. 378 */ 379 assert(s->sgi_pending[irq][cpu] != 0); 380 src = ctz32(s->sgi_pending[irq][cpu]); 381 s->sgi_pending[irq][cpu] &= ~(1 << src); 382 if (s->sgi_pending[irq][cpu] == 0) { 383 GIC_DIST_CLEAR_PENDING(irq, 384 GIC_DIST_TEST_MODEL(irq) ? ALL_CPU_MASK 385 : cm); 386 } 387 ret = irq | ((src & 0x7) << 10); 388 } else { 389 /* Clear pending state for both level and edge triggered 390 * interrupts. (level triggered interrupts with an active line 391 * remain pending, see gic_test_pending) 392 */ 393 GIC_DIST_CLEAR_PENDING(irq, GIC_DIST_TEST_MODEL(irq) ? ALL_CPU_MASK 394 : cm); 395 ret = irq; 396 } 397 } 398 399 gic_activate_irq(s, cpu, irq); 400 gic_update(s); 401 DPRINTF("ACK %d\n", irq); 402 return ret; 403 } 404 405 void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val, 406 MemTxAttrs attrs) 407 { 408 if (s->security_extn && !attrs.secure) { 409 if (!GIC_DIST_TEST_GROUP(irq, (1 << cpu))) { 410 return; /* Ignore Non-secure access of Group0 IRQ */ 411 } 412 val = 0x80 | (val >> 1); /* Non-secure view */ 413 } 414 415 if (irq < GIC_INTERNAL) { 416 s->priority1[irq][cpu] = val; 417 } else { 418 s->priority2[(irq) - GIC_INTERNAL] = val; 419 } 420 } 421 422 static uint32_t gic_dist_get_priority(GICState *s, int cpu, int irq, 423 MemTxAttrs attrs) 424 { 425 uint32_t prio = GIC_DIST_GET_PRIORITY(irq, cpu); 426 427 if (s->security_extn && !attrs.secure) { 428 if (!GIC_DIST_TEST_GROUP(irq, (1 << cpu))) { 429 return 0; /* Non-secure access cannot read priority of Group0 IRQ */ 430 } 431 prio = (prio << 1) & 0xff; /* Non-secure view */ 432 } 433 return prio; 434 } 435 436 static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, 437 MemTxAttrs attrs) 438 { 439 if (s->security_extn && !attrs.secure) { 440 if (s->priority_mask[cpu] & 0x80) { 441 /* Priority Mask in upper half */ 442 pmask = 0x80 | (pmask >> 1); 443 } else { 444 /* Non-secure write ignored if priority mask is in lower half */ 445 return; 446 } 447 } 448 s->priority_mask[cpu] = pmask; 449 } 450 451 static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs) 452 { 453 uint32_t pmask = s->priority_mask[cpu]; 454 455 if (s->security_extn && !attrs.secure) { 456 if (pmask & 0x80) { 457 /* Priority Mask in upper half, return Non-secure view */ 458 pmask = (pmask << 1) & 0xff; 459 } else { 460 /* Priority Mask in lower half, RAZ */ 461 pmask = 0; 462 } 463 } 464 return pmask; 465 } 466 467 static uint32_t gic_get_cpu_control(GICState *s, int cpu, MemTxAttrs attrs) 468 { 469 uint32_t ret = s->cpu_ctlr[cpu]; 470 471 if (s->security_extn && !attrs.secure) { 472 /* Construct the NS banked view of GICC_CTLR from the correct 473 * bits of the S banked view. We don't need to move the bypass 474 * control bits because we don't implement that (IMPDEF) part 475 * of the GIC architecture. 476 */ 477 ret = (ret & (GICC_CTLR_EN_GRP1 | GICC_CTLR_EOIMODE_NS)) >> 1; 478 } 479 return ret; 480 } 481 482 static void gic_set_cpu_control(GICState *s, int cpu, uint32_t value, 483 MemTxAttrs attrs) 484 { 485 uint32_t mask; 486 487 if (s->security_extn && !attrs.secure) { 488 /* The NS view can only write certain bits in the register; 489 * the rest are unchanged 490 */ 491 mask = GICC_CTLR_EN_GRP1; 492 if (s->revision == 2) { 493 mask |= GICC_CTLR_EOIMODE_NS; 494 } 495 s->cpu_ctlr[cpu] &= ~mask; 496 s->cpu_ctlr[cpu] |= (value << 1) & mask; 497 } else { 498 if (s->revision == 2) { 499 mask = s->security_extn ? GICC_CTLR_V2_S_MASK : GICC_CTLR_V2_MASK; 500 } else { 501 mask = s->security_extn ? GICC_CTLR_V1_S_MASK : GICC_CTLR_V1_MASK; 502 } 503 s->cpu_ctlr[cpu] = value & mask; 504 } 505 DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, " 506 "Group1 Interrupts %sabled\n", cpu, 507 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP0) ? "En" : "Dis", 508 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP1) ? "En" : "Dis"); 509 } 510 511 static uint8_t gic_get_running_priority(GICState *s, int cpu, MemTxAttrs attrs) 512 { 513 if ((s->revision != REV_11MPCORE) && (s->running_priority[cpu] > 0xff)) { 514 /* Idle priority */ 515 return 0xff; 516 } 517 518 if (s->security_extn && !attrs.secure) { 519 if (s->running_priority[cpu] & 0x80) { 520 /* Running priority in upper half of range: return the Non-secure 521 * view of the priority. 522 */ 523 return s->running_priority[cpu] << 1; 524 } else { 525 /* Running priority in lower half of range: RAZ */ 526 return 0; 527 } 528 } else { 529 return s->running_priority[cpu]; 530 } 531 } 532 533 /* Return true if we should split priority drop and interrupt deactivation, 534 * ie whether the relevant EOIMode bit is set. 535 */ 536 static bool gic_eoi_split(GICState *s, int cpu, MemTxAttrs attrs) 537 { 538 if (s->revision != 2) { 539 /* Before GICv2 prio-drop and deactivate are not separable */ 540 return false; 541 } 542 if (s->security_extn && !attrs.secure) { 543 return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE_NS; 544 } 545 return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE; 546 } 547 548 static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) 549 { 550 int cm = 1 << cpu; 551 int group; 552 553 if (irq >= s->num_irq) { 554 /* 555 * This handles two cases: 556 * 1. If software writes the ID of a spurious interrupt [ie 1023] 557 * to the GICC_DIR, the GIC ignores that write. 558 * 2. If software writes the number of a non-existent interrupt 559 * this must be a subcase of "value written is not an active interrupt" 560 * and so this is UNPREDICTABLE. We choose to ignore it. 561 */ 562 return; 563 } 564 565 group = gic_has_groups(s) && GIC_DIST_TEST_GROUP(irq, cm); 566 567 if (!gic_eoi_split(s, cpu, attrs)) { 568 /* This is UNPREDICTABLE; we choose to ignore it */ 569 qemu_log_mask(LOG_GUEST_ERROR, 570 "gic_deactivate_irq: GICC_DIR write when EOIMode clear"); 571 return; 572 } 573 574 if (s->security_extn && !attrs.secure && !group) { 575 DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq); 576 return; 577 } 578 579 GIC_DIST_CLEAR_ACTIVE(irq, cm); 580 } 581 582 void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) 583 { 584 int cm = 1 << cpu; 585 int group; 586 587 DPRINTF("EOI %d\n", irq); 588 if (irq >= s->num_irq) { 589 /* This handles two cases: 590 * 1. If software writes the ID of a spurious interrupt [ie 1023] 591 * to the GICC_EOIR, the GIC ignores that write. 592 * 2. If software writes the number of a non-existent interrupt 593 * this must be a subcase of "value written does not match the last 594 * valid interrupt value read from the Interrupt Acknowledge 595 * register" and so this is UNPREDICTABLE. We choose to ignore it. 596 */ 597 return; 598 } 599 if (s->running_priority[cpu] == 0x100) { 600 return; /* No active IRQ. */ 601 } 602 603 if (s->revision == REV_11MPCORE) { 604 /* Mark level triggered interrupts as pending if they are still 605 raised. */ 606 if (!GIC_DIST_TEST_EDGE_TRIGGER(irq) && GIC_DIST_TEST_ENABLED(irq, cm) 607 && GIC_DIST_TEST_LEVEL(irq, cm) 608 && (GIC_DIST_TARGET(irq) & cm) != 0) { 609 DPRINTF("Set %d pending mask %x\n", irq, cm); 610 GIC_DIST_SET_PENDING(irq, cm); 611 } 612 } 613 614 group = gic_has_groups(s) && GIC_DIST_TEST_GROUP(irq, cm); 615 616 if (s->security_extn && !attrs.secure && !group) { 617 DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq); 618 return; 619 } 620 621 /* Secure EOI with GICC_CTLR.AckCtl == 0 when the IRQ is a Group 1 622 * interrupt is UNPREDICTABLE. We choose to handle it as if AckCtl == 1, 623 * i.e. go ahead and complete the irq anyway. 624 */ 625 626 gic_drop_prio(s, cpu, group); 627 628 /* In GICv2 the guest can choose to split priority-drop and deactivate */ 629 if (!gic_eoi_split(s, cpu, attrs)) { 630 GIC_DIST_CLEAR_ACTIVE(irq, cm); 631 } 632 gic_update(s); 633 } 634 635 static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) 636 { 637 GICState *s = (GICState *)opaque; 638 uint32_t res; 639 int irq; 640 int i; 641 int cpu; 642 int cm; 643 int mask; 644 645 cpu = gic_get_current_cpu(s); 646 cm = 1 << cpu; 647 if (offset < 0x100) { 648 if (offset == 0) { /* GICD_CTLR */ 649 if (s->security_extn && !attrs.secure) { 650 /* The NS bank of this register is just an alias of the 651 * EnableGrp1 bit in the S bank version. 652 */ 653 return extract32(s->ctlr, 1, 1); 654 } else { 655 return s->ctlr; 656 } 657 } 658 if (offset == 4) 659 /* Interrupt Controller Type Register */ 660 return ((s->num_irq / 32) - 1) 661 | ((s->num_cpu - 1) << 5) 662 | (s->security_extn << 10); 663 if (offset < 0x08) 664 return 0; 665 if (offset >= 0x80) { 666 /* Interrupt Group Registers: these RAZ/WI if this is an NS 667 * access to a GIC with the security extensions, or if the GIC 668 * doesn't have groups at all. 669 */ 670 res = 0; 671 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 672 /* Every byte offset holds 8 group status bits */ 673 irq = (offset - 0x080) * 8 + GIC_BASE_IRQ; 674 if (irq >= s->num_irq) { 675 goto bad_reg; 676 } 677 for (i = 0; i < 8; i++) { 678 if (GIC_DIST_TEST_GROUP(irq + i, cm)) { 679 res |= (1 << i); 680 } 681 } 682 } 683 return res; 684 } 685 goto bad_reg; 686 } else if (offset < 0x200) { 687 /* Interrupt Set/Clear Enable. */ 688 if (offset < 0x180) 689 irq = (offset - 0x100) * 8; 690 else 691 irq = (offset - 0x180) * 8; 692 irq += GIC_BASE_IRQ; 693 if (irq >= s->num_irq) 694 goto bad_reg; 695 res = 0; 696 for (i = 0; i < 8; i++) { 697 if (s->security_extn && !attrs.secure && 698 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 699 continue; /* Ignore Non-secure access of Group0 IRQ */ 700 } 701 702 if (GIC_DIST_TEST_ENABLED(irq + i, cm)) { 703 res |= (1 << i); 704 } 705 } 706 } else if (offset < 0x300) { 707 /* Interrupt Set/Clear Pending. */ 708 if (offset < 0x280) 709 irq = (offset - 0x200) * 8; 710 else 711 irq = (offset - 0x280) * 8; 712 irq += GIC_BASE_IRQ; 713 if (irq >= s->num_irq) 714 goto bad_reg; 715 res = 0; 716 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 717 for (i = 0; i < 8; i++) { 718 if (s->security_extn && !attrs.secure && 719 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 720 continue; /* Ignore Non-secure access of Group0 IRQ */ 721 } 722 723 if (gic_test_pending(s, irq + i, mask)) { 724 res |= (1 << i); 725 } 726 } 727 } else if (offset < 0x400) { 728 /* Interrupt Active. */ 729 irq = (offset - 0x300) * 8 + GIC_BASE_IRQ; 730 if (irq >= s->num_irq) 731 goto bad_reg; 732 res = 0; 733 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 734 for (i = 0; i < 8; i++) { 735 if (s->security_extn && !attrs.secure && 736 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 737 continue; /* Ignore Non-secure access of Group0 IRQ */ 738 } 739 740 if (GIC_DIST_TEST_ACTIVE(irq + i, mask)) { 741 res |= (1 << i); 742 } 743 } 744 } else if (offset < 0x800) { 745 /* Interrupt Priority. */ 746 irq = (offset - 0x400) + GIC_BASE_IRQ; 747 if (irq >= s->num_irq) 748 goto bad_reg; 749 res = gic_dist_get_priority(s, cpu, irq, attrs); 750 } else if (offset < 0xc00) { 751 /* Interrupt CPU Target. */ 752 if (s->num_cpu == 1 && s->revision != REV_11MPCORE) { 753 /* For uniprocessor GICs these RAZ/WI */ 754 res = 0; 755 } else { 756 irq = (offset - 0x800) + GIC_BASE_IRQ; 757 if (irq >= s->num_irq) { 758 goto bad_reg; 759 } 760 if (irq < 29 && s->revision == REV_11MPCORE) { 761 res = 0; 762 } else if (irq < GIC_INTERNAL) { 763 res = cm; 764 } else { 765 res = GIC_DIST_TARGET(irq); 766 } 767 } 768 } else if (offset < 0xf00) { 769 /* Interrupt Configuration. */ 770 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 771 if (irq >= s->num_irq) 772 goto bad_reg; 773 res = 0; 774 for (i = 0; i < 4; i++) { 775 if (s->security_extn && !attrs.secure && 776 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 777 continue; /* Ignore Non-secure access of Group0 IRQ */ 778 } 779 780 if (GIC_DIST_TEST_MODEL(irq + i)) { 781 res |= (1 << (i * 2)); 782 } 783 if (GIC_DIST_TEST_EDGE_TRIGGER(irq + i)) { 784 res |= (2 << (i * 2)); 785 } 786 } 787 } else if (offset < 0xf10) { 788 goto bad_reg; 789 } else if (offset < 0xf30) { 790 if (s->revision == REV_11MPCORE) { 791 goto bad_reg; 792 } 793 794 if (offset < 0xf20) { 795 /* GICD_CPENDSGIRn */ 796 irq = (offset - 0xf10); 797 } else { 798 irq = (offset - 0xf20); 799 /* GICD_SPENDSGIRn */ 800 } 801 802 if (s->security_extn && !attrs.secure && 803 !GIC_DIST_TEST_GROUP(irq, 1 << cpu)) { 804 res = 0; /* Ignore Non-secure access of Group0 IRQ */ 805 } else { 806 res = s->sgi_pending[irq][cpu]; 807 } 808 } else if (offset < 0xfd0) { 809 goto bad_reg; 810 } else if (offset < 0x1000) { 811 if (offset & 3) { 812 res = 0; 813 } else { 814 switch (s->revision) { 815 case REV_11MPCORE: 816 res = gic_id_11mpcore[(offset - 0xfd0) >> 2]; 817 break; 818 case 1: 819 res = gic_id_gicv1[(offset - 0xfd0) >> 2]; 820 break; 821 case 2: 822 res = gic_id_gicv2[(offset - 0xfd0) >> 2]; 823 break; 824 default: 825 res = 0; 826 } 827 } 828 } else { 829 g_assert_not_reached(); 830 } 831 return res; 832 bad_reg: 833 qemu_log_mask(LOG_GUEST_ERROR, 834 "gic_dist_readb: Bad offset %x\n", (int)offset); 835 return 0; 836 } 837 838 static MemTxResult gic_dist_read(void *opaque, hwaddr offset, uint64_t *data, 839 unsigned size, MemTxAttrs attrs) 840 { 841 switch (size) { 842 case 1: 843 *data = gic_dist_readb(opaque, offset, attrs); 844 return MEMTX_OK; 845 case 2: 846 *data = gic_dist_readb(opaque, offset, attrs); 847 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 848 return MEMTX_OK; 849 case 4: 850 *data = gic_dist_readb(opaque, offset, attrs); 851 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 852 *data |= gic_dist_readb(opaque, offset + 2, attrs) << 16; 853 *data |= gic_dist_readb(opaque, offset + 3, attrs) << 24; 854 return MEMTX_OK; 855 default: 856 return MEMTX_ERROR; 857 } 858 } 859 860 static void gic_dist_writeb(void *opaque, hwaddr offset, 861 uint32_t value, MemTxAttrs attrs) 862 { 863 GICState *s = (GICState *)opaque; 864 int irq; 865 int i; 866 int cpu; 867 868 cpu = gic_get_current_cpu(s); 869 if (offset < 0x100) { 870 if (offset == 0) { 871 if (s->security_extn && !attrs.secure) { 872 /* NS version is just an alias of the S version's bit 1 */ 873 s->ctlr = deposit32(s->ctlr, 1, 1, value); 874 } else if (gic_has_groups(s)) { 875 s->ctlr = value & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1); 876 } else { 877 s->ctlr = value & GICD_CTLR_EN_GRP0; 878 } 879 DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n", 880 s->ctlr & GICD_CTLR_EN_GRP0 ? "En" : "Dis", 881 s->ctlr & GICD_CTLR_EN_GRP1 ? "En" : "Dis"); 882 } else if (offset < 4) { 883 /* ignored. */ 884 } else if (offset >= 0x80) { 885 /* Interrupt Group Registers: RAZ/WI for NS access to secure 886 * GIC, or for GICs without groups. 887 */ 888 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 889 /* Every byte offset holds 8 group status bits */ 890 irq = (offset - 0x80) * 8 + GIC_BASE_IRQ; 891 if (irq >= s->num_irq) { 892 goto bad_reg; 893 } 894 for (i = 0; i < 8; i++) { 895 /* Group bits are banked for private interrupts */ 896 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 897 if (value & (1 << i)) { 898 /* Group1 (Non-secure) */ 899 GIC_DIST_SET_GROUP(irq + i, cm); 900 } else { 901 /* Group0 (Secure) */ 902 GIC_DIST_CLEAR_GROUP(irq + i, cm); 903 } 904 } 905 } 906 } else { 907 goto bad_reg; 908 } 909 } else if (offset < 0x180) { 910 /* Interrupt Set Enable. */ 911 irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; 912 if (irq >= s->num_irq) 913 goto bad_reg; 914 if (irq < GIC_NR_SGIS) { 915 value = 0xff; 916 } 917 918 for (i = 0; i < 8; i++) { 919 if (value & (1 << i)) { 920 int mask = 921 (irq < GIC_INTERNAL) ? (1 << cpu) 922 : GIC_DIST_TARGET(irq + i); 923 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 924 925 if (s->security_extn && !attrs.secure && 926 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 927 continue; /* Ignore Non-secure access of Group0 IRQ */ 928 } 929 930 if (!GIC_DIST_TEST_ENABLED(irq + i, cm)) { 931 DPRINTF("Enabled IRQ %d\n", irq + i); 932 trace_gic_enable_irq(irq + i); 933 } 934 GIC_DIST_SET_ENABLED(irq + i, cm); 935 /* If a raised level triggered IRQ enabled then mark 936 is as pending. */ 937 if (GIC_DIST_TEST_LEVEL(irq + i, mask) 938 && !GIC_DIST_TEST_EDGE_TRIGGER(irq + i)) { 939 DPRINTF("Set %d pending mask %x\n", irq + i, mask); 940 GIC_DIST_SET_PENDING(irq + i, mask); 941 } 942 } 943 } 944 } else if (offset < 0x200) { 945 /* Interrupt Clear Enable. */ 946 irq = (offset - 0x180) * 8 + GIC_BASE_IRQ; 947 if (irq >= s->num_irq) 948 goto bad_reg; 949 if (irq < GIC_NR_SGIS) { 950 value = 0; 951 } 952 953 for (i = 0; i < 8; i++) { 954 if (value & (1 << i)) { 955 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 956 957 if (s->security_extn && !attrs.secure && 958 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 959 continue; /* Ignore Non-secure access of Group0 IRQ */ 960 } 961 962 if (GIC_DIST_TEST_ENABLED(irq + i, cm)) { 963 DPRINTF("Disabled IRQ %d\n", irq + i); 964 trace_gic_disable_irq(irq + i); 965 } 966 GIC_DIST_CLEAR_ENABLED(irq + i, cm); 967 } 968 } 969 } else if (offset < 0x280) { 970 /* Interrupt Set Pending. */ 971 irq = (offset - 0x200) * 8 + GIC_BASE_IRQ; 972 if (irq >= s->num_irq) 973 goto bad_reg; 974 if (irq < GIC_NR_SGIS) { 975 value = 0; 976 } 977 978 for (i = 0; i < 8; i++) { 979 if (value & (1 << i)) { 980 if (s->security_extn && !attrs.secure && 981 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 982 continue; /* Ignore Non-secure access of Group0 IRQ */ 983 } 984 985 GIC_DIST_SET_PENDING(irq + i, GIC_DIST_TARGET(irq + i)); 986 } 987 } 988 } else if (offset < 0x300) { 989 /* Interrupt Clear Pending. */ 990 irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; 991 if (irq >= s->num_irq) 992 goto bad_reg; 993 if (irq < GIC_NR_SGIS) { 994 value = 0; 995 } 996 997 for (i = 0; i < 8; i++) { 998 if (s->security_extn && !attrs.secure && 999 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 1000 continue; /* Ignore Non-secure access of Group0 IRQ */ 1001 } 1002 1003 /* ??? This currently clears the pending bit for all CPUs, even 1004 for per-CPU interrupts. It's unclear whether this is the 1005 corect behavior. */ 1006 if (value & (1 << i)) { 1007 GIC_DIST_CLEAR_PENDING(irq + i, ALL_CPU_MASK); 1008 } 1009 } 1010 } else if (offset < 0x400) { 1011 /* Interrupt Active. */ 1012 goto bad_reg; 1013 } else if (offset < 0x800) { 1014 /* Interrupt Priority. */ 1015 irq = (offset - 0x400) + GIC_BASE_IRQ; 1016 if (irq >= s->num_irq) 1017 goto bad_reg; 1018 gic_dist_set_priority(s, cpu, irq, value, attrs); 1019 } else if (offset < 0xc00) { 1020 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the 1021 * annoying exception of the 11MPCore's GIC. 1022 */ 1023 if (s->num_cpu != 1 || s->revision == REV_11MPCORE) { 1024 irq = (offset - 0x800) + GIC_BASE_IRQ; 1025 if (irq >= s->num_irq) { 1026 goto bad_reg; 1027 } 1028 if (irq < 29 && s->revision == REV_11MPCORE) { 1029 value = 0; 1030 } else if (irq < GIC_INTERNAL) { 1031 value = ALL_CPU_MASK; 1032 } 1033 s->irq_target[irq] = value & ALL_CPU_MASK; 1034 } 1035 } else if (offset < 0xf00) { 1036 /* Interrupt Configuration. */ 1037 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 1038 if (irq >= s->num_irq) 1039 goto bad_reg; 1040 if (irq < GIC_NR_SGIS) 1041 value |= 0xaa; 1042 for (i = 0; i < 4; i++) { 1043 if (s->security_extn && !attrs.secure && 1044 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 1045 continue; /* Ignore Non-secure access of Group0 IRQ */ 1046 } 1047 1048 if (s->revision == REV_11MPCORE) { 1049 if (value & (1 << (i * 2))) { 1050 GIC_DIST_SET_MODEL(irq + i); 1051 } else { 1052 GIC_DIST_CLEAR_MODEL(irq + i); 1053 } 1054 } 1055 if (value & (2 << (i * 2))) { 1056 GIC_DIST_SET_EDGE_TRIGGER(irq + i); 1057 } else { 1058 GIC_DIST_CLEAR_EDGE_TRIGGER(irq + i); 1059 } 1060 } 1061 } else if (offset < 0xf10) { 1062 /* 0xf00 is only handled for 32-bit writes. */ 1063 goto bad_reg; 1064 } else if (offset < 0xf20) { 1065 /* GICD_CPENDSGIRn */ 1066 if (s->revision == REV_11MPCORE) { 1067 goto bad_reg; 1068 } 1069 irq = (offset - 0xf10); 1070 1071 if (!s->security_extn || attrs.secure || 1072 GIC_DIST_TEST_GROUP(irq, 1 << cpu)) { 1073 s->sgi_pending[irq][cpu] &= ~value; 1074 if (s->sgi_pending[irq][cpu] == 0) { 1075 GIC_DIST_CLEAR_PENDING(irq, 1 << cpu); 1076 } 1077 } 1078 } else if (offset < 0xf30) { 1079 /* GICD_SPENDSGIRn */ 1080 if (s->revision == REV_11MPCORE) { 1081 goto bad_reg; 1082 } 1083 irq = (offset - 0xf20); 1084 1085 if (!s->security_extn || attrs.secure || 1086 GIC_DIST_TEST_GROUP(irq, 1 << cpu)) { 1087 GIC_DIST_SET_PENDING(irq, 1 << cpu); 1088 s->sgi_pending[irq][cpu] |= value; 1089 } 1090 } else { 1091 goto bad_reg; 1092 } 1093 gic_update(s); 1094 return; 1095 bad_reg: 1096 qemu_log_mask(LOG_GUEST_ERROR, 1097 "gic_dist_writeb: Bad offset %x\n", (int)offset); 1098 } 1099 1100 static void gic_dist_writew(void *opaque, hwaddr offset, 1101 uint32_t value, MemTxAttrs attrs) 1102 { 1103 gic_dist_writeb(opaque, offset, value & 0xff, attrs); 1104 gic_dist_writeb(opaque, offset + 1, value >> 8, attrs); 1105 } 1106 1107 static void gic_dist_writel(void *opaque, hwaddr offset, 1108 uint32_t value, MemTxAttrs attrs) 1109 { 1110 GICState *s = (GICState *)opaque; 1111 if (offset == 0xf00) { 1112 int cpu; 1113 int irq; 1114 int mask; 1115 int target_cpu; 1116 1117 cpu = gic_get_current_cpu(s); 1118 irq = value & 0x3ff; 1119 switch ((value >> 24) & 3) { 1120 case 0: 1121 mask = (value >> 16) & ALL_CPU_MASK; 1122 break; 1123 case 1: 1124 mask = ALL_CPU_MASK ^ (1 << cpu); 1125 break; 1126 case 2: 1127 mask = 1 << cpu; 1128 break; 1129 default: 1130 DPRINTF("Bad Soft Int target filter\n"); 1131 mask = ALL_CPU_MASK; 1132 break; 1133 } 1134 GIC_DIST_SET_PENDING(irq, mask); 1135 target_cpu = ctz32(mask); 1136 while (target_cpu < GIC_NCPU) { 1137 s->sgi_pending[irq][target_cpu] |= (1 << cpu); 1138 mask &= ~(1 << target_cpu); 1139 target_cpu = ctz32(mask); 1140 } 1141 gic_update(s); 1142 return; 1143 } 1144 gic_dist_writew(opaque, offset, value & 0xffff, attrs); 1145 gic_dist_writew(opaque, offset + 2, value >> 16, attrs); 1146 } 1147 1148 static MemTxResult gic_dist_write(void *opaque, hwaddr offset, uint64_t data, 1149 unsigned size, MemTxAttrs attrs) 1150 { 1151 switch (size) { 1152 case 1: 1153 gic_dist_writeb(opaque, offset, data, attrs); 1154 return MEMTX_OK; 1155 case 2: 1156 gic_dist_writew(opaque, offset, data, attrs); 1157 return MEMTX_OK; 1158 case 4: 1159 gic_dist_writel(opaque, offset, data, attrs); 1160 return MEMTX_OK; 1161 default: 1162 return MEMTX_ERROR; 1163 } 1164 } 1165 1166 static inline uint32_t gic_apr_ns_view(GICState *s, int cpu, int regno) 1167 { 1168 /* Return the Nonsecure view of GICC_APR<regno>. This is the 1169 * second half of GICC_NSAPR. 1170 */ 1171 switch (GIC_MIN_BPR) { 1172 case 0: 1173 if (regno < 2) { 1174 return s->nsapr[regno + 2][cpu]; 1175 } 1176 break; 1177 case 1: 1178 if (regno == 0) { 1179 return s->nsapr[regno + 1][cpu]; 1180 } 1181 break; 1182 case 2: 1183 if (regno == 0) { 1184 return extract32(s->nsapr[0][cpu], 16, 16); 1185 } 1186 break; 1187 case 3: 1188 if (regno == 0) { 1189 return extract32(s->nsapr[0][cpu], 8, 8); 1190 } 1191 break; 1192 default: 1193 g_assert_not_reached(); 1194 } 1195 return 0; 1196 } 1197 1198 static inline void gic_apr_write_ns_view(GICState *s, int cpu, int regno, 1199 uint32_t value) 1200 { 1201 /* Write the Nonsecure view of GICC_APR<regno>. */ 1202 switch (GIC_MIN_BPR) { 1203 case 0: 1204 if (regno < 2) { 1205 s->nsapr[regno + 2][cpu] = value; 1206 } 1207 break; 1208 case 1: 1209 if (regno == 0) { 1210 s->nsapr[regno + 1][cpu] = value; 1211 } 1212 break; 1213 case 2: 1214 if (regno == 0) { 1215 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 16, 16, value); 1216 } 1217 break; 1218 case 3: 1219 if (regno == 0) { 1220 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 8, 8, value); 1221 } 1222 break; 1223 default: 1224 g_assert_not_reached(); 1225 } 1226 } 1227 1228 static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset, 1229 uint64_t *data, MemTxAttrs attrs) 1230 { 1231 switch (offset) { 1232 case 0x00: /* Control */ 1233 *data = gic_get_cpu_control(s, cpu, attrs); 1234 break; 1235 case 0x04: /* Priority mask */ 1236 *data = gic_get_priority_mask(s, cpu, attrs); 1237 break; 1238 case 0x08: /* Binary Point */ 1239 if (s->security_extn && !attrs.secure) { 1240 if (s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) { 1241 /* NS view of BPR when CBPR is 1 */ 1242 *data = MIN(s->bpr[cpu] + 1, 7); 1243 } else { 1244 /* BPR is banked. Non-secure copy stored in ABPR. */ 1245 *data = s->abpr[cpu]; 1246 } 1247 } else { 1248 *data = s->bpr[cpu]; 1249 } 1250 break; 1251 case 0x0c: /* Acknowledge */ 1252 *data = gic_acknowledge_irq(s, cpu, attrs); 1253 break; 1254 case 0x14: /* Running Priority */ 1255 *data = gic_get_running_priority(s, cpu, attrs); 1256 break; 1257 case 0x18: /* Highest Pending Interrupt */ 1258 *data = gic_get_current_pending_irq(s, cpu, attrs); 1259 break; 1260 case 0x1c: /* Aliased Binary Point */ 1261 /* GIC v2, no security: ABPR 1262 * GIC v1, no security: not implemented (RAZ/WI) 1263 * With security extensions, secure access: ABPR (alias of NS BPR) 1264 * With security extensions, nonsecure access: RAZ/WI 1265 */ 1266 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 1267 *data = 0; 1268 } else { 1269 *data = s->abpr[cpu]; 1270 } 1271 break; 1272 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 1273 { 1274 int regno = (offset - 0xd0) / 4; 1275 1276 if (regno >= GIC_NR_APRS || s->revision != 2) { 1277 *data = 0; 1278 } else if (s->security_extn && !attrs.secure) { 1279 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ 1280 *data = gic_apr_ns_view(s, regno, cpu); 1281 } else { 1282 *data = s->apr[regno][cpu]; 1283 } 1284 break; 1285 } 1286 case 0xe0: case 0xe4: case 0xe8: case 0xec: 1287 { 1288 int regno = (offset - 0xe0) / 4; 1289 1290 if (regno >= GIC_NR_APRS || s->revision != 2 || !gic_has_groups(s) || 1291 (s->security_extn && !attrs.secure)) { 1292 *data = 0; 1293 } else { 1294 *data = s->nsapr[regno][cpu]; 1295 } 1296 break; 1297 } 1298 default: 1299 qemu_log_mask(LOG_GUEST_ERROR, 1300 "gic_cpu_read: Bad offset %x\n", (int)offset); 1301 *data = 0; 1302 break; 1303 } 1304 return MEMTX_OK; 1305 } 1306 1307 static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset, 1308 uint32_t value, MemTxAttrs attrs) 1309 { 1310 switch (offset) { 1311 case 0x00: /* Control */ 1312 gic_set_cpu_control(s, cpu, value, attrs); 1313 break; 1314 case 0x04: /* Priority mask */ 1315 gic_set_priority_mask(s, cpu, value, attrs); 1316 break; 1317 case 0x08: /* Binary Point */ 1318 if (s->security_extn && !attrs.secure) { 1319 if (s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) { 1320 /* WI when CBPR is 1 */ 1321 return MEMTX_OK; 1322 } else { 1323 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 1324 } 1325 } else { 1326 s->bpr[cpu] = MAX(value & 0x7, GIC_MIN_BPR); 1327 } 1328 break; 1329 case 0x10: /* End Of Interrupt */ 1330 gic_complete_irq(s, cpu, value & 0x3ff, attrs); 1331 return MEMTX_OK; 1332 case 0x1c: /* Aliased Binary Point */ 1333 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 1334 /* unimplemented, or NS access: RAZ/WI */ 1335 return MEMTX_OK; 1336 } else { 1337 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 1338 } 1339 break; 1340 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 1341 { 1342 int regno = (offset - 0xd0) / 4; 1343 1344 if (regno >= GIC_NR_APRS || s->revision != 2) { 1345 return MEMTX_OK; 1346 } 1347 if (s->security_extn && !attrs.secure) { 1348 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ 1349 gic_apr_write_ns_view(s, regno, cpu, value); 1350 } else { 1351 s->apr[regno][cpu] = value; 1352 } 1353 break; 1354 } 1355 case 0xe0: case 0xe4: case 0xe8: case 0xec: 1356 { 1357 int regno = (offset - 0xe0) / 4; 1358 1359 if (regno >= GIC_NR_APRS || s->revision != 2) { 1360 return MEMTX_OK; 1361 } 1362 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 1363 return MEMTX_OK; 1364 } 1365 s->nsapr[regno][cpu] = value; 1366 break; 1367 } 1368 case 0x1000: 1369 /* GICC_DIR */ 1370 gic_deactivate_irq(s, cpu, value & 0x3ff, attrs); 1371 break; 1372 default: 1373 qemu_log_mask(LOG_GUEST_ERROR, 1374 "gic_cpu_write: Bad offset %x\n", (int)offset); 1375 return MEMTX_OK; 1376 } 1377 gic_update(s); 1378 return MEMTX_OK; 1379 } 1380 1381 /* Wrappers to read/write the GIC CPU interface for the current CPU */ 1382 static MemTxResult gic_thiscpu_read(void *opaque, hwaddr addr, uint64_t *data, 1383 unsigned size, MemTxAttrs attrs) 1384 { 1385 GICState *s = (GICState *)opaque; 1386 return gic_cpu_read(s, gic_get_current_cpu(s), addr, data, attrs); 1387 } 1388 1389 static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, 1390 uint64_t value, unsigned size, 1391 MemTxAttrs attrs) 1392 { 1393 GICState *s = (GICState *)opaque; 1394 return gic_cpu_write(s, gic_get_current_cpu(s), addr, value, attrs); 1395 } 1396 1397 /* Wrappers to read/write the GIC CPU interface for a specific CPU. 1398 * These just decode the opaque pointer into GICState* + cpu id. 1399 */ 1400 static MemTxResult gic_do_cpu_read(void *opaque, hwaddr addr, uint64_t *data, 1401 unsigned size, MemTxAttrs attrs) 1402 { 1403 GICState **backref = (GICState **)opaque; 1404 GICState *s = *backref; 1405 int id = (backref - s->backref); 1406 return gic_cpu_read(s, id, addr, data, attrs); 1407 } 1408 1409 static MemTxResult gic_do_cpu_write(void *opaque, hwaddr addr, 1410 uint64_t value, unsigned size, 1411 MemTxAttrs attrs) 1412 { 1413 GICState **backref = (GICState **)opaque; 1414 GICState *s = *backref; 1415 int id = (backref - s->backref); 1416 return gic_cpu_write(s, id, addr, value, attrs); 1417 } 1418 1419 static const MemoryRegionOps gic_ops[2] = { 1420 { 1421 .read_with_attrs = gic_dist_read, 1422 .write_with_attrs = gic_dist_write, 1423 .endianness = DEVICE_NATIVE_ENDIAN, 1424 }, 1425 { 1426 .read_with_attrs = gic_thiscpu_read, 1427 .write_with_attrs = gic_thiscpu_write, 1428 .endianness = DEVICE_NATIVE_ENDIAN, 1429 } 1430 }; 1431 1432 static const MemoryRegionOps gic_cpu_ops = { 1433 .read_with_attrs = gic_do_cpu_read, 1434 .write_with_attrs = gic_do_cpu_write, 1435 .endianness = DEVICE_NATIVE_ENDIAN, 1436 }; 1437 1438 /* This function is used by nvic model */ 1439 void gic_init_irqs_and_distributor(GICState *s) 1440 { 1441 gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops); 1442 } 1443 1444 static void arm_gic_realize(DeviceState *dev, Error **errp) 1445 { 1446 /* Device instance realize function for the GIC sysbus device */ 1447 int i; 1448 GICState *s = ARM_GIC(dev); 1449 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1450 ARMGICClass *agc = ARM_GIC_GET_CLASS(s); 1451 Error *local_err = NULL; 1452 1453 agc->parent_realize(dev, &local_err); 1454 if (local_err) { 1455 error_propagate(errp, local_err); 1456 return; 1457 } 1458 1459 if (kvm_enabled() && !kvm_arm_supports_user_irq()) { 1460 error_setg(errp, "KVM with user space irqchip only works when the " 1461 "host kernel supports KVM_CAP_ARM_USER_IRQ"); 1462 return; 1463 } 1464 1465 /* This creates distributor and main CPU interface (s->cpuiomem[0]) */ 1466 gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops); 1467 1468 /* Extra core-specific regions for the CPU interfaces. This is 1469 * necessary for "franken-GIC" implementations, for example on 1470 * Exynos 4. 1471 * NB that the memory region size of 0x100 applies for the 11MPCore 1472 * and also cores following the GIC v1 spec (ie A9). 1473 * GIC v2 defines a larger memory region (0x1000) so this will need 1474 * to be extended when we implement A15. 1475 */ 1476 for (i = 0; i < s->num_cpu; i++) { 1477 s->backref[i] = s; 1478 memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops, 1479 &s->backref[i], "gic_cpu", 0x100); 1480 sysbus_init_mmio(sbd, &s->cpuiomem[i+1]); 1481 } 1482 } 1483 1484 static void arm_gic_class_init(ObjectClass *klass, void *data) 1485 { 1486 DeviceClass *dc = DEVICE_CLASS(klass); 1487 ARMGICClass *agc = ARM_GIC_CLASS(klass); 1488 1489 device_class_set_parent_realize(dc, arm_gic_realize, &agc->parent_realize); 1490 } 1491 1492 static const TypeInfo arm_gic_info = { 1493 .name = TYPE_ARM_GIC, 1494 .parent = TYPE_ARM_GIC_COMMON, 1495 .instance_size = sizeof(GICState), 1496 .class_init = arm_gic_class_init, 1497 .class_size = sizeof(ARMGICClass), 1498 }; 1499 1500 static void arm_gic_register_types(void) 1501 { 1502 type_register_static(&arm_gic_info); 1503 } 1504 1505 type_init(arm_gic_register_types) 1506